JPS6313521A - Pulse density modulator - Google Patents

Abstract

PURPOSE:To obtain a pulse density modulator whose circuit design is easy by connecting plural stages of means converting a signal into a PCM signal having a few bit length and a high clock frequency in cascade. CONSTITUTION:Data bit length reduction circuits 1-4 are connected in cascade over plural stages and a quantized PCM signal X is inputted to an adder 11 of the data bit length decrease circuit 1 of the 1st stage. Then a pulse density modulation signal Yn of the PCM signal X is obtained at a number of bits limiting circuit 45 of the data bit length decrease circuit 4 of the n-th stage the same as the principle of a conventional puse density modulator. The data with a long bit length is processed comparatively at a low speed in the initial stage of the plural stages, while the final stage of the plural stages applies the processing of the data having a short bit length at a comparatively high speed and the circuit constitution of an adder and a memory or the like is simplified. Thus, the circuit design of the pulse density modulator is facilitated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to pulse density modulators.

[Prior Art] FIGS. 2 and 4 are block diagrams of a pulse density modulator proposed in Japanese Patent Application No. 60-298451.
FIG. 3 is a diagram showing input and output waveforms of the pulse density modulators of FIGS. 2 and 4. FIG. Hereinafter, the pulse density modulators shown in FIGS. 2 and 4 will be referred to as a first conventional example and a second conventional example, respectively.

In the following, the PCM signal X refers to a signal that has a predetermined bit length and is expressed by predetermined encoding of information such as amplitude size including positive and negative signs, and the pulse density modulation signal refers to the PCM signal described above. A signal in which the density of output pulses changes in a predetermined relationship in response to information on X.

The pulse density modulator of FIGS. 2 and 4 is a two's complement or offset binary signal that indicates the magnitude of amplitude with a predetermined bit length and is a quantized PC, as shown in FIG.
This modulator converts the M signal X into a pulse density modulation signal Ya or Yb whose output pulse density increases in proportion to the magnitude of the amplitude.
is shown as a quantized sine wave waveform for convenience.

In FIG. 2, 11 is an adder, and 12 and 16 are memories that take in data using a clock φ. Further, I8 is a positive/negative determination circuit that determines whether the output data S of the adder 11 is positive or negative and outputs only the positive or negative determination result Ya. In the case represented by , it is possible to determine whether the input data is positive or negative by determining only the most significant bit of the input data.

In FIG. 2, the following equation holds.

5=X-Ya-Z-'+S-Z'...
(1) S=Ya+N...
・(2) Here, Z''-'=cosωT-jsinωT
...(3), where ω is the angular frequency of the input signal,
T is the clock period. In addition, N in equation (2) is the noise generated when the output S of the adder 11 is obtained by the sign-only output Ya in the sign determination circuit 18, that is, the output S of the adder 11 is quantized to 1 bit. This is noise generated due to the input data S of the positive/negative determination circuit I8.
By eliminating S from the above equations (1) and (2), which corresponds to the difference between
, , , (4) is obtained.

In equation (4), when ωT is sufficiently small, that is, when the angular frequency ω of the input signal X is low or the clock period T is short, Z-1 takes a value close to l.

Therefore, I-Z-' length is 0, and in equation (4). When l-Z'#O, Ya≠X. here,
As mentioned above, X is input data having a bit length of 2 bits or more, and Ya is 1 bit data. Therefore, by comparing the frequency of the clock φ with the frequency of the input signal X and selecting a sufficiently high frequency, a pulse density modulator can be realized.

FIG. 4 is a block diagram of a pulse density modulator that is an improved version of the pulse density modulator shown in FIG. 2. In FIG. 4, the same parts as in FIG. 2 are given the same reference numerals. In FIG. 4, 13 is an adder, 14 is a memory that takes in data by clock φ, and 17 is an adder.
is a double multiplier circuit. Now, assuming that the outputs of the adders 11 and 13 are S, S2, respectively, and the output of the positive/negative determining circuit 18 is Yb, the following equation holds true in FIG.

X+S, -Z-'-Yb-Z'=S+...(
5) S 1 ・Z− Violet+ 82 ・Z′−
2Yb-Z'=82...(6)S,-Yb
+N...(7) Here, Z'=cosωT-jsinωT-(8
), ω is the angular frequency of the input signal, and T is the clock period. Also, N in equation (7) is as in equation (2) above,
This is noise due to quantization.

If S, , S2 are eliminated from equations (5), (6), and (7), Yb=Z'・X-N(l-Z-02...(
9) is obtained.

Similarly to equation (4), when ωT is sufficiently small, that is, when the angular frequency ω of the input signal X is low and the clock period T is short, 1−Z′ 0. Further, the coefficient Zl of X in equation (9) represents a delay by the period T of the clock φ, and has no effect on the noise component or the frequency characteristics of the input/output signal. Therefore, if the frequency of the clock φ is made sufficiently high compared to the frequency of the input signal X, a pulse density modulator similar to the pulse density modulator shown in FIG. 2 can be realized.

[Problems to be Solved by the Invention] However, in the first and second conventional examples described above, when converting the PCM input signal into a layered pulse density modulation signal, the clock φ of the modulator is The frequency of P
There is a problem that the wave number of the CM input must be sufficiently high compared to the wave number of the PCM input signal layer. In other words, the modulator needs to process data with a long bit length at a high speed compared to the wave number of the PCM input signal layer. Ta.

[Object of the Invention] An object of the present invention is to convert the PCM input signal layer into a pulse density modulated signal by converting the PCM input signal layer into a PCM signal having a long bit length in the modulator
Input input signal layer - PCM input signal layer that can process data at relatively low speed and has a short bit length.
The object of the present invention is to provide a pulse density modulator that can perform data processing at relatively high speed and that facilitates circuit design.

[Configuration of the Invention] The present invention provides a pulse density modulator that converts a PCM signal into a pulse density modulation signal in which the pulse density changes in accordance with information contained in the PCM signal. Means for converting into a PCM signal having a bit length smaller than the bit length of the input PCM signal, a clock frequency higher than the clock frequency of the input PCM signal, and having information equivalent to the input PCM signal. are connected in cascade in multiple stages and converted into a pulse density modulated signal consisting of a pulse train having a bit length of 1 pit.

[Embodiment] FIG. 1 is a block diagram of a pulse density modulator that is an embodiment of the present invention. Components in FIG. 1 that are the same as those in FIG. 4 are designated by the same reference numerals.

In the pulse density modulator of the present invention, the positive/negative determination circuit 18 of the conventional pulse density modulator shown in FIG. The pulse density modulator is realized by using a pulse density modulator as a data bit length reduction circuit and further cascading a plurality of stages of this data bit length reduction circuit.

In the following example, the PCM signal signal layer is a signal representing the magnitude of amplitude including positive and negative signs with a predetermined bit length, and the most significant bit is the bit representing the sign of the amplitude, counting from the most significant bit. The bits below 2 bits up to the least significant bit are bits indicating the magnitude of the amplitude. Further, the output pulse density modulation signal Yn is a signal whose output pulse density increases in proportion to the magnitude of the amplitude.

In FIG. 1, 1, 2.3, and 4 are data bit length reduction circuits, and each data bit length reduction circuit 1, 2.3, and 4 have the same configuration.

In the data bit length reduction circuit l, the PCM of bit length a1 bits is adopted and inputted to this pulse density modulator.
The signal is input to the signal layer adder 11, and the adder 11 inputs the signal to the PC.
Add the M signal X and the output data of the memory 12, which will be described later,
Further, output data of the memory 16, which will be described later, is subtracted from the addition result to obtain output data S of the adder 11 having a bit length of .

is output to the memory 12. Memory 12 is the input PC
After latching the input data S1 in synchronization with the clock φ1 having a higher frequency than the M signal signal layer wave number,
Data having a bit length CI bits is output to adder 13 and adder 1.1.

The adder 13 adds the input data having the bit length C and the output data of the memory 14, which will be described later, and further subtracts the output data of the doubler circuit I7, which will be described later, from the addition result to obtain the bit length d. .

Output data S2 of adder 13 with bits and memory 1
4 and the bit number limiting circuit 15.

The memory 14 latches the input data S in synchronization with the clock φ, and then outputs it to the adder 13. On the other hand, the bit number limiting circuit 15 extracts only the predetermined high-order bits counting from the most significant bit from the input data with a bit length d1 bits, and selects the bit length of the a bits, which is a predetermined number of bits smaller than the a1 bits. The converted data Y1 is outputted to the memory 16 and the adder 21 of the data bit length reduction circuit 2 at the next stage. After the memory 16 latches the input data Y1 in synchronization with the clock φ, the adder 1
The frequency of the input data is output to the 1 and 2 multiplier circuits I7, and the 2 multiplier circuit 17 multiplies the frequency of the input data by 2 and outputs the result to the adder 13.

Hereinafter, the data bit length reduction circuits 2.3 and 4 are constructed in the same manner as the data bit length reduction circuit 1, and each memory 22, 24, and 26 of the data bit length reduction circuit 2 has a frequency higher than the frequency of the clock φ1. A clock φ is supplied to each memory 32 .
A clock φn-1 having a frequency higher than the frequency of the clock φ2 is supplied to 34 and 36, and a clock φn-1 having a frequency higher than the frequency of the clock φn- is supplied to each memory 4, 2, 44 and 46 of the data bit length reduction circuit 4. A clock φn having φn is supplied. Therefore, the clock frequency φ4 . φ
7. The following equation holds true for φn-1 and φn.

fx<φ, 〈φ2〈...〈φn-1kuφn
=.(10) However, fX is the input PCM signal signal layer wave number, and ■ is a natural number.

In addition, in the data bit length reduction circuit 2, 21 and 2
3 is an adder, and 27 is a doubling circuit.

Further, 25 is a bit number limiting circuit, and the bit number limiting circuit 25 extracts only a predetermined upper bit counting from the most significant bit from the output data of the adder 23 having a bit length d2 bits, and extracts a predetermined upper bit from the output data of the adder 23 having a bit length d2 bits. It is converted into data Y having a bit length of a3 bits, which is less by a predetermined number of bits, and output to the memory 26 and the adder of the data bit length reduction circuit in the next stage.

Note that each output data of the adder 21 and the memory 22 has a bit length of d, bits and C, bits, respectively.

In the data bit length reduction circuit 3, 31 and 33 are adders, and 37 is a doubling circuit. Further, 35 is a bit number limiting circuit, and the bit number limiting circuit 35 has a bit length dn.
-, from the output data of the adder 33 having bits, only a predetermined upper bit is extracted counting from the most significant bit, and a
It is converted into data Yn-, which has a bit length of an bits, which is smaller than n-1 bits by a predetermined number of bits, and is sent to the memory 36 and the adder 4 of the data bit length reduction circuit 4 in the final stage.
Output to 1. Note that each output data of the adder 31 and the memory 32 is bn-, bit, and cn-, respectively.

It has a bit length of bits.

In the data bit length reduction circuit 4, 41 and 43 are adders, and 47 is a doubling circuit. Further, 45 is a bit number limiting circuit, and the bit number limiting circuit 45 has a bit length of 1.
From the output data of the adder 43 having bits, extract only the most significant bits counting from the most significant bit, determine whether the output data is positive or negative, and convert it into data Yn with a bit length of 1 bit, which is a positive or negative determination result. At the same time, data Yn is outputted as an output signal of the pulse density modulator. Note that each output data of the adder 41 and the memory 42 has a bit length of bn bits and cn bits, respectively.

~U- Therefore, each data bit length reduction circuit r, 2. s- and 4
The following equation holds true for the bit length of the output data of each adder, memory, and bit number limiting circuit.

a,〉a,〉IIIl>an-1〉an>1-11+
(11) b, >bt> ++z+ >bn, >b
n...Q2) C,>C=> Item II
I>cn-,>cn lll1(13)dl>
d,〉・・・・・・〉dn-1〉dn・・・(14)
However, n is a natural number.

As described above, the data bit length reduction circuits I, 2, 3, and 4 are connected in cascade in multiple stages, and the quantized PCM signal layer signal is sent to the adder 11 of the data bit length reduction circuit 1 in the first stage. By doing so, similar to the principle of the second conventional pulse density modulator described above, PCM is applied to the output of the bit number limiting circuit 45 of the n-th data bit length reduction circuit 4.
A signal layer pulse density modulation signal Yn is obtained.

Therefore, by performing the processing of the conventional pulse density modulator shown in FIG. 4 in multiple stages, the first stage of the multiple stages processes data with a long bit length at a relatively low speed, while In the final stage, data with a short bit length can be processed at relatively high speed. In other words, the bit length of processing in the adder, memory, etc. in the first stage must be the bit length of the input P and CM signal X, but the data processing speed must be relatively low. On the other hand, in the final stage, it is necessary to process data at a relatively high speed, but the bit length of the processing is much shorter than the bit length of the input PCM signal The circuit configuration of memory etc. can be simplified. Therefore, there is an advantage that the circuit design of the pulse density modulator is easier than in the conventional example.

Number of stages n of the data bit length reduction circuit in the above embodiment
can be appropriately selected depending on the frequency of the input PCM signal.

In the above embodiment, the second conventional pulse density modulator shown in FIG. 4 is used as the data bit length reduction circuit, but the pulse density modulator of the first conventional example shown in FIG.
Any circuit that reduces the number of bits of input data while inputting and outputting data is equivalent can be used.

This pulse density modulator is, for example, disclosed in Japanese Patent Application No. 1983.
It is composed of a pulse density modulator proposed in No. 298451 and an analog low-pass filter that limits the band of the output of the modulator, and can be used in a DA converter that converts a digital signal into an analog signal.

In the above embodiments, the PCM signal is used as a signal representing the magnitude of the width, but it is not limited to the magnitude of the amplitude, but may be used as a signal representing other information amount with a predetermined bit length. In addition, the output pulse density modulation signal Yn
is a signal whose output pulse density increases in proportion to the above amplitude, but the input P
The CM signal may be a signal in which the density of output pulses changes in a predetermined relationship in response to the amount of information contained in the signal.

[Effects of the Invention] As described in detail above, an input PCM signal is clocked by a clock having a bit length smaller than the bit length of the input PCM signal and higher than the clock frequency of the input PCM signal. has the frequency and the input P
The means for converting into a PCM signal having information equivalent to a CM signal can be connected in cascade in multiple stages and can be converted into a pulse density modulation signal consisting of a pulse signal train having a bit length of 1 bit. In the first stage, it is necessary to process data according to the bit length of the input PCM signal, but the data processing speed can be relatively low.On the other hand, in the first stage of the above means, Although it is necessary to process data at a relatively high speed, the bit length of the processing is much shorter than the bit length of the input PCM signal, and the circuit configuration of the pulse density modulator can be simplified.

Therefore, there is an advantage that the circuit design of the pulse density modulator is easier than in the conventional example.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pulse density modulator that is an embodiment of the present invention, FIG. 2 is a block diagram of a pulse density modulator that is a first conventional example, and FIG. 3 is a block diagram of a pulse density modulator that is an example of the first conventional example. FIG. 4 is a block diagram of a second conventional pulse density modulator. 1.2, 3.4... Data bit length reduction circuit, 11.
13, 21, 23, 31, 33, 41.43...Adder, 12.14, 16, 22, 24, 26, 32, 34°3
6.42, 44.46...Memory, 15.25, 35
．． 45...Bit number limiting circuit, 17.2 r:s 7
, 47...2 multiplier circuit.

Claims (1)

[Claims] (1) In a pulse density modulator that converts a PCM signal into a pulse density modulation signal in which the pulse density changes in accordance with the information contained in the PCM signal, the input PCM signal is
A PCM signal having a bit length smaller than the bit length of this input PCM signal, a clock frequency higher than the clock frequency of the input PCM signal, and having information equivalent to the input PCM signal. A pulse density modulator, characterized in that a plurality of converting means are connected in cascade and converts into a pulse density modulated signal consisting of a pulse train having a bit length of 1 bit.