JPH01232422A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce delay and to shorten an arithmetic time and to speed up processing by carrying out normalization and rounding processing in parallel in consideration of added bits. CONSTITUTION:When the quantity of shifting of normalization based upon the arithmetic result of a mantissa part part exceeds the number of added bits, a 1st execution means 19 consisting of a shifter 13, a primary encoder 15, and a LSB circuit 17 shifts the mantissa part and rounds the least significant digit bit of the mantissa part in parallel, and puts them together in one. When the quantity of shifting of normalization is less than the number of the added bits, a 2nd execution part 58 consisting of a LSB adding circuit 31, a rounding circuit 32, and a selector 33 sets the digit movement of the mantissa part caused by the rounding processing previously as the processing result of the rounding and selects one of them. In this case, the rounding process and mantissa part shifting are carried out in parallel. Thus, the normalization and rounding are processed in parallel, so the arithmetic speed is improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figure 5.6) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems One Embodiment of the Present Invention (Figures 1 to 4) Effects of the invention [(already required)] The purpose of this invention is to provide an arithmetic circuit that can speed up arithmetic processing with respect to an arithmetic circuit that performs arithmetic operations on numerical values in floating point notation. An operation that performs operations on two numbers using the floating-point notation represented by In the circuit, when the shift amount of normalization based on the operation result of the mantissa part exceeds the number of additional bits, the mantissa part is shifted, and rounding for the lowest via of the mantissa part is processed in parallel, a first execution means for synthesizing both; a shifting means for shifting the mantissa for normalization within the range of the number of appendage bits based on the result of the operation of the mantissa; and normalization based on the result of the operation of the mantissa. When the shift amount is less than or equal to the additional bits, the digit shift of the mantissa caused by rounding is calculated for each aspect as follows:
a second execution means that selects one of the results set in advance as a result of rounding processing; and a first execution means that determines whether or not the shift amount of normalization based on the calculation result of the mantissa exceeds the additional focus. and a selection means for alternatively selecting the output of the first execution means or the second execution means.

[Industrial application field]

The present invention relates to an arithmetic circuit, and more particularly to an arithmetic circuit that performs arithmetic operations on numerical values in floating point notation.

Fixed-point representation cannot represent very large numbers because the range of numbers that can be represented is narrow. Furthermore, fixed-point representation usually handles only integers, and therefore a separate notation is required to represent real numbers necessary for scientific and technical calculations. For this reason, floating point notation (float) is a combination of two numbers called mantissa and exponent.
ing point representation)
was considered.

- A floating point number in a shell, when the radix is R, is shown as follows.

(-1)'·m-R'' Here, S is a sign; when positive, 5=O1; when negative, s=1. Also, m and e are the mantissas (m
The floating point representation in a computer is a combination of fixed point representations. Note that in floating point representation, the length of the mantissa m determines the length of the effective digit, so if a highly accurate numerical value is required, a representation with a larger mantissa length is used.

Such floating-point operations have a wider range and higher precision than integer operations, and in recent years, there has been a trend in which high-speed operations are required to meet various advanced calculation requirements.

(Prior art) Currently, the most widely used binary floating point standard is
TEEE, DEC, IBM, MIL-3t d 17
It is 4 of 50A. Both are single-precision floating point numbers of 32
It is expressed in terms of word length in bits. All standards support double-precision data, and some also support other data formats, such as extended single-precision and extended double-precision. Among these, the IEEE working group is responsible for the ANSI/IEEE Std 754-1985
(Standards) (Standardized as the final standard in 1985.

) is proposed as a powerful standard for highly portable floating-point software. This proposed standard has received wide support and is likely to become the basis for much of the hardware subsequently created.

An example of a conventional arithmetic circuit according to this type of IEEE floating point format is shown in FIG. This example is an example of adding normalized numbers to each other or normalized numbers or non-normalized numbers for two manual numbers (input data) with base 2. In particular, Figure 5 shows the addition process. The addition of the mantissa part by the adder is completed,
A block diagram after the mantissa is stored in the pipeline register I is shown. Note that 2 is a register for the exponent part. In addition, the calculation of the code focus in the figure is omitted. Fifth
The operations of bost normalization (normalization) and rounding (rounding) will be described based on the figure.

Note that normalization means to prevent the most significant digit of the mantissa from becoming "0", and rounding means to prevent the most significant digit of the mantissa from becoming "0", and rounding means to round off the overflowing lower part when the calculation result exceeds a predetermined number of digits and cannot be stored. Processing, ie, rounding, by methods such as truncation. Depending on the rounding method, there is a possibility that the cumulative error will be significantly affected, so there are methods such as rounding toward a neighboring value or toward O. The format of the data stored in the pipeline register 1 is shown in FIG. 6, and the meanings of the main symbols are as follows.

V: overflow bit of mantissa part G: guard bit R: round bit, 7 to S: stay-open bit, to Now, in boss normalization, it is necessary to shift the mantissa part so that V=φ and N-1. First, the priority encoder (PE) 3 counts the number of consecutive "φ" from the ■ bit, and the value is sent to the shifter (sh
ifter) 4 and sends it to the exponent part adder (
adder) 5 as well. Then, the shifter 4 shifts only the necessary bits, thereby completing the boss normalization.

Next, do a round. The round is executed by the round circuit 6 by rounding down or rounding up the R bits as necessary. At this time, if the data in the mantissa is, for example, [1.11 to 110] and R = 1, an overflow will occur, so it is necessary to shift it to the right again by l bits and add "1" in adder 5. There is. After the round ends, the mantissa data is stored in the register 7 on the output side, and similarly the exponent data is stored in the register 8.

[Problem to be solved by the invention]

However, in such conventional arithmetic circuits,
Since the round is performed after normalization, the overall calculation processing time is long, making it difficult to meet the recent demands for higher speeds.

Therefore, an object of the present invention is to provide an arithmetic circuit that can speed up arithmetic processing.

[Means to solve the problem]

In order to achieve the above object, the arithmetic circuit according to the present invention operates on two numbers using floating point notation represented by an exponent part and a mantissa part, and has a predetermined number of additional bits in the lower digits of the mantissa part. In an arithmetic circuit that performs normalization and rounding processing according to a calculation result of a mantissa part, when a shift amount of normalization based on a calculation result of a mantissa part exceeds the number of additional bits, the mantissa part is shifted and, a first execution means for processing the least significant bit of the mantissa part in parallel and composing the two; and a shift means for shifting the mantissa, and when the shift amount of normalization based on the operation result of the mantissa is equal to or less than the additional bits, the digit shift of the mantissa caused by the rounding process is calculated by the rounding process result. and a second execution means that selects one of them in advance, and a second execution means that selects one of them;
and a selection means for selectively selecting the output of the execution means or the output of the second execution means.

[For production]

In the present invention, the normalization shift 1 based on the calculation result of the mantissa
When ffi exceeds the number of additional bits, shifting of the mantissa for normalization and rounding of the least significant bit are performed in parallel. On the other hand, when the normalization shift amount is less than or equal to the additional bits, the digit shift of the mantissa caused by the rounding process is set in advance for each aspect, and one of them is selected. In this case as well, rounding and mantissa shifting are performed in parallel.

Therefore, unlike sequential processing, normalization and rounding are processed in parallel, so calculation speed is significantly improved.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing one embodiment of an arithmetic circuit according to the present invention. FIG. 1 is a diagram showing a calculation block that performs subsequent round processing after the addition of the mantissa part is completed. first,
Explain the configuration. In Fig. 1, numeral 11 is a register, for example, a pipeline register, which stores 28 bits of data in the arrangement shown in the figure, of which 3 bits GSR and S (additional bits) are placed on the lower side of the LSB. ), which is the same as before. 12 is a sign register, and the sign register 12 represents positive and negative data. Stores 1-bit code data (SGN). For example, "0" represents positive, and "1" represents negative.

The output of register 11 is taken out in 28 bits and is passed through shifter 13,14, priority encoder PE15, 4-bit priority encoder (4bPE) 16 and L
The signal is input to the SB circuit 17. The priority encoder PE15 counts the number of consecutive "0"s from the V bits and sends the value to the shifter 13 as well as to an exponent adder (not shown) (represented by EXP). The shifter 13 performs a shift operation based on the output from the priority encoder PE15 for S<27 bits of the 28-bit mantissa, and sends the shifted 23-bit data to the selector 18. The LSB circuit 17 determines the LSB based on the mode requests RP and RM from the 5 data of the V, NI, NZ, N3, and S bits out of the 28-bit data in the register 11. It is shown in Figure 2.

That is, as shown in FIG. 2, the LSB circuit 17 has V, N
NOR gate 21 to which each bit of I, N2, and N3 is input
, an OR gate 22a to which the mode RM, S bit and SGN are input, and an inverter 2 for inverting the S bit.
2b, an OR gate 22C to which the inverted signals of mode RP, S bit, and SGN are input, and a Nante gate 23 for calculating the NAND of the OR gate 22a and the OR gate 22c.
LS
The decision of B is specifically shown in the attached table, and L after the decision is made.
1-bit data indicating S and B is input to the selector 18.

The shifter 13, priority encoder 15 and LSB circuit 17 collectively constitute a first execution means 19.

4-bit priority encoder 16 is in register rl
ノ28Hisototetano? )V, Nr, Nz, Ns
The system counts the number of consecutive "0"s starting from the (2) bit for the four bits, and sends that value to the shifter 14.A specific circuit is shown in FIG. That is, as shown in FIG. 3, the 4-pin priority encoder 16 has a gate 2 having at least one low active terminal.
4 to 26, and depending on the value of "0" consecutive from the ■ bit, the following four states are determined and a shift request is made: R1: 1-bit shift to the right, R2: No shift, L2: 1-bit shift to the left, L2: 2-bit shift to the left. is sent to the shifter 14, and this shift request is sent to the exponent adder. The shifter 14 shifts the 28-bit data from the register 11 by a predetermined amount in accordance with a shift request from the 4-bit priority encoder 16, and converts the shifted data into the LSB.
It is sent to an adder circuit 31, a round circuit 32 and a selector 33. The shifter 14 and the 4-bit priority encoder 16 constitute a shift means 27.

The LSB adder circuit 31 increments the shifted data sent by the shifter 14 by "1" in advance, and the incremented data is sent to the selector 33 in 24 bits, and its overflow signal OVF is Sent to exponent part adder. The round circuit 32 also receives 4-bit data from the register 11, namely LSB, G', R'S' (dashes represent shifted data) and the sign bit S from the sign register 12.
A specific circuit for performing round processing based on mode requests RN, RP, RM, and RZ from GN is shown in FIG. That is, in FIG. 4, the round circuit 32 includes gates 41 to 46 having at least one low active terminal, OR gates 47 to 50, an inverter 51, and AND gates 52 to 56. It is shown as in the attached table, and is rounded down to L.
Either adding +1 to SB is executed, and round circuit 3
The 2 bits output from 2 are a control signal for the selector 33, and are sent to the selector 33, which has no relation to the G and R bits.

The selector 18 receives the upper 24-bit data from the shifter 14 and the 24-bit data from the LSB adder 31, and the selector 33 selects the upper 24-bit data from the LSB adder 31 or the shifter 14 based on the 2-bit data from the round circuit 32. Data is selected and output to the selector 18. The selector 18 selectively selects the 24-bit data from the shifter 13 and the LSB circuit 17 and the 24-bit data from the selector 33 in accordance with the control request regarding the boss normalization round, and outputs the selected data and sends it to the register 57. . As shown in FIG. 1, the output register 57 is (1, mz:+, ゛・.

. . . mz, m+) 24-bit data that has undergone normalization and round processing is stored.

The LSB addition circuit 31, round circuit 32, and selector 33 collectively constitute the second execution means 58, and the selector 18 constitutes the selection means.

Next, the effect will be explained.

In data in which 3 bits are added to the lower digits of the LSB as in this embodiment, the data content of the lower bits including the LSB is influenced by the round processing of these 3 bits even after normalization. However, since there are 3 additional bits, at most 3 bits can only be shifted. For example, when performing a left shift operation on 3 bits during boss normalization, after performing the left shift operation,
No matter what round is selected, no carry occurs when the round is executed. Therefore, only a shift operation is required.

Therefore, in this embodiment, focusing on the above fact, shifts of more than 3 bits and shifts of less than 3 bits and subjected to round processing (including all round processing of this embodiment) are as follows: By performing calculations in advance using parallel processing and then simply selecting the corresponding processed data using the selector 18, the time required for calculation processing is shortened.

3 bits. The 111 shift amount of normalization is detected by the priority encoder 15, and shifted by the shifter 13. At the same time, the LSB value is determined by the LSB circuit 17 based on the round processing request, and both are combined and The data is sent to the selector 18 as bit data. Then, the 24-bit data is selected as is by the selector 18 and stored in the output register 57. Note that the storage register of the output register 57 does not include the V bit, and is always hidden as V=O. Therefore, in the case of normalization of more than 3 bits, normalization and round processing are executed in parallel, and then it is only necessary to compile them, which shortens the overall processing time compared to the conventional method, resulting in faster processing. be able to.

Since the normalization of 3 bits p is 1", the shift l is within 3 bits, so first, register 11
Of the 28 bits stored in , V, , N, , N2 ,
About N3 ■ The number of consecutive "0"s from the bit is counted by the 4-bit priority encoder 16, and according to that value, the shifter 14 selects the S bit from the register 11. Shifted by a fixed amount. Thereafter, values assuming all situations regarding the round process are created in advance. Specifically, the following four cases are possible.

([)V, NI N2 N3 = IXXX However,
X is l or O. In this case, ■=0, so a 1-bit right shift operation is required.

(If) VN+NZ N3 = 01 Since it is normalized when XX, there is no shift III) V N+ NZ N3 = 001 X1
Bit left shift required (TV) VN, N2 Nff -00012 bit left shift required These round processes are mode requests RN, RP, RM,
As shown in the attached table, RZ is performed in advance by the round circuit 32, and then based on the output of the round circuit 32, the selector 33 selects either adding +1 to S B or rounding down, and the 24-bit data is sent to the selector. 18. Then, output data from the selector 33 is selected by the selector 18 in accordance with the control request and stored in the output register 57.

In such a case, since the normalization is within 3 bits, the shift amount is limited to 4 bits or less at most, so the processing can be performed using a 4-pin logic circuit, and the shift time is short. Further, regarding round processing, all possible cases are set in advance, and only one of them is selected, and this round processing is performed by logic circuits arranged in parallel. Therefore, unlike the conventional method, the overall calculation processing time is shortened, and the processing speed can be increased.

Note that in this embodiment, G is added as an additional bit to the lower digit of the LSB.
Although this is an example in which 3 bits of R3 are added, the number of additional bits is not limited to 3 bits, and may be any other number. Furthermore, the round mode request is not limited to the embodiment described above, and may be other examples. Furthermore, although the explanation has been made using a single-precision floating point data format according to the IEEE standard, other examples such as double-precision may also be used. Furthermore, data formats such as IBM and DEC type 2 may also be used.

〔effect〕

According to the present invention, since the normalization and rounding processes are executed in parallel while taking additional bits into consideration, it is possible to reduce delay, shorten calculation time, and speed up processing. .

[Brief Description of the Drawings] Figures 1 to 4 are diagrams showing one embodiment of the arithmetic circuit according to the present invention. Figure 1 is an overall block diagram thereof, Figure 2 is a circuit diagram of its LSB circuit, Figure 3 is a circuit diagram of the 4-bit priority encoder, Figure 4 is a circuit diagram of its round circuit, Figure 5.6 is a diagram showing a conventional arithmetic circuit, and Figure 5 is its block diagram. The figure shows the data formation of the register. 11...Register, 12...Sign register, 13.14...Shifter, I5...Priority encoder, 16...
...4-bit priority encoder, 17...
... LSB circuit, 18 ... Selector, 19 ... First execution means, 27 ... Shift means, 57 ... Output register, 58 ...Second execution means. Patent applicant Fujitsu Ltd.: Attached table (1)
58 circuit operation, round processing) ×: “l'or”
φ” - Truncation: G, R, S bits are discarded. LSB: 'φ゛→'l', Ls[l is changed to “φ
Change "from 1" and truncate the G, R, and S bits. The S bit is not related to normalization software and maintains its position. Fig. 2 Ichitora ga Sn 4 rows of 4-pit Bryo 1 Noti Encoater Aguro Boku 4 Fig. 3 - Round box of protruding A row ■Each circuit diagram Fig. 4 Fig. 5 Decimal point

Claims (1)

[Claims] In addition to performing operations on two numbers using floating point notation represented by an exponent part and a mantissa part, a predetermined number of additional bits are added to the lower digits of the mantissa part, and the result of the operation of the mantissa part is In the arithmetic circuit that performs normalization and rounding processing accordingly, when the shift amount of normalization based on the operation result of the mantissa part exceeds the number of additional bits, the mantissa part is shifted and the least significant bit of the mantissa part is a first execution means for processing the rounding for , in parallel, and composing the two; and a shifting means for shifting the mantissa for normalization within the range of the number of appendage bits based on the operation result of the mantissa. , When the shift amount of normalization based on the operation result of the mantissa part is less than or equal to the additional bit, the digit shift of the mantissa part caused by the rounding process is set in advance as the result of the rounding process for each aspect, and one of them is set as the result of the rounding process. a second execution means that selects the first execution means or the second execution means, depending on whether the shift amount of normalization based on the operation result of the mantissa exceeds the additional bits;
An arithmetic circuit comprising: a selection means for selectively selecting the output of the execution means;