JPH02211669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the spread of depletion layers in source-drain diffusion layers, and to manufacture a MOSFET having large junction capacitance by forming diffusion layers having concentration higher than a semiconductor region just under the source-drain diffusion layers. CONSTITUTION:A photo-resist is shaped selectively onto the surface of a silicon substrate 1 except a substrate surface to which a MOSFET having the large junction capacitance of source-drain diffusion layers is formed, and a photo-resist pattern 7 is shaped. Boron ions are implanted selectively to the surface of the silicon substrate 1 while using the photo-resist pattern 7 and a field oxide film 4 and a gate electrode 6 as masks. The photo-resist pattern 7 is removed, and, P<+> diffusion layers 8 are formed to the MOSFET having the large junction capacitance of the source-drain diffusion layers through heat treatment. The boron concentration of the P<+> diffusion layers 8 is made thicker than a P well 3 by approximately one figure, and the depletion layers of N<+> source-drain diffusion layers 9 at a time when a MOSFETA is operated is difficult to be made wider than a MOSFETB, thus increasing junction capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming source/drain diffusion layers of MO and S type transistors having large junction capacitance.

[Conventional technology]

Figure 3 shows how to form the source/drain diffusion layer of MOSFET with large junction capacitance.
This will be explained using T as an example.

First, as shown in FIG. 3(a), an oxide film 2 is selectively formed on an N-type silicon substrate 1 to serve as a mask for ion implantation, and then boron ions are selectively implanted on the silicon substrate 1. P-well 3 is formed by implanting and driving in at high temperature.

Next, as shown in FIG. 3(b), a field oxide film 4 is formed by the LOCO3 method, and then a gate oxide film 5 and a gate electrode 6 are formed. Furthermore, field oxide film 4
Then, arsenic ions are implanted into the entire surface of the silicon substrate 1 using the gate electrode 6 as a mask.

Then, as shown in FIG. 3(C), the silicon substrate 1 is heat-treated in a nitrogen atmosphere.
The arsenic implanted into the source/drain region of the P well 3 is activated to form an N'' source/drain diffusion layer 9.
．． Gate oxide film 5. Gate electrode 6. An N-channel MOSFET consisting of N source/drain diffusion layers 9 is formed.

[Problem to be solved by the invention]

In the conventional semiconductor device manufactured as described above, MO
The junction capacitance of the source/drain diffusion layer 9 of the S FET is determined by the impurity concentration of the well 3, the depth Xj of the source/drain diffusion layer 9, and its planar area. Therefore, in order to increase the junction capacitance of the source/drain diffusion layer 9, it is necessary to increase the impurity concentration of the well 3 or increase the depth of the source/drain diffusion layer. It is necessary to increase the area.

However, increasing the planar area of the source/drain diffusion layer is not preferable because it leads to an increase in the chip size of the semiconductor device, which goes against the trend toward higher integration of the semiconductor device and increases costs. Also, source
If the depth Xj of the drain diffusion layer is increased, bunch-through tends to occur between the source and drain, making it unsuitable for miniaturization. Furthermore, although it is easy to increase the impurity concentration of the well, when forming multiple MOSFETs with different source/drain diffusion layer junction capacitances on the same chip, It is necessary to form wells each having a different concentration, which greatly increases the number of manufacturing steps. Furthermore, it is difficult to change the junction capacitance of the source diffusion layer and drain diffusion layer in the same MOSFET.

The present invention solves the above-mentioned problems and has a large junction capacitance.
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can selectively increase the junction capacitance of any diffusion layer.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a diffusion layer of one conductivity type in a region where a source or drain diffusion layer of a semiconductor region of one conductivity type is to be formed, with an impurity concentration higher than that of the semiconductor region, respectively. and a step of forming source/drain diffusion layers of opposite conductivity type shallower within each of the high concentration one conductivity type diffusion layers.

Another method of manufacturing a semiconductor device of the present invention includes a step of forming a one-conductivity type diffusion layer with a higher impurity concentration than the semiconductor region in one of the regions in which the source or drain diffusion layer of the one-conductivity type semiconductor region is to be formed. , forming either a source diffusion layer or a drain diffusion layer of an opposite conductivity type shallower within this highly doped diffusion layer of one conductivity type.

[Effect]

In the above-described manufacturing method, a diffusion layer having a higher concentration than the semiconductor region is present directly under each or one of the source and drain diffusion layers, thereby increasing the junction capacitance of the source and drain diffusion layers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(First Embodiment) FIGS. 1(a) to (f) show the present invention in an N-channel MOS
FIG. 3 is a vertical cross-sectional view showing an example applied to an FET in the order of manufacturing steps.

First, as shown in Figure 1(a), the specific resistance is 4 to 5 ΩcmO.
An oxide film 2 having a thickness of approximately 0.6 μm is formed on an N-type silicon substrate 1, and is selectively photo-etched to form a mask pattern for ion implantation. Thereafter, using this oxide film 2 as a mask, boron ions accelerated to 100 KeV are implanted, for example, 2XIO''cyn-2.

Next, as shown in FIG. 1(b), the silicon substrate 1 is
A heat treatment is performed in a nitrogen atmosphere at 100 to 1200°C for 8 to 10 hours to form a P-well 3 with a depth of about 10 μm.

At this time, the boron concentration in P-well 3 is approximately 2 to 4 x 1016
cm-3. After removing the oxide film 2 by etching with a hydrofluoric acid solution, a field oxide film 4 with a thickness of about 0.8 μm is selectively formed using the LOCOS method, leaving the part where the N-channel MO3FET will be formed. .

Next, as shown in FIG. 1(c), the surface of the silicon substrate 1 is oxidized, and a gate oxide film 5 with a thickness of 150 to 250 nm is formed on the portion of the silicon substrate surface that is not covered with the field oxide film 4. do. Next, a layer with a thickness of 0 is applied to the surface of the silicon substrate 1.
．． A gate electrode 6 is formed by growing a 6 μm thick phosphorus-doped polysilicon film and selectively photoetching it.

Next, as shown in FIG. 1(d), a photoresist is selectively formed on the surface of the silicon substrate 1 excluding the substrate surface where a MOSFET with a large junction capacitance of the source/drain diffusion layer is formed. Pattern 7 Strike pattern 7, field oxide film 4 and gate electrode 6
For example, boron ions accelerated to 20 KeV using a mask of 1×101' to 1×! Q'zcm-z is selectively implanted into the surface of the silicon substrate 1.

Next, as shown in FIG. 1(e), the photoresist pattern 7 is removed and a heat treatment is performed to form a P' diffusion layer 8 in the MOSFET having a large junction capacitance of the source/drain diffusion layer. The boron concentration of this P1 diffusion layer 8 is higher than that of the P well 3, and is about 5×1016 to 5×10I
It becomes 7cm-3. After this, using the field oxide film 4 and the gate electrode 6 as masks, arsenic ions accelerated to 3QKeV are applied to the silicon substrate surface at 5×10+5 to 1×101.
Inject 6 cm-2.

Thereafter, heat treatment is performed in a nitrogen atmosphere at 900° C. for about 10 minutes to form an N source/drain diffusion layer 9 as shown in FIG. 1(f). At this time, in a MOSFET with a large junction capacitance, the N'' source/drain diffusion layer 9 is formed on the P'' diffusion layer 8.

As a result, a MOSFE. TA and P well 3. Gate electrode 5
, gate electrode 6. and an M.N. source/drain diffusion layer 9. OSFETB is formed. And especially M
In OSFETA, the P4 diffusion layer 8 has a thickness of approximately 400 mm, and the boron concentration is approximately one order of magnitude higher than that of the P well 3.
When SFETA operates, the depletion layer of the N+ source/drain diffusion layer 9 becomes more difficult to expand than in MOSFETB.
Junction capacitance can be increased.

(Second Embodiment) Figures 2(a) to 2(c) show M
OSFET, here a P-channel MOSF. FIG. 3 is a vertical cross-sectional view showing a method for forming an ET in the order of manufacturing steps.

First, as shown in FIG. 2(a), a field with a thickness of about 0.8 μm is selectively formed by the LOCOS method on a silicon substrate 1 with a resistivity of 4 to 5 Ω・can, leaving a portion where a P-channel MOSFET will be formed. An oxide film 4 is formed. Then,
The surface of the silicon substrate 1 is oxidized to a thickness of 150 to 300μ.
After forming a gate oxide film 5 of m thickness, a phosphorus-doped polysilicon film with a thickness of about 0.6 μm is grown on the surface of the silicon substrate 1, and a gate electrode 6 is further formed by photoetching. At this time, the areas of the source and drain regions are the same.

Then, a photoresist is selectively formed on the surface of the silicon substrate 1 excluding the surface of the portion that will become the source of the MOSFET to provide a photoresist pattern 7. Then, using this photoresist pattern 7, field oxide film 4, and gate electrode 6 as a mask, a
Arsenic ions accelerated to KeV are 5×1010 to 1×10
It is selectively injected onto the surface of a 13 cm -2 silicon substrate 1.

Next, as shown in FIG. 2(b), after removing the photoresist pattern 7, heat treatment is performed to form an N diffusion layer 8A only on the source side of the MOSFET. At this time, the arsenic concentration in the N diffusion layer 8A is about one to two orders of magnitude higher than that of the silicon substrate. After this, a field oxide film 4 is further formed on the silicon substrate surface.
Using the gate electrode 6 as a mask, boron ions accelerated to 10 KeV are implanted at 5 x 10+5 to 1 x 1016 cm-2.

Thereafter, a heat treatment is performed in a nitrogen atmosphere at 950° C. for about 5 minutes to form a P source/drain diffusion layer 9A as shown in FIG. 2(C). As a result, the N' diffusion layer exists directly under the P' source diffusion layer 9A, and the junction capacitance is increased compared to the P' drain diffusion layer 9A.

In addition, in this example, the thickness of the N+ diffusion layer 8A is 50 to 2
It is set to 00 people.

〔Effect of the invention〕

As explained above, the present invention forms a one-conductivity type diffusion layer with a higher impurity concentration than the semiconductor region in at least one of the regions where the source/drain diffusion layer is formed, and in this high concentration one-conductivity type diffusion layer. Since each or one of the opposite conductivity type source/drain diffusion layers is formed shallower than this, a diffusion layer with a higher concentration than the semiconductor region is present directly under the source/drain diffusion layer. Therefore, it is possible to easily manufacture a MOSFET with a large junction capacitance by reducing the spread of the depletion layer in the source/drain diffusion layer.

Thereby, there is no need to increase the planar area of the source/drain diffusion layer, and high integration of the semiconductor device can be achieved.

In addition, it becomes possible to simultaneously form MO'5FETs with different junction capacitances, for example, static RAM (
S RAM: 5tatic Rank
If applied to the simultaneous formation of a MOSFET with a large junction capacitance in the storage area and a MOSFET with a small junction capacitance in the peripheral area in OM Access Memory, the soft error rate due to alpha rays will be low and the input/output access speed will be high. Devices can be manufactured at low cost.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are vertical sectional views showing a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to (C) show a second embodiment of the present invention in the order of manufacturing steps. Longitudinal sectional view, Figure 3 (a
) to (C) are vertical cross-sectional views showing the conventional manufacturing method in the order of steps. 1... N-type silicon substrate, 2... Oxide film, 3...
P well, 4...Field oxide film, 5...Gate oxide film, 6...Gate electrode, 7...Photoresist, 8...P' diffusion layer, 8A...N' diffusion layer , 9...
・N゛source drain diffusion layer, 9A...P+ source・
Drain diffusion layer. I'm sorry C.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a MOSFET in which a source/drain diffusion layer of opposite conductivity type is formed in a semiconductor region of one conductivity type, in which the source/drain diffusion layer is formed in a region of the semiconductor region of one conductivity type, respectively. A step of forming a one-conductivity type diffusion layer with an impurity concentration higher than that of the semiconductor region, and a step of forming an opposite conductivity type source/drain diffusion layer shallower than this in each of the one-conductivity type diffusion layer with an impurity concentration higher than that of the semiconductor region. A method for manufacturing a semiconductor device, characterized in that: 2. In a method for manufacturing a MOSFET in which a source/drain diffusion layer of an opposite conductivity type is formed in a semiconductor region of one conductivity type, one of the regions of the semiconductor region of one conductivity type in which a source or drain diffusion layer is formed has a height higher than that of the semiconductor region. A step of forming a diffusion layer of one conductivity type with an impurity concentration, and a step of forming one of a source diffusion layer or a drain diffusion layer of an opposite conductivity type shallower within this high concentration diffusion layer of one conductivity type. A method for manufacturing a featured semiconductor device.