JPS58140162A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58140162A JPS58140162A JP2418982A JP2418982A JPS58140162A JP S58140162 A JPS58140162 A JP S58140162A JP 2418982 A JP2418982 A JP 2418982A JP 2418982 A JP2418982 A JP 2418982A JP S58140162 A JPS58140162 A JP S58140162A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- ccd
- substrate
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8236—Combination of enhancement and depletion transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823406—Combination of charge coupled devices, i.e. CCD, or BBD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本兄明は半導体装置の製造方法に関し、特に、同一チッ
プ内にＸ／Ｄ Ｍ Ｏ８回路とＣＣＤとを有する半導体
装置製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having an X/D MO8 circuit and a CCD in the same chip.
従来はＣＣＤと同一チップ内にＭＯＳ １−ランジスタ
を共存させる場合、そのしきい値電圧を制御するために
不純物を導入する工程を追加していたため、ウェハプロ
セス工程全体が複雑になっていた。Conventionally, when a MOS 1-transistor is co-existed in the same chip as a CCD, a step of introducing impurities is added to control the threshold voltage, which complicates the entire wafer process.
本発明は、埋込チャンネルＣＯＤと同一チップ内ニエン
ハンスメントモードのＭＯＳトランジスタと、デプレッ
ションモードのＭＯＳトランジスタとを追加の工程を用
いることなく形成することができる半導体装置の製造方
法を提供することを目的とする。すなわち、ＣＯＤと同
一チップ内にＥ／Ｄ Ｍ ＯＳ回路を同時形成する半導
体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can form an enhancement mode MOS transistor and a depletion mode MOS transistor in the same chip as a buried channel COD without using any additional steps. shall be. That is, an object of the present invention is to provide a method for manufacturing a semiconductor device in which an E/D MOS circuit is simultaneously formed in the same chip as a COD.
本発明の製造法を実施例を用いて説明する。The manufacturing method of the present invention will be explained using Examples.
第１図〜第６図は本発明に係るプロセスを説明する断面
説明図である。第１図において、１はＰ形（１００）の
シリコン基板であり、不純物濃度１×１ｏ１５ｃｒｎ−
３４呈度のものである。同図はＬＯＣＯ５工程による厚
膜部２と薄膜部３−１ 、３−２．３−３との８ｉｏ２
が形成された状態である。同図には薄膜部が３箇所示さ
れており、左側の薄膜部３−１がＣＣＤ部となるところ
、中央の薄膜部３−２がエンハンスメント形ＭＯ８）ラ
ンジスタとなるところ、右側の薄膜部３−３がデプレッ
ション形ＭＯＳトランジスタとなるところである。1 to 6 are cross-sectional explanatory diagrams illustrating the process according to the present invention. In FIG. 1, 1 is a P-type (100) silicon substrate, with an impurity concentration of 1×1o15crn-
It has an intensity of 34 degrees. The figure shows 8io2 of thick film part 2 and thin film part 3-1, 3-2.3-3 by LOCO5 process.
is formed. The figure shows three thin film parts: the thin film part 3-1 on the left becomes the CCD part, the thin film part 3-2 in the center becomes the enhancement type MO8) transistor, and the thin film part 3 on the right -3 is a depletion type MOS transistor.
第２図はフォトレジストを用いた周知のフォトエッチ技
術により部分的にフォトレジストでマスクし、部分的に
リンを１．６×１０１２ｃｒｎ−２イオン注入し、かつ
ドライブイン拡散を行なった後の状態であり、４−１．
４−２は同時に形成されたｒ領域であり、それぞれ埋込
チャンネル部および、デプレッションチャンネル部を構
成するものである。Figure 2 shows the state after partially masking with photoresist using a well-known photoetch technique using photoresist, partially implanting 1.6 x 1012 crn-2 ions of phosphorus, and performing drive-in diffusion. 4-1.
Reference numeral 4-2 denotes an r region formed at the same time, which constitutes a buried channel section and a depression channel section, respectively.
そのあと、全面にポリシリコン膜を生成し、フォトエツ
チングによりＣＯＤゲート部５−１とデプレッショント
ランジスタのゲート部５−２とを形成する。Ｃ第３図）
次に、全面にボロンを乙６×１ｏ１１ｃｒｎ−２イオン
注入することにより薄膜ＳｉＯ□３−１．３−２゜３−
３を通して基板のシリコン中にボロンの注入された明域
が形成される。６−１．６−２．６−３がこのボロンの
注入された領域であり、ポリシリコンのゲート部５−１
．５−２厚膜５ｉ０２２で（まボロンイオンはシリコン
基板１には届かない。領域６−１はＣＯＤのバリヤ部を
形成しており、また領域ｅ−２はエンノ１ンスメントＭ
ＯＳトランジスタのエンハンスメントチャネル部を構成
するものである。（第４図）
次にポリシリコンのゲート部５−１．５−２を酸化して
表面に５ｉ０２膜を形成し、さらに、その上から第２の
ポリシリコン膜を生成し、フオトエ・ノチングでＣＯＤ
のバリヤゲート部７−１とエンハンスメントトランジス
タのゲート部７−２とを構成した状態を第５図に示す。Thereafter, a polysilicon film is formed on the entire surface, and a COD gate section 5-1 and a gate section 5-2 of a depletion transistor are formed by photoetching. (Fig. 3) Next, a thin film of SiO□3-1.3-2゜3- is formed by implanting boron ions into the entire surface.
A boron-implanted bright area is formed in the silicon of the substrate through 3. 6-1.6-2.6-3 is the region where this boron is implanted, and the polysilicon gate part 5-1
．． 5-2 Thick film 5i022 (boron ions do not reach the silicon substrate 1. Region 6-1 forms the barrier part of COD, and region e-2 forms the enhancement M).
This constitutes an enhancement channel section of the OS transistor. (Fig. 4) Next, the polysilicon gate part 5-1, 5-2 is oxidized to form a 5i02 film on the surface, and then a second polysilicon film is formed on top of it, and photo-notching is performed. COD
FIG. 5 shows the configuration of the barrier gate section 7-1 of the transistor and the gate section 7-2 of the enhancement transistor.
第６図の状態で全面に６Ｘ１ｏ１５ｃｒｎ−２のリンを
イオン注入し、ドライブインした状態を第６図に示す。In the state shown in FIG. 6, 6×1o15 crn-2 phosphorus ions are implanted into the entire surface and the drive-in state is shown in FIG.
第６図において薄膜部のみリンが基板１のシリコン中に
注入されて、工ンノ１ンスメントトランジスタのソース
・ ドレイン部８−１．デプレ、７シヨントランジスタ
のソース・ドレイン部ａ −２が形成されている。In FIG. 6, phosphorus is injected into the silicon of the substrate 1 only in the thin film portion to form the source/drain portions 8-1 of the engineering transistor. The source/drain portions a-2 of the depression transistor are formed.
以下第６図を用いて各部分の構成を詳しく説明する。同
図の部分９が埋込チャネルＣＯＤ部であり蓄積ゲート部
６−１部とバリヤゲート部７−１部とよりなる一対のゲ
ートの繰返し構造の２相駆動形ＣＯＤ転送部である。部
分１ｏは第１層ポリシリコンより成るゲート部７−２を
有し、その直下の領域６−２にボロンが打込まれた構造
のエンハンスメントトランジスタとなっている。部分１
１は第１層ポリシリコンより成るゲート部６−２を有し
、その直下にリンの打込まれた領域４−２を有する構造
のデプレッショントランジスタとなっている。なお、ボ
ロンの打込まれた領域６−３志それより充分多い量のリ
ンの打込まれた領域８−２に含まれており、従って先行
のボロンはこの場合作用しない。The configuration of each part will be explained in detail below using FIG. 6. A portion 9 in the figure is a buried channel COD section, which is a two-phase drive type COD transfer section having a repeating structure of a pair of gates consisting of a storage gate section 6-1 and a barrier gate section 7-1. The portion 1o has a gate portion 7-2 made of a first layer of polysilicon, and is an enhancement transistor having a structure in which boron is implanted into a region 6-2 immediately below the gate portion 7-2. part 1
1 is a depletion transistor having a structure having a gate portion 6-2 made of a first layer of polysilicon and a region 4-2 implanted with phosphorus immediately below the gate portion 6-2. Note that the region 6-3 into which boron is implanted is included in the region 8-2 into which a sufficiently larger amount of phosphorus is implanted, so that the preceding boron does not act in this case.
本実施例ではエンハンスメントトランジスタのしきい値
電圧ＶＴＲは
ＶＴ１１＝１．０Ｖ
デプレッショントランジスタのしきい値電圧ＶＴＤは
Ｖｔｎ＝−５Ｖ程度となり、また
ＣＯＤ蓄積部のピンチオフ電圧ｖｐｓは
Ｖｐｇ＝７．５Ｖ
ＣＣＤバリヤ部のピンチオフ電圧ＶＩＩＢＧまＶＰＢ
＝ ４．５ Ｖ
程度となる。In this embodiment, the threshold voltage VTR of the enhancement transistor is VT11=1.0V, and the threshold voltage VTD of the depletion transistor is
Vtn=about -5V, and the pinch-off voltage vps of the COD storage section is Vpg=7.5V.The pinch-off voltage of the CCD barrier section is VIIBG or VPB.
= approximately 4.5 V.
以上の実施例では簡単のため、フィールド部のチャネル
ストッパーについては説明を省略した力く通常のＬｏｃ
ｏｓプロセスと同様にフィールド部の選択酸化前にボロ
ン管のイオン注入等を実施するとよい。また、ゲートポ
リシリコンへの不純物の導入についても、各層の生成直
後にドーピング゛する等ノ、通常のＭＯＳプロセスを適
用すれｃｆよ０゜以上実施例を用いて説明したごとく、
本発明によれば埋込チャネル（ＳＯＤを作るプロセスに
何ら工程を追加することなく、エンハンスメントトラン
ジスタとデプレ・ノショントランジスタを同時に作りこ
みに／Ｄ Ｍ ＯＳ回路を構成出来、ｃａｎ周辺回路部
等を同一チ・ツブ内に集積化するのに極めて好都合であ
る。In the above embodiment, for the sake of simplicity, the description of the channel stopper in the field section is omitted.
As in the OS process, it is preferable to perform ion implantation into a boron tube before selective oxidation of the field portion. Also, regarding the introduction of impurities into the gate polysilicon, a normal MOS process is applied, such as doping immediately after the formation of each layer.
According to the present invention, it is possible to configure a DMOS circuit by simultaneously building an enhancement transistor and a depreciation transistor without adding any process to the process of making a buried channel (SOD), and to configure a CAN peripheral circuit section, etc. This is extremely convenient for integration within the same chip.
第１図〜第６図は本発明の実施例に係る工程説明図であ
る。
１・・・・・・Ｐ型半導体基板、４−１・・・・・・Ｃ
ＯＤの埋込チャネル部、４−２・・・用デプレッシ９ン
チャンネル部、６−１・・・・・・ＣＯＤのバリヤ部、
６−２・・・・・・エンハンスチャンネル部、８−１．
８−２・・・・・・ＭＯＳ）ランジスタのソース・ ド
レイン部。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１１
図1 to 6 are process explanatory diagrams according to an embodiment of the present invention. 1...P-type semiconductor substrate, 4-1...C
Embedded channel section of OD, depression 9 channel section for 4-2..., barrier section of COD, 6-1...
6-2...Enhance channel section, 8-1.
8-2...MOS) Source/drain part of transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person11
figure
Claims (1)
することによりＣＣＤ部の埋込チャンネル層とデプレッ
ショントランジスタのデプレッションチャンネル層とを
形成する工程と、前記承板に＋ｊｉＪ記−万導電型の不
純物４人をすることにより＋ｊ’ｒＪ記ＣＯＤ ｄのバ
リヤ領域とエンハンスメントトランジスタのエンハンス
メントチャンネルｆｍ 域（！： 全形成する工程と、
前記基板に前記他方尋′磁型の不純物導入をすることに
より前記エンハンスメントトランジスタおよびデプレッ
ショントランジスタのソース、ドレイン領域を形成する
工程とを含むことを特徴とする半導体装置の製造方法。A step of forming a buried channel layer of a CCD section and a depression channel layer of a depletion transistor by applying an impurity layer of a dielectric type to a semiconductor substrate of a type semiconductor substrate; By adding conductivity type impurities, the barrier region of +j'rJ COD d and the enhancement channel fm region of the enhancement transistor (!: Complete formation process and
A method for manufacturing a semiconductor device, comprising the step of forming source and drain regions of the enhancement transistor and the depletion transistor by introducing impurities of the other type into the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2418982A JPS58140162A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2418982A JPS58140162A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58140162A true JPS58140162A (en) | 1983-08-19 |
Family
ID=12131373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2418982A Pending JPS58140162A (en) | 1982-02-16 | 1982-02-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140162A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0305742A1 (en) * | 1987-07-31 | 1989-03-08 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device having CCD and peripheral circuit |
-
1982
- 1982-02-16 JP JP2418982A patent/JPS58140162A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0305742A1 (en) * | 1987-07-31 | 1989-03-08 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device having CCD and peripheral circuit |
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