JPH0220924A - ロジックアレイ - Google Patents

ロジックアレイ

Info

Publication number
JPH0220924A
JPH0220924A JP31788588A JP31788588A JPH0220924A JP H0220924 A JPH0220924 A JP H0220924A JP 31788588 A JP31788588 A JP 31788588A JP 31788588 A JP31788588 A JP 31788588A JP H0220924 A JPH0220924 A JP H0220924A
Authority
JP
Japan
Prior art keywords
circuit
gate circuit
input
array
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31788588A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0379887B2 (enrdf_load_stackoverflow
Inventor
Junichi Iwasaki
岩先　純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31788588A priority Critical patent/JPH0220924A/ja
Publication of JPH0220924A publication Critical patent/JPH0220924A/ja
Publication of JPH0379887B2 publication Critical patent/JPH0379887B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP31788588A 1988-12-16 1988-12-16 ロジックアレイ Granted JPH0220924A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31788588A JPH0220924A (ja) 1988-12-16 1988-12-16 ロジックアレイ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31788588A JPH0220924A (ja) 1988-12-16 1988-12-16 ロジックアレイ

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57157466A Division JPS5947845A (ja) 1982-09-10 1982-09-10 Ｃｍｏｓロジツクアレイ

Publications (2)

Publication Number Publication Date
JPH0220924A true JPH0220924A (ja) 1990-01-24
JPH0379887B2 JPH0379887B2 (enrdf_load_stackoverflow) 1991-12-20

Family

ID=18093140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31788588A Granted JPH0220924A (ja) 1988-12-16 1988-12-16 ロジックアレイ

Country Status (1)

Country Link
JP (1) JPH0220924A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0379887B2 (enrdf_load_stackoverflow) 1991-12-20

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