JPH021971A - Formation of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a development period by a method wherein a program or a logic is decided, which controls a CPU as writing or erasing an information in an EPROM mounted on a first semiconductor integrated circuit device, the EPROM of the first semiconductor integrated circuit device is converted into a mask ROM, and a second semiconductor integrated circuit device, in which a program determined by the mask ROM is written in, is formed. CONSTITUTION:A floating gate electrode, which is peculiar to a field effect transistor as a memory cell of a memory cell array M-ARY EPROM, is removed to constitute a mask ROM which makes a field effect transistor of a single layer gate electrode structure serve as a memory cell. That is, in the EPROM, as the floating gate electrode is formed of a first layer gate electrode, a forming process of the first layer gate electrode is eliminated when the EPROM is substituted with the mask ROM. Each circuit block other than a read only memory(ROM) block is composed of a second layer gate electrode, so that the change in structure or electrical property due to the replacement of the EPROM with the mask ROM is prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device mounted in an electronic device, and is particularly applicable to a semiconductor integrated circuit device having a microcomputer equipped with a nonvolatile memory circuit. It is about effective techniques.

[Conventional technology]

Semiconductor integrated circuit devices (LSIs) that have microcomputers installed in electronic devices undergo sufficient initial evaluation (debugging) such as system checks and circuit checks in the early stages of development, so changes to internal data and internal logic are not possible. It is desirable that this can be done easily.

For this reason, EPROM (erasable &
There is a trend of incorporating programmable read-only memory (programmable read-only memory) into semiconductor integrated circuit devices. EPROM is a nonvolatile memory circuit in which information is electrically written and erased using ultraviolet light, and the information can be rewritten after the manufacturing process. Note that this type of technology is described in, for example, Japanese Patent Laid-Open No. 188234/1983.

When the initial evaluation is completed and the program to control the microcomputer is determined, the EPR is used as a storage element.
There is no need to use OM.

Since the EPROM has a memory cell formed by a field effect transistor having a two-layer gate electrode structure, the manufacturing process is complicated and requires a large number of manufacturing steps. Additionally, EPROMs require a window for UV erasure, which increases the manufacturing cost of the package. For this reason, a semiconductor integrated circuit device having a microcomputer equipped with an EPROM becomes expensive to manufacture. Furthermore, when the semiconductor integrated circuit device is mass-produced, it is necessary to write the determined program into each EPROM, which increases the time required to write information.

Therefore, after determining the program in a semiconductor integrated circuit device having a microcomputer equipped with the EPROM, a new semiconductor integrated circuit device having a microcomputer equipped with a mask ROM was developed, and the program was determined in the mounted mask ROM. The program is being written. The mask ROM is a nonvolatile memory circuit used only for reading information, and information is written to it during the manufacturing process. Mask ROM has a simple structure in which a field effect transistor with a single-layer gate electrode structure is used as a memory cell, and the manufacturing process is simple and the number of manufacturing steps is small. Since no erasing window is required, the manufacturing cost of the package can be reduced. In other words, a semiconductor integrated circuit device having a microcomputer equipped with a mask ROM is low in price and suitable for mass production, and as a result, the cost of electronic equipment can be reduced.

[Problem to be solved by the invention]

The inventor discovered the following problem during the development of a semiconductor integrated circuit device having the above-mentioned microcomputer.

Areas other than the mask ROM, that is, peripheral circuits such as the microcomputer, of a semiconductor integrated circuit device having a microcomputer equipped with the mask ROM are the same as those of a semiconductor integrated circuit device having a microcomputer equipped with an EPROM. However, the peripheral circuits of these microcomputers and the like are formed using newly created manufacturing masks used throughout the manufacturing process. For this reason, it is necessary to check the manufactured mask itself and perform the same evaluation as the initial evaluation described above again, which is essentially equivalent to developing a new semiconductor integrated circuit device. There has been a problem in that the development period for a semiconductor integrated circuit device including a computer is extremely long.

An object of the present invention is to provide a technique that can shorten the development period in a semiconductor integrated circuit device having a microcomputer (CPU) equipped with a nonvolatile memory circuit.

Another object of the present invention is to provide a technique that can reduce the cost of electronic equipment in which the semiconductor integrated circuit device is mounted.

Another object of the present invention is to provide a semiconductor integrated circuit device having a microcomputer equipped with a first non-volatile memory circuit, in which the first non-volatile memory circuit can be converted into a second non-volatile memory circuit with the minimum necessary amount. Our goal is to provide the technology that is possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

A first semiconductor integrated circuit device having a CPU equipped with an EPROM (or EEPROM) is formed, and a program or logic for controlling the CPU is determined while writing and erasing information in the EPROM mounted on the first semiconductor integrated circuit device. Then, the EPROM of the first semiconductor integrated circuit device is converted into a mask ROM, and a second semiconductor integrated circuit device is formed in which the determined program is written into the mask ROM.

[For production]

According to the above-mentioned means, since the EPROM is converted into a mask ROM without changing the peripheral circuits of the microcomputer, etc., the second
The development period of a semiconductor integrated circuit device can be shortened.

As a result, the first semiconductor integrated circuit device mounted on the electronic device can be easily and quickly replaced with the second semiconductor integrated circuit device, which is cheaper than the first semiconductor integrated circuit device, so that the cost of the electronic device can be reduced.

Hereinafter, the configuration of the present invention will be explained along with examples.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) Example of the present invention! A semiconductor integrated circuit device having a microcomputer is shown in FIG. 1 (block diagram).

As shown in FIG. 1, the semiconductor integrated circuit device LSI is -
This is the part surrounded by dotted lines and constitutes a 1-chip microcomputer.

CPU is a microcomputer (microprocessor)
It is. Ilo is an input/output port, and this input/output port I10 has a data transfer direction register inside. O8C is an oscillation circuit. Although not particularly limited, the oscillation circuit ○SC may include a crystal resonator Xtal connected externally.
is used to form a highly accurate reference frequency signal and to form a lock pulse required by the microcomputer CPU. RAM is a random access memory (volatile memory circuit), and is mainly used as a temporary storage circuit for programs being executed or data in the middle of an operation. R.O.
M is a read-only memory (non-volatile memory circuit) in which various information processing programs, dictionary data, etc. are stored. Each of the random access memory RAM and read-only memory ROM includes a control circuit necessary for reading and writing operations of the storage element. In addition, each of these circuit blocks is a microcomputer C.
They are interconnected by an input/output bus l10BUS centered around the PU. This input/output bus T/○BUS includes a data bus and an address bus.

The read-only memory ROM mounted on the semiconductor integrated circuit device LSI is configured as shown in FIG. 2 (block diagram of the ROM).

The memory cell array M-ARY has a plurality of memory elements (memory cells) arranged in rows and columns, and has word lines W1 to W m ,
Each of the data lines Dn is extended. The X decoder circuit X-DE,C is configured to select the word line W. The Y-decoder circuit Y-DEC is configured to select a data line. Although not particularly limited,
X decoder circuit X-DEC, Y decoder circuit Y-DEC
Each of these is controlled by a microcomputer CPU.

The sense amplifier SA converts the signal of the storage element (memory cell) output to the data line in the information read operation into H4.
It is configured to determine whether it is the gh level or the Loν level and output it to the input/output bus I/○BUS via the data out buffer DOB. This output is controlled by the microcomputer CPU.

This read-only memory ROM is composed of an EPROM shown in FIG. 3A (equivalent circuit diagram) or a mask ROM shown in FIG. 3B (equivalent circuit diagram).

EPROM is a nonvolatile memory circuit in which information is electrically written and erased using ultraviolet light, and is configured so that information can be written and erased after the manufacturing process of the semiconductor integrated circuit device LSI. Read-only memory RO
The X decoder circuit X-DEC, which is a direct peripheral circuit of M,
An EPROM is mounted on a semiconductor integrated circuit device LSI that performs initial evaluation (debugging) of a Y-decoder circuit Y-DEC and its indirect peripheral circuits such as a microcomputer CPU and a random access memory RAM. In this initial evaluation, a system check and a circuit check are performed on the circuit blocks, and in particular, the microprogram and data program for controlling the microcomputer CPU are determined. That is, the EPROM is configured so that initial evaluation such as determining the program can be performed while repeatedly writing and erasing information.

As shown in FIG. 3A, the memory cell array M-ARY of the EPROM includes word lines W1 to Wm and data lines D□ to D.
A memory element (memory cell) Q□□... is located at the intersection with n.
Qmn is placed. The storage element Q has a basic structure of a field effect transistor having a two-layer gate electrode structure, which has a floating gate electrode that stores charges serving as information and a control gate electrode.

The mask ROM is a nonvolatile memory circuit used only for reading information, and is configured so that information can be stored during the manufacturing process of the semiconductor integrated circuit device LSI. Mask ROM
The same program (information) for controlling the microcomputer CPU is written in the EPROM in the initial evaluation.

As shown in FIG. 3B, the memory cell array M-ARY of the mask ROM includes words #IW, ~Wm and data A! D
A Memory element (memory cell) Q1 is placed at the intersection with Dn.
□″...Qflln' is arranged.Storage element Q'
The basic structure is a field effect transistor having a single-layer gate electrode structure.

In addition, the respective circuits of the read-only memory ROM's X-decoder circuit X-DEC, Y-decoder circuit Y-DEC, sense amplifier SA, and data-out buffer DOB are used to read information from the EPROM and mask ROM. Since it is a direct peripheral circuit that can be commonly used for EP
Both ROM and mask ROM have substantially the same structure. For example, in a read operation of an EPROM, the selected word line W is set to a level between the externally supplied power supply voltage Vcc and the data line W to prevent erroneous writing during the read operation. Power supply voltage 1/4 cc to 1/3 lower than cc
set to vcc. Even when the EPROM is replaced with a mask ROM, the circuit configuration is such that the level of the word line W between the above-mentioned path and the level of the data line is maintained. In addition, EPROM and mask ROM that can operate with such a circuit configuration
with husband and wife.

In addition, as a direct peripheral circuit unique to EPROM, a second
As shown surrounded by broken lines in the figure, there is a data-in buffer DIB and a program circuit PGC. These peripheral circuits are used for writing information into the EFROM. Information to be written is data in buffer DIB
At the same time, write control signals such as the write voltage VPP and the program control circuit PGM are input to the program circuit PGC from the input/output bus l10BUS or directly from the outside via the control circuit C0NT. Information is written to the EPROM by inputting the information to the EPROM.

Direct peripheral circuits (information writing circuits) unique to this EPROM are configured to remain in a logically inactive state in the semiconductor integrated circuit device LSI when the EPROM is replaced with a mask ROM. . For example, the information writing circuit may leave the circuit pattern intact;
Configured into a logically inactive state by a control signal.

Further, the information writing circuit is configured in a logically inactive state without forming a circuit pattern (without forming any elements), although the circuit formation area remains.

Next, using Fig. 1, Fig. 2, Fig. 3A, and Fig. 3B,
A method for converting an EPROM mounted on a semiconductor integrated circuit device LSI into a mask ROM will be described. Here, E
In PROM, the memory cell is composed of a field effect transistor with a two-layer gate electrode and a 44W structure.The first layer gate electrode is a floating gate electrode, the second layer gate electrode is a control gate electrode, and the word line extending from these is a floating gate electrode. The case where this is configured will be explained. Further, a case will be described in which each circuit block other than the read-only memory ROM block shown in FIG. 1 is constituted by a field effect transistor having a single-layer gate electrode structure formed of a second-layer gate electrode.

(1) Memory Cell Array M-ARY The floating gate electrode peculiar to the field effect transistor which is the memory cell of the EPROM is deleted, and a mask ROM whose memory cell is a field effect transistor having a single-layer gate electrode structure is constructed. In other words, in EPROM, the floating gate electrode is formed by the first layer gate electrode, so if it is replaced with a mask ROM,
The step of forming the second layer gate electrode is eliminated. Each circuit block other than the read-only memory ROM block has 2
Since it is composed of layered gate electrodes, the mask ROM
There are no structural changes or changes in electrical characteristics due to the replacement. Furthermore, as shown in FIGS. 3A and 3B, the memory cells of the EPROM are arranged in parallel, so it can be easily replaced with a horizontal mask R'OM (mask ROM in which memory cells are arranged in parallel). I can do it.

(2) Decoder circuit DEC and read-out circuit Information written in the memory cell array M-ARY is read out by the X decoder circuit, Y decoder circuit, sense amplifier SA, data out buffer DOB, and control circuit C0NT.

The direct peripheral circuits used for these read operations are E
The circuit configuration is such that it can be used in common whether it is P ROM or mask ROM, so EPR
No changes are required when replacing OM with mask ROM.

However, since EPROM uses high voltage for write operation, the gate electrode of the field effect transistor in the direct peripheral circuit has a two-layer gate electrode structure consisting of a first layer gate electrode and a second layer gate electrode. In some cases, a single layer gate electrode structure including only the first layer gate electrode is used.

In either case, when replacing the mask ROM with a mask ROM, a direct peripheral circuit is constructed using a field effect transistor having a single-layer gate electrode structure with only a second-layer gate electrode. At this time, circuit constants may be changed, although there is no particular restriction. In the former case where the peripheral circuit is configured with a field effect transistor with a two-layer gate electrode structure, the first layer gate electrode and the second layer gate electrode are
If the gate electrodes intersect with each other in a plane through an interlayer insulating film, a shimmy portion will occur when replacing it with a mask ROM. Therefore, in an EPROM, the peripheral circuit is constructed using field effect transistors with a two-layer gate electrode structure. case,
A mask pattern is formed so that the two gate electrodes in the active state do not intersect in a plane.

(3) Write system circuit The write system circuit for information is mainly used in the case of EPROM, and mainly includes the program circuit PGC, data-in buffer DIB, program control circuit PGM, write voltage VPP, and control circuit. It is composed of C0NT. Among these, the write-related circuits that are not used in the mask ROM except for the control circuit C0NT are configured to be logically inactive as described above when replacing the EPROM with the mask ROM.

(4) Although not shown, the memory cell array M-ARY is EFRO.
In the case of M, since it has a circuit that allows direct access to the EPROM from the outside, the inter-track circuit is activated so that the mask ROM can be directly accessed even if it is replaced with a mask ROM. This facilitates data checking of the mask ROM.

Next, the semiconductor integrated circuit device L equipped with the EFROM is
Replace SI EPROM with mask ROM, mask R
Regarding the case of forming a semiconductor integrated circuit device LSI on which an OM is mounted, the basic concept of the forming method will be explained using FIG. 4 (manufacturing process flow diagram).

As shown in FIG. 4, first, an element isolation region is formed.
401>. This element isolation region forming step is a step for isolating each semiconductor element formed on a semiconductor substrate, and is a step of forming a thick field insulating film formed by, for example, a selective oxidation method.

This step is common to both EPROM and mask ROM.

Next, a gate insulating film and a gate electrode are formed (402
). This gate insulating film and gate electrode forming step is a step of forming a gate insulating film and a gate electrode of a field effect transistor, respectively. In the case of EPROM, this process is performed with two-layer gate ff1l! Since it is an i-structure, this is a process of forming two layers of gate electrodes, and in the case of a mask ROM, since it has a one-layer gate electrode structure, this is a process of forming one layer of gate electrodes. This step includes an impurity introduction step for adjusting the threshold voltage of the field effect transistor.

Next, a diffusion layer is formed (403). The diffusion layer forming step is a step of forming a source region and a drain region of a field effect transistor.
This is the process of introducing each type impurity. This diffusion layer formation process is an EPROM.

This process is common to each mask ROM.

Next, an interlayer insulating film is formed <404>. The interlayer insulating film forming step is a step of forming an insulating film that electrically isolates the field effect transistor and the wiring layer above it. The interlayer insulating film is a silicon oxide film deposited by CVD method, PS
It is formed of a single layer such as a G film or a BPSG film, or a composite film of a combination thereof.

This interlayer insulating film forming step is common to both EFROM and mask ROM.

Next, wiring is formed (405). The wiring forming process includes a process of forming connection holes for connecting each semiconductor element and a process of forming wiring made of aluminum or the like.

This wiring forming step is common to both EPROM and mask ROM.

Next, a passivation film is formed (406).

The passivation film forming step is a step of forming a final passivation film covering the entire surface of the semiconductor element.

The passivation film is formed of, for example, a PSG film, a silicon nitride film, or the like. This passivation film forming step is common to both EPROM and mask ROM.

Next, using FIG. 5A (a sectional view of the main part) and FIGS. 5B to 5F (a sectional view of the main part shown for each manufacturing process).

The structure and specific manufacturing method of a semiconductor integrated circuit device LSI equipped with an EPROM will be explained.

Furthermore, Fig. 6A (main part sectional view), Fig. 6B to 6F
Using figures (cross-sectional views of main parts shown for each manufacturing process).

The structure and specific manufacturing method of a semiconductor integrated circuit device LSI in which EPROM is replaced with mask ROM will be described.

As shown in FIG. 5A, the semiconductor integrated circuit device LSI is an EPROM having a field effect transistor Q as a memory cell.
It is equipped with The field effect transistor Q is formed on the main surface of a p° type semiconductor substrate 1 made of single crystal silicon, and includes a gate insulating film 4, a floating gate electrode 5. Gate insulating film 6, control gate electrode 8. It is composed of an n-type semiconductor region 10 which is a source region and a drain region. The field effect transistor Q has a two-layer gate electrode structure.

Field effect transistors (MI3FET) Q? formed on the main surface of the same semiconductor substrate 1? , Q, and □ constitute peripheral circuits. In this example, the lead
A circuit block serving as an indirect peripheral circuit other than the only memory ROM is composed of a field effect transistor Q T 2. The lower field effect transistor 2 has a one-layer gate electrode structure having a gate electrode 8 formed of the same conductive layer as the control gate electrode 8 of the field effect transistor Q.

Further, the direct peripheral circuit of the read-only memory ROM is composed of field effect transistors Q, , Q, and □, respectively. The field effect transistor Qtt has a one-layer gate electrode structure having a gate electrode 5 formed of the same conductive layer as the floating gate electrode 5 of the field effect transistor Q.

In FIG. 5A, field effect transistors Q, ,Q? ,
, Q? □ are electrically isolated from each other by field insulating film 2 and p-type channel stopper region 3. A wiring 13 is connected to the semiconductor region 0 of each of the field effect transistors Q, 'Q, . A passivation film 14 is provided on the wiring 13.

On the other hand, as shown in FIG. 6A, the semiconductor integrated circuit device LS
I is replaced by a mask ROM from an EPROM in the read-only memory ROM block, and a field effect transistor Q is a memory cell of the replaced mask ROM.

have. The field effect transistor Q is formed on the main surface of the semiconductor substrate 1, with a gate insulating film 7° and a gate electrode 8.
, 6 direct and indirect peripheral circuit field effect transistors (M5FETs) Q, □, Q?, each consisting of an n-type semiconductor region 10 which is a source region and a drain region. □
Each of the field effect transistors Q is a memory cell of this mask ROM.

It has a structure similar to that of , that is, a one-layer gate electrode structure formed of a second layer of gate electrode 8 .

Next, the semiconductor integrated circuit device LSI equipped with EPROM
A manufacturing method for the semiconductor integrated circuit device LSI equipped with a mask ROM and a corresponding manufacturing method for the semiconductor integrated circuit device LSI will be described with reference to FIG.

(1) Common element isolation region formation step As shown in FIG. 5B, a semiconductor integrated circuit device LSI equipped with an EPROM is field-insulated using a known selective oxidation method in a predetermined region on the main surface of a P-type semiconductor substrate 1. A film 2 is formed, and a p-type channel stopper region 3 is formed between this and the line in a manufacturing process. Although not particularly limited, the field insulating film 2
Before and after forming p-type or n-type on the main surface of semiconductor substrate 1.
A mold well region may also be formed.

When replacing the EPROM and forming a semiconductor integrated circuit device LSI equipped with a mask ROM, the field insulating film 2 and channel stopper region 3 are formed in substantially the same manner as shown in FIG. 6A.

(2) Gate insulating film and gate electrode formation process First, EPR
In the semiconductor integrated circuit device LSI equipped with O'M, a clean gate insulating film 4 is formed after removing the insulating film 4' in the element formation region. Thereafter, impurities for adjusting the threshold voltage are introduced into the main surface of the semiconductor substrate 1 in the element formation region.

Next, after depositing a polycrystalline silicon film over the entire surface of the substrate, a predetermined patterning is performed, and as shown in FIG. 5C, the floating gate electrode 5 of the field effect transistor Q and the floating gate electrode 5 of the field effect transistor Q7. A gate electrode 5 is formed.

A semiconductor integrated circuit device LSI equipped with a mask ROM is
Substantially, the step of forming the first layer gate electrode 5 is omitted.

Next, 'Semiconductor integrated circuit device LS equipped with EPROM
'I forms the gate insulating film 6 of the field effect transistor Q on the floating gate electrode 5. At this time, the gate insulating film 7 of the field effect transistor QT□ is formed by the same manufacturing process or the intermediate manufacturing process.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM replacing the EPROM.

After removing the insulating film 4' in the element formation region, a clean gate insulating film 7 is formed.

Next, the semiconductor integrated circuit device tLs equipped with EPROM
After introducing a predetermined impurity to adjust the threshold voltage, a polycrystalline silicon film is deposited on the entire surface of the substrate, and a predetermined patterning is performed to form the gate electrode 8 as shown in FIG. 5D. do. This gate electrode 8 is a control gate electrode 81 of the field effect transistor Q, which is a peripheral circuit of the field effect transistor Q? The gate electrodes 8 are formed as two gate electrodes 8, respectively.

When replacing the EFROM and forming a semiconductor integrated circuit device LSI equipped with a mask ROM, as shown in FIG. 6C, a gate electrode 8 is similarly formed on the gate insulating film 7 corresponding to the step shown in FIG. 5D. Form. This gate electrode 8
is a field effect transistor Q. , Q? 1 and Qo are formed as gate electrodes 8, respectively.

(3) Common diffusion layer formation process First, the semiconductor integrated circuit device LSI equipped with EPROM
mainly uses the thermal oxidation method to produce field effect transistors Q,
An insulating film 9 is formed to cover the floating gate electrode 5. This can prevent written electrons serving as information from escaping from the floating gate electrode 5 of the memory cell of the EPROM. Moreover, this insulating film 9 is
The dielectric strength of the end of the gate electrode 5 or 8 can be improved.

Next, as shown in FIG. 5E, n-type impurities are introduced into the entire surface of the substrate by ion implantation, and field effect transistors Q, , Q
.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM by replacing the EPROMttliq, as shown in FIG. 6D, the steps shown in FIG.
A °-type semiconductor region 10 is formed. This semiconductor region 10 is a field effect transistor Q,,Q? , , Q7□ are formed as the respective semiconductor regions 10.

(4) Common interlayer insulating film forming step In the semiconductor integrated circuit device LSI equipped with an EPROM, an interlayer insulating film 11 is formed.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM instead of an EPROM, an interlayer insulating film 11 is formed in the same manner as in the step described above.

(5) Common wiring formation step The semiconductor integrated circuit device LSI equipped with an EPROM is manufactured by forming one interlayer insulating film 1 after forming a connection hole 12 in an interlayer insulating film 11.
A wiring layer is formed on the entire surface of the wiring layer 1, and a predetermined patterning is performed thereon to form a wiring layer 13 as shown in FIG. 5F.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM replacing the EPROM.

As shown in FIG. 6E, the connection hole 12. Each of the wirings 13 is formed in sequence.

(6) Information writing process The semiconductor integrated circuit device LSI equipped with a mask ROM is
After forming the arrangement 113, as shown in FIG. 6F, a predetermined impurity such as B is introduced into the channel formation region of a predetermined field effect transistor Q through the interlayer insulator 111 and the gate electrode 8 to change the threshold voltage. let In other words, when word aW is selected, the field effect transistor Q, (memory cell) into which no impurities are introduced becomes ONL, and the field effect transistor Q, (memory cell) into which impurities are introduced.
is turned off even if word line W is selected.

Note that this information writing process is not limited to this, and the field effect transistor Q shown in FIG. 6D.

You can do this after the project is completed. Basically, it is preferable for the information writing process to be performed closer to the final stage of the manufacturing process, since this can shorten the time required to complete the product.

In addition, the information writing process includes a field effect transistor Q,
Whether or not the field insulating film 2 is formed in the element formation region of the field effect transistor Q.

The wiring (data line) 13 may be connected to the source region or drain region (semiconductor region 10) or not.

(7) Common passivation film forming step In the semiconductor integrated circuit device LSI equipped with the EPROM, a passivation film 14 is formed as shown in FIG. 5A.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM replacing the EPROM.

As shown in FIG. 6A, a passivation film 14 is similarly formed corresponding to the step.

By applying these pair of manufacturing processes, EPROM
A semiconductor integrated circuit device LSI mounted with a mask ROM can be formed by using this manufacturing process and a semiconductor integrated circuit device LSI mounted with a mask ROM can be formed by only partially modifying the manufacturing process.

In this way, a semiconductor integrated circuit device LSI having a microcomputer CPU equipped with an EPROM is formed,
EPROM installed in this semiconductor integrated circuit device LSI
perform an initial evaluation to determine the program that controls the microcomputer CPU while writing and erasing information to the microcomputer CPU), convert the EPROM of the semiconductor integrated circuit device LSI to a mask ROM, and write the determined program to the mask ROM. By forming an integrated semiconductor integrated circuit device LSI, EPROM was converted to mask ROM without changing peripheral circuits such as microcomputers.
The mask R corresponds to the test period of the peripheral circuit.
The development period of a semiconductor integrated circuit device LSI equipped with an OM can be shortened.

As a result, EFR was implemented in electronic equipment during initial evaluation.
To reduce the cost of electronic equipment by easily and quickly replacing a semiconductor integrated circuit device LSI equipped with an OM with a semiconductor integrated circuit device LSI equipped with a mask ROM, which is cheaper than the LSI after initial evaluation is completed. I can do it.

In addition, EFRO installed in semiconductor integrated circuit device LSI
M can be easily replaced with a horizontal mask ROM by simply omitting the step of forming the floating gate electrode 5 of the field effect transistor Q, which is a memory cell of the EPROM.

This replacement also applies to E P ROM, mask ROM
Since the peripheral circuits required for each have basically the same circuit configuration, changes at the time of replacement can be minimized and initial evaluations such as system checks and circuit checks can be simplified.

In addition, when replacing the unique peripheral circuits used only in EPROM with mask ROM, one circuit area is left as a logically inactive area, so mask ROM
It is possible to reduce the number of changes in mask patterns used when manufacturing a semiconductor integrated circuit device LSI equipped with a semiconductor integrated circuit device LSI. That is, replacing a semiconductor integrated circuit device LSI equipped with an EPROM with a semiconductor integrated circuit device LSI equipped with a mask ROM can be performed with minimal design changes for both the circuit and the mask used in the manufacturing process.

In addition, semiconductor integrated circuit device LSI equipped with EPROM
Semiconductor integrated circuit device LSI equipped with mask ROM from
Since the ultraviolet ray erasing window can be eliminated from the package, the packaging cost itself can be reduced. Furthermore, since the package can be replaced from a ceramic package to a resin package, the cost of the mm package can be further reduced.

(Embodiment 2) Embodiment 2 is a second embodiment of the present invention in which an EPROM composed of memory cells with a single-layer gate electrode structure is replaced with a mask ROM.

A memory cell of an EPROM mounted on a semiconductor integrated circuit device LSI, which is Embodiment 2 of the present invention, is shown in FIG. 7A (a sectional view of a main part).

As shown in FIG. 7A, a memory cell of an EPROM mounted on a semiconductor integrated circuit device LSI has a floating gate electrode 8 formed of a second layer gate electrode and a control gate electrode formed of an n-type semiconductor region. It is composed of a field effect transistor Q having 15. The source region and the drain region are arranged in the gate length direction of the floating gate electrode 8, respectively.

Next, a specific method for manufacturing the memory cell of this EPROM will be briefly explained using FIGS. 7B and 7C (cross-sectional views of main parts shown for each manufacturing process).

First, a field insulating film 2 is formed on the main surface of a p-type semiconductor substrate 1.
, p-type channel stopper region 3. A gate insulating film 7 is sequentially formed, and impurities for adjusting the threshold voltage are introduced.

Next, as shown in FIG. 7B, n-type impurities are introduced into the main surface of the semiconductor substrate 1 to form the control gate electrode 15.

Next, a polycrystalline silicon film is deposited on the entire surface of the substrate and subjected to predetermined patterning to form a floating gate electrode 8 as shown in FIG. 7C. Through the same manufacturing process as this process, the gate electrode 8 of the field effect transistor of the peripheral circuit is formed.

Next, in the same manner as in Example 2, the n-type semiconductor region 10,
Interlayer insulation film 11. By sequentially forming the connection hole 12 and the wiring 13, a semiconductor integrated circuit device LSI equipped with an EPROM is completed.

EFROM installed in this semiconductor integrated circuit device LSI
To replace it with a mask ROM, use one of the methods described below.

(1) Floating gate electrode 8 and control gate electrode 15 are electrically connected. This connection is made, for example, by the wiring 13.

(2) The step of forming the control gate electrode 15 is deleted, and the thick field insulating film 2 is formed in the deleted region. The floating gate electrode 8 is connected to a wiring 13 used as a word line W.

In this way, the 1 mounted on the semiconductor integrated circuit device LSI
Replacing an EPROM having a memory cell with a layered gate electrode structure with a mask ROM is easier than replacing an EPROM having a memory cell with a two-layered gate electrode structure.

(Example ■) In the present Example ■, a nonvolatile memory circuit, that is, an EEPROM (Electrical EPROM) in which information is written electrically and information is erased electrically, was used as the ROM before being replaced with a mask ROM.

This is a third embodiment of the present invention.

FIG. 8 (equivalent circuit diagram) shows a memory cell of an EEPROM mounted on a semiconductor integrated circuit device LSI which is Embodiment 2 of the present invention.

As shown in FIG. 8, a memory cell of an EEPROM mounted on a semiconductor integrated circuit device LSI has a floating gate electrode that stores charges, and an F that injects electrons into the floating gate electrode by a tunneling phenomenon.
Field effect transistor QM constructed of LOTOX type
11 to (Lmn) and control field effect transistors Q7□1 to Q?mn connected in series with the control field effect transistors Q7□ to Q?
TIIIn is connected to data lines Dn and word lines Wtt to W? They are connected to In and arranged in rows and columns. Further, the control gate electrodes of the field effect transistors Q, Y, to QMmn are connected to the word line W?
It is connected to word lines WM1 to W and m arranged in parallel to □ to W and m.

The information writing operation and information erasing operation of this EEPROM are well known and will not be specifically explained.

Next, the EEPR installed in the semiconductor integrated circuit device LSI
A method of replacing OM with mask ROM will be explained below. Note that the method for forming the peripheral circuit 1 is as described in Example ① above.
Since it is substantially the same as , it will be omitted here.

(1) When replacing the control field effect transistor Q7 of a memory cell with a mask ROM The control field effect transistor QT of a memory cell can be replaced as it is with a mask ROM memory cell without changing its basic structure. When replacing with a mask ROM, a FLOTOX field effect transistor Q is used as a memory cell.

and the word line WH connected thereto are deleted.

This part of the field effect transistor Q, 4 is formed as a diffusion layer and acts as a mere resistor, so the mask RO
It does not affect the configuration of M.

(2) FLOTOX field effect transistor Q of the memory cell. When the FLOTOX field effect transistor Q of the memory cell is replaced with a mask ROM, the FLOTOX field effect transistor Q of the memory cell can be replaced with a mask ROM in substantially the same manner as in Example I above. When replacing with a mask ROM, the control field effect transistor QT of the memory cell and the word line WT connected thereto are deleted. This field effect transistor lower portion is formed as a diffusion layer and acts simply as a resistor, so it does not affect the structure of the mask ROM.

In this way, the E
By replacing the EP ROM with a mask ROM, substantially the same effect as in the embodiment (2) can be achieved.

(Embodiment 2) Embodiment 2 is a fourth embodiment of the present invention in which a programmable logic array PLA using an EPROM as a logic function determining element is replaced with a mask ROM.

FIG. 9 (equivalent circuit diagram) shows the configuration of a programmable logic array PLA mounted on a semiconductor integrated circuit device LSI, which is Embodiment 2 of the present invention.

Since the method of writing information to the programmable logic array PLA mounted on the semiconductor integrated circuit device LSI shown in FIG. 9 is known, it will be briefly explained.

First, when writing information to the logic cell Q on the AND plane (1) turn off the control transistor T□ between the AND plane and the OR plane, and set the potential V to the write voltage.

(2) After applying a write voltage to the input I0, turn on the load transistor TQ1 to write information into the logic cell Q8.

Next, when writing information to the logic cell Mli on the OR plane (1) control transistors T, ~Tm, t o, ~L
o1 is turned off, and potentials v2 and v3 are set to write voltages.

(2) Turn on the load transistor TH1 and the control transistor t1 to write information into the logic cell M1□. Regular programmable logic array PLA
When used as a control transistor T□~Tm
, t□-tm are set to OFF state, to□ to tol are set to ON state, and (1) and V2 are set to predetermined potentials.

The method of replacing the EPROM used in this programmable logic array PLA with a mask ROM is as follows.
Since it is substantially the same as the above-mentioned Example I, the description thereof will be omitted here.

In this way, programmable
A semiconductor integrated circuit device LSI equipped with a logic array PLA is a semiconductor integrated circuit device L equipped with a mask ROM.
By replacing it with SI, substantially the same effect as in Example I can be achieved.

Also, the above example! In each of Embodiment 2 to Embodiment 2, the present invention provides a mask R mounted on a semiconductor integrated circuit device LSI.
OM can be replaced with EPROM or EEPROM.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in one aspect of the present invention, the EPROM is a vertical EPROM,
This may be replaced with a vertical mask ROM.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a microcomputer equipped with a nonvolatile memory circuit, the development period for converting the nonvolatile memory circuit into another nonvolatile memory circuit can be shortened.

[Brief explanation of the drawing]

Figure 1 is an embodiment of the present invention! FIG. 1 is a block configuration diagram of a semiconductor integrated circuit device having a microcomputer. FIG. 2 shows the RO of the semiconductor integrated circuit device shown in FIG.
The block configuration diagram of M, FIG. 3A, shows the EPRO formed in the ROM block.
The equivalent circuit diagram of M, FIG. 3B, shows the mask R formed in the ROM block.
Equivalent circuit diagram of OM. FIG. 4 is a flow diagram of the manufacturing process of a nonvolatile memory circuit formed in the ROM block. FIG. 5A is a sectional view of essential parts of the semiconductor integrated circuit device. 5B to 5F are main part sectional views showing the semiconductor integrated circuit device at each manufacturing process; FIG. 6A is a main part sectional view of the semiconductor integrated circuit device; FIGS. 6B to 6F are FIG. 7A is a cross-sectional view of the main parts of the semiconductor integrated circuit device showing each manufacturing process, and FIG.
81A is a cross-sectional view of a main part showing the structure of a memory cell of M, FIGS. 7B and 7C are main part cross-sectional views showing the memory cell in each manufacturing process, and FIG. E E mounted on a semiconductor integrated circuit device having
Equivalent circuit diagram of F ROM. FIG. 9 is an equivalent circuit diagram of a PLA mounted on a semiconductor integrated circuit device having a microcomputer, which is Embodiment 2 of the present invention. In the figure, LSI...semiconductor integrated circuit device, ROM...
・Note-only memory, CPU...microcomputer, M-ARY...memory cell array, DE
C...Decoder circuit, SA...Sense amplifier, D. 13...Data out buffer, DIR...Data in buffer, PGC...Program circuit, C
0NT...Control circuit.

Claims (1)

[Claims] 1. A first device capable of electrically writing information and erasing the information.
forming a first semiconductor integrated circuit device having a microcomputer equipped with a nonvolatile memory circuit;
determining a program or logic for controlling the microcomputer while writing and erasing information in a first nonvolatile memory circuit mounted on a semiconductor integrated circuit device;
a second semiconductor in which the first nonvolatile memory circuit of the first semiconductor integrated circuit device is converted into a second nonvolatile memory circuit for reading information only, and the determined program is written in the second nonvolatile memory element; 1. A method for forming a semiconductor integrated circuit device, comprising the step of forming an integrated circuit device. 2. The first nonvolatile memory circuit of the first semiconductor integrated circuit device is an ultraviolet erasable EPROM or an electrically erasable EE
2. The method of forming a semiconductor integrated circuit device according to claim 1, wherein the second nonvolatile memory circuit of the second semiconductor integrated circuit device is a PROM and the second nonvolatile memory circuit of the second semiconductor integrated circuit device is a mask ROM. 3. In the second nonvolatile memory circuit of the second semiconductor integrated circuit device, a part of the memory cell array of the first nonvolatile memory circuit of the first semiconductor integrated circuit device is modified, and the decoder circuit and the information readout circuit remain as they are. Formation of the semiconductor integrated circuit device according to claim 1 or 2, characterized in that the semiconductor integrated circuit device is formed by making the information writing circuit and the information erasing circuit logically inactive. Method. 4. The memory cell of the first non-volatile memory circuit of the first semiconductor integrated circuit device is composed of a field effect transistor having a floating gate electrode and a control gate electrode, and the memory cell of the first non-volatile memory circuit of the second semiconductor integrated circuit device Claim 3, wherein the memory cell is constituted by a field effect transistor having a gate electrode formed in a step corresponding to the control gate electrode of the memory cell of the first nonvolatile memory circuit. A method for forming a semiconductor integrated circuit device according to . 5. Claim 4, wherein information is written in the memory cell of the second nonvolatile memory circuit of the second semiconductor integrated circuit device by controlling the threshold voltage of a field effect transistor. A method for forming a semiconductor integrated circuit device according to section 1.