JP2000068378A - Manufacture of semiconductor device using programmable gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To necessitate almost no redesigning for mass-produced products by setting an operating threshold of a transistor constituting a non-volatile memory to such a one as to keep the transistor in an off-state even if it is written with on-data. SOLUTION: An FPGA(field programmable gate array) assembled with devices is tested for actual operations such as electrical characteristics, operating characteristics, etc., (51). Then, the device assembling program data for the FPGA stored in an external memory is read (52). Next, ions are implanted into a channel formation region of each transistor to conduct a preprocess (53). Then, a switching, transistor corresponding to the '1' data in a memory cell region is turned to an off state according to the FPGA program data to set a threshold value to such a high one that makes rewriting impossible (54). After an afterprocess of the FPGA (55), data is written to keep the FPGA in a '0' state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a programmable gate array, and more particularly, to a semiconductor device which is mass-produced with little deviation in operation characteristics and operation performance, does not require redesign and is stable. The present invention relates to a method for manufacturing a semiconductor device using a field programmable gate array (hereinafter referred to as an FPGA) that can be expected to perform the above operation.

[0002]

2. Description of the Related Art A flash-type EEPROM (flash memory) FPGA has a basic logic element forming area, an internal wiring of these basic logic elements, and a tile in an area having a size called a tile arranged in a matrix. It has matrix wirings arranged in a matrix to be interconnected with each other, and switch cells of a flash memory for connecting the respective wirings. A switch cell of a flash memory is composed of a switch transistor, a memory cell of an EEPROM, and an element for batch erasing. A switch transistor is arranged at the intersection of each wiring, and this switch is connected to a memory cell formed correspondingly. Write data,
Turning ON / OFF selectively establishes wiring.
There are two types of wiring formed at this time, one of which is a local connection wiring (connection inside the tile), and the other is a global connection wiring (devices of other similar tiles). Select wiring outside the tile area to connect
It is. The local connection wiring forms a NAND gate, a transmission gate, a switch circuit, an inverter, a buffer, and the like by selectively connecting basic logic elements in the tile or gates based thereon, and further connecting these devices. , Flip-flops, and other specific devices are formed on tiles. The global connection wiring is for selectively connecting devices of other tiles.

In such an FPGA, a specific device can be formed, that is, a so-called program can be performed by writing data into a memory cell of an EEPROM which forms a selective connection wiring.
Specific devices can be formed and incorporated into FPGAs. At this time, when each memory cell in the switch cell is a flash EEPROM, it becomes a programmable gate array of a flash memory. At this time, the program sets a specific memory cell in the tile to “1” or “0”, sets a connection switch to ON or OFF, and sets a connection memory in the tile or a memory involved in wiring between the tile and the tile. By storing "1" or "0" in the cell, a specific wiring connection is established, and a specific device is realized in each area.

FIG. 5 is an explanatory diagram of a tile which is a unit area in the FPGA 8 shown in FIG. 6. A tile 1 includes a connection wiring matrix 2 within the tile, a wiring matrix 3 outside the tile, and a switch connecting these matrix wirings. Memory cell region 4 including transistors and flash memory cells connected to each switch transistor
And a basic logic gate region 5 provided with basic logic elements forming a predetermined device. FPGA8
Has a structure in which a large number of tiles 1 are arranged in a matrix as shown in FIG. Reference numeral 14 denotes a pad connected to an external terminal. The tile device and pad 1
Wirings such as 4 and wiring to external terminals are omitted.

[0005] In the memory cell area 4, in order to form a connection wiring in the tile (local connection wiring) and a connection matrix wiring outside the tile (global connection wiring), the intersection of the matrix of the connection wiring matrix 2 in the tile is formed. And the switch transistors provided corresponding to the intersections of the matrices of the extra-tile wiring matrix 3, and the flash memories provided correspondingly to turn on / off these switch transistors And a cell. FIG. 7 shows an example of the connection relationship.

The relationship between a memory cell in the memory cell region 4 and a switch transistor for connecting a matrix wiring is shown in FIG.
When one flash memory cell MC is allocated to the T transistor Tr, the transistor Tr receives the output corresponding to the storage of "1" and "0" at the gate, and "0" is stored in the memory cell. Transistor is ON
By doing so, the lines of the vertical wiring and the horizontal wiring to which the switch transistor Tr is connected are connected. In the figure,
The logic elements are connected to the basic logic gate regions 5 connected by the wires in the connection wiring matrix 2 in the tile.
The logical elements of The memory cell area 4 of the tile 1
Each of the memory cells shown in FIG.
Each memory cell of the memory cell area 4 of each tile 1 arranged in a matrix shown in FIG. 1 is connected to a word line and a bit line, respectively, is wired in a matrix, and each cell is addressed. To simplify the drawing, wiring lines such as word lines and bit lines for accessing each memory cell are not shown.

[0007]

SUMMARY OF THE INVENTION Such an FPGA
Usually, many products are used as prototypes for products mass-produced as semiconductor devices such as gate arrays, MPUs, and various controllers, and their electrical performance, operation characteristics, and operation performance are examined. However, since a semiconductor device of a mass-produced product corresponding to an FPGA manufactured as a prototype is not usually a wiring form logically connected through a switch cell like an FPGA, a wiring form formed inside the semiconductor device is not generally used. Differences occur in device layout. For this reason, differences in signal delay, skew, operation speed, and the like occur between devices, and it is usually necessary to redesign devices as mass-produced devices. Such redesign takes time and at the same time makes the FP as a prototype.
Even confirming the electrical performance of the GA may be wasted. On the other hand, when the FPGA is used as it is as a mass-produced semiconductor device, data stored in the nonvolatile memory volatilizes due to aging, noise, and the like. There is a possibility of malfunction and the reliability must be reduced. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and it is possible to expect a stable operation with little redesign for mass-produced products.
An object of the present invention is to provide a method for manufacturing a semiconductor device by PGA.

[0008]

A feature of a method of manufacturing a semiconductor device using an FPGA according to the present invention that achieves the above object is that each of a transistor and a switch transistor constituting an electrically writable nonvolatile memory is provided. In a method of manufacturing a semiconductor device by a programmable gate array, which has a large number of switch cells in which floating gates are combined or integrated, and can be programmed by writing predetermined data to a nonvolatile memory,
An assembling step of writing predetermined program data into the non-volatile memory and incorporating a predetermined device, an operation confirming step of confirming operation of the device incorporated by the predetermined program data, and an operation characteristic is confirmed in the operation confirming step A switch transistor that is turned off in accordance with the program data of the embedded device that has been turned off is turned off even if ON data is written to a transistor that forms a nonvolatile memory corresponding to the switch transistor that is turned off by mask processing in the manufacturing process. And setting a processing threshold to an operation threshold for maintaining the state.

[0009]

As described above, according to the present invention, an FPGA having a large number of switch cells in which floating gates of transistors and switch transistors constituting an electrically writable nonvolatile memory are coupled or integrated. Then, in the program processing, data is written and a device is incorporated. The operation in a state where the data is written and the state of the switch transistor which is turned off are selectively written in the mask processing in the manufacturing process. Regardless of the above, a device is formed by setting an operation threshold value fixed to OFF. As a result, the switch transistor is selectively turned off in a state in which the device is operated in the program processing and the mask processing.
And a difference in operation characteristics between the case where the device is fixed and the device is built and operated is not required. At this time, the ON side of the switch transistor is set to ON by the conventional data writing by the program, but the OFF side is set to OFF regardless of the data writing by the program. It is less likely to volatilize due to changes or noise, so that the operation is more stable than the program processing, and the risk of malfunction is reduced.
As a result, by using an FPGA as a mass-produced product and fixing the state of the switch transistor to OFF in the operation state, it is possible to realize a semiconductor device that requires little redesign and can expect stable operation. .

[0010]

FIG. 1 is a flowchart of a device manufacturing process based on device embedding data into an FPGA to which a method of manufacturing a semiconductor device using an FPGA according to the present invention is applied. FIG. FIG. 3 and FIG. 3 are flowcharts of the process of incorporating the device into the FPGA, and FIG. 4 is an explanatory diagram of the structure of the switch cell. By the way, the cell itself of the flash memory becomes "0" when data is written in the operation state, the state where data is not written is "1", and the memory cell in the state programmed on the connection side is "1". Is “0”. The configuration as a switch cell in the FPGA is shown in FIG.
As shown in the external view of (a), an EEPROM forming area EEPROM and a switch transistor forming area SW
Tr and an erasing device forming region FN having a tunnel window for performing erasing at a time have an integrated structure having a common control gate layer 9 and a floating gate layer 10 with their respective gate layers being combined. . FIG. 2B shows a circuit diagram thereof.
Is a word line, and 12 is a bit line. FIG. 4 (c)
FIG. 2 is a sectional view taken along the line II of the switch transistor portion of FIG. 1A and shows a portion of a switch transistor formation region SWTr. As shown in this cross-sectional view, by adjusting the impurity concentration of the channel region 13 of the switch transistor SWTr by the amount of ion implantation, the operation threshold value of the switch transistor SWTr can be set, thereby fixing the transistor to the OFF state in the operation state. Can be set to In addition, 15 is an ONO film, and 16 is a P-type substrate (P-SUB). By the way, the ON / OFF operation threshold value of the transistor increases as the impurity concentration of the channel region increases, and when the operation threshold value increases, the switch transistor SWTr is set and maintained in an OFF state in an operation state. Conversely, if the impurity concentration of the channel region is set low, the switch transistor is set to the ON state when "0" is written in the operating state, or is maintained when set to the ON state. Of course, the latter can be set to OFF by the program processing of writing "1". In other words, if the operation threshold is increased to a predetermined value or more, in the operation state, electrons are injected into the floating gate of the switch transistor, and the transistor is set to OFF. Conversely, if the operation threshold value is lowered to a predetermined value or more, on the contrary, in the operation state, electrons are drawn from the floating gate, and the switch transistor is set to ON. Since an FPGA using a flash memory as a switch cell has the above-described integrated structure, the threshold value of the switch transistor SWTr is controlled by ion implantation in the manufacturing process, and the switch transistor is turned on or off in an operation state. Is almost equivalent to a state where data is written to the EEPROM memory as a program and turned ON or OFF, and the state of the wiring connected by the switch transistor SWTr and the characteristics of the device are not substantially changed. .
Therefore, there is very little characteristic deviation between the operation of the programmed device and the case where the switch transistor SWTr is operated by setting the operation threshold so as to be turned ON or OFF in the operation state by ion implantation in the manufacturing process.

Now, a method of incorporating a device using such an FPGA and the collection of data incorporating the device will be described with reference to FIG. The embedded device is analyzed in such a manner that the target circuit is adjusted to the formation device unit (the number of basic logic gates for forming one or two flip-flops) in the tile 1 (step 101), and the size of the tile 1 is reduced. As a combination of the devices analyzed together, each device is assigned to each tile so as to be optimally arranged (step 102). The device wiring in the optimum arrangement and the write data for the memory switch cells connecting the inside and outside of the tile for that are generated (step 10).
3). Next, the generated data is written into the FPGA 8 (step 103). As a result, in a certain tile, a specific wiring region in which the connection is formed by the flash memory switch cells forming the in-tile connection wiring, and at the same time, a matrix connection wiring forming the out-of-tile wiring are formed.

Next, the operation of the FPGA and its embedded device is checked by the operation trace and the input / output of data (step 104), and it is determined whether or not there is a problem in the operation (step 105). If there is a problem, a problematic device is extracted (step 106), the tile to which the device is assigned is detected as a defective tile (step 107), and the defective tile is stored (step 108). The devices analyzed in step 102 are reallocated corresponding to each tile except for defective tiles to obtain an optimal arrangement (step 109). Then, it is determined whether or not the optimal arrangement has been achieved (step 110). When the optimal arrangement is obtained, the process returns to step 103, and the same processing as described above is performed. If not, processing is performed as an FPGA failure (step 111). Step 1
If it is determined that there is no problem in the determination in step 05, it is determined that the device integration processing has been completed, and necessary processing such as recording the embedded program data in an external storage device is performed (step 112).

The F in which the device is incorporated as described above
A manufacturing method for mass-producing another FPGA using the program data for the PGA 8 will be described with reference to FIG. First, an actual test of the electrical performance, operating characteristics, and operating performance of the device incorporated in step 112 in the device incorporating method is performed (step 51). When the operation is confirmed, the FPG recorded in the external storage device in the previous step 112 is executed.
A8 device embedded program data is read (step 52). Next, enter the manufacturing process of FPGA,
Through the previous process even before ion implantation into the channel formation region of each transistor (step 53), "1", "1",
Regarding the write data of “0”, in the manufacturing process, the switch transistor corresponding to the data of “1” is set to an OFF state (data “1”) in the operating state by the mask processing in the manufacturing process, and “0” is stored in the corresponding memory cell. "
Is set to such a high threshold that rewriting cannot be performed. This is performed by implanting more ions into the channel formation region of the switch transistor by mask processing (step 54). As a result, the switch transistor set to the high threshold value is in a state where the write data of the corresponding memory cell is fixed to “1” in the operation state. The reason is that the floating gate of the switch transistor and the floating gate of the transistor forming the corresponding memory cell are combined or integrated. Then, as a subsequent process, a floating electrode, a gate electrode, a source region,
A FPGA is manufactured by forming a drain region and the like (post-process) (step 55). Thus, the FPGA is manufactured as a normal mass-produced semiconductor device. Finally, the FPGA that has undergone the above-described steps is put into an operating state, and data writing processing of “0” is performed on the flash memory (step 5).
6). Thus, as described above, the memory cell corresponding to the switch transistor for which the high threshold value is set maintains the write state of “1” without writing “0”, and the connection (“0”) ) Is written into the memory cell corresponding to only the switch transistor to be set to (0). In this case, needless to say, in the collective erasing type, it is possible to perform the collective erasing, write "1" in all the memory cells, and then write "0". As a result, the memory cell of only the switch transistor that is originally in the connection state becomes “0”, and the memory cell of the switch transistor that is in the cutoff state maintains the state of “1”, and the integration of the target device is completed. . The FPGA manufactured at this time is fixed as a ROM by setting the operation threshold of the switch transistor high for “1” of the write data in the memory cell area 4. Since the switch transistor for writing the memory cell “1” is no longer programmable as in the state of the prototype, it operates in a stable state as a mass-produced product. Moreover,
In the operation, since the internal wiring is in the same state as the FPGA at the time of the prototype, the same performance as that of the prototype can be obtained. Therefore, there is no need to redesign as a mass-produced product. Also,
When the threshold value of the switch transistor on the side set to “0” is set to a value lower than usual, the corresponding switch transistor is written in a more stable state with “0” written.
Is maintained. As a result, the incorporated device can be operated as a more stable FPGA than in the prototype. FIG. 2 shows the case where the data “1” in the memory cell area 4 in step 53 cannot be rewritten.
It is explanatory drawing of the manufacturing process which performs OM processing. First, FIG.
FIG. 3 is a cross-sectional view of a semiconductor device for one of the switch cells of the flash memory in the memory cell region 4. This includes, as shown in FIG. 2A, an EEPROM forming area EEPROM and a switch transistor forming area SW.
Tr and an erasing device formation region FN having a tunnel window for batch erasing are provided. Each of these regions is a P-type silicon substrate (P
First, an N-well region 21 is formed on the surface of (-SUB) 20. Specifically, thermal oxidation is performed to form a SiO ₂ film on the surface, the portion other than the N-well region 21 is covered with a resist, the resist is used as a mask to etch and expose the N-well region 21, and phosphorus is ionized. Injection, then 1200
It is formed by performing a heat treatment at about ゜ C for about 10 hours.

Next, a field isolation region (Field-OX) 22 is formed as an element isolation region. In this method, after removing an oxide film, an oxide film having a predetermined thickness is formed, a nitride film is further formed, a portion other than the element isolation region is covered with a resist, and the nitride film is etched. Then, heat treatment is performed to grow an oxide film. As a result, a cross-sectional view as shown in FIG. 2A is obtained corresponding to the formation area of the EEPROM as the memory, the SWTr formation area as the switch transistor, and the erase device formation area FN. In the drawing, two switch cell areas of the plurality of switch cells are represented by A and B, respectively. Next, a region other than the SWTr formation region is covered with a resist, and boron is implanted at a low level through the oxide film using the resist as a mask. At this time, the impurity concentration of boron is a low amount at which the transistor formed in the SWTr formation region is set to the ON state.
This is a sectional view as shown in FIG.

Further, a transistor formed in the SWTr formation region is set to an OFF state. This is, for example,
The switch transistor SWTr in the area A is turned on, and the switch transistor SWTr in the area B is turned off.
If it is set to the state, the portion of the area A in the ON state is covered with the resist 23. Further, the area other than the switch transistor SWTr in the area B or the switch transistor area in another area to be set to the OFF state is covered with a resist.
Using this resist 23 as a mask, boron is further implanted through the oxide film at a high concentration level. This is shown in FIG.
A sectional view as shown in FIG. At this time, the switch transistor SWTr in the B region has a higher operation threshold value in the channel region than the switch transistor SWTr in the A region. As a result, the impurity concentration of the channel region of each switch transistor SWTr differs,
The channel region of the OFF transistor portion is set to a high concentration, and a transistor in an OFF state is formed. In this case, the mask for forming the resist is:
In accordance with the device-incorporated program data stored in the external storage device in step 112 of FIG. 3, it corresponds to the position of "0" data. Thus, this region usually has a low operation threshold such that the switch transistor is set to ON.

After that, a resist and a field isolation region 2
The gate oxide film 24 is formed to have a predetermined thickness by removing the oxide film and the nitride film when the gate insulating film 2 is formed. Further, a tunnel oxide region is formed by etching corresponding to the erase device formation region FN, and the EEPROM formation region and the SW are formed.
Polysilicon is volumetrically formed in the entire Tr forming region and the erasing device forming region FN, and phosphorus is ion-implanted into the polysilicon to form the floating gate electrode layer 25. Further, an interlayer insulating film 26 is formed in the order of an oxide film (O), a nitride film (N), and an oxide film (O) to form an ONO film. This is a sectional view as shown in FIG. Finally, a control gate electrode is formed on the ONO film and etched to form a source region and a drain region in each transistor forming region, thereby forming a transistor shown in FIG.
A transistor having a sectional view as shown in FIG. Note that the transistor in the erase device formation region FN has a tunnel window formed, and therefore has a slightly different structure from other transistors. As a result, a structure as shown in FIG. 4A is formed, and a circuit as shown in FIG. 4B is obtained. In the above case, the switch transistor S in the region A
WTr becomes a switch transistor in an ON state, and BTr
The switch transistor SWTr in the region is a transistor in an OFF state.

As described above, in the flash memory type FPGA constituting the integrated switch cell, the operation in the data writing state for programming and the switch transistor in the operation state are actually set to OFF by the mask processing. The operation of the device when the operation threshold is set (or maintained ON) is substantially the same as the operation of the device because the memory side and the switch transistor side are constituted by the adjacent and common floating gates.
As a result, when the operation in the program writing state is mass-produced, the characteristics are inherited by the embedded device by fixing or keeping the switch transistor OFF according to the program data by the mask performed by the mask, and the same operation as the mass-production product is performed as it is. Promising, with little need for redesign.

As described above, in the embodiment, the threshold value of the channel region of the transistor for setting the switch transistor to the ON state in the operation state is set to the operation threshold value lower than usual, and the ON state is maintained in the operation state. However, it is not always necessary. Since such a threshold value of “0” setting is not set to ON only in the manufacturing process, “0” is written into a memory cell by a program later to set the switch transistor to ON. It is good to guarantee the operation. Therefore, “0” writing may be performed only on the switch transistor that makes this connection (“0”). In the embodiment, the impurity concentration of the channel region of the switch transistor is selectively set to a high concentration, and the switch transistor is turned off in the operating state.
The switch transistor is fixed in the OFF state by keeping the impurity concentration of these channel regions high including the region of the EEPROM and the region of the other transistors corresponding to the erase device formation region FN. Is also good.

[0019]

As described above, according to the present invention, a switch cell in which a floating gate of a transistor and a switch transistor of an electrically writable nonvolatile memory is combined or integrated. In a FPGA having a large number of devices, data is written in a program process to incorporate a device, and the operation in a state where the data is written and the state of the switch transistor to be turned off are selectively performed in a mask process in a manufacturing process. Is set to OFF regardless of the write data to form a device. As a result, there is almost no difference in operating characteristics between the state in which the device is incorporated in the program processing and the operation in which the switch transistor is selectively fixed to OFF in the mask processing and the device is incorporated to operate. I'm done. As a result, by using an FPGA as a mass-produced product and fixing the state of the switch transistor to OFF in the operation state, it is possible to realize a semiconductor device that requires little redesign and can expect stable operation. .

[Brief description of the drawings]

FIG. 1 is a flowchart of a device manufacturing process based on device-incorporated data into an FPGA to which an embodiment of a semiconductor device manufacturing method using an FPGA according to the present invention is applied;

FIG. 2 is an explanatory diagram of device formation of an FPGA in a manufacturing process.

FIG. 3 is a flowchart of a process of incorporating a device into an FPGA.

4A and 4B are explanatory views of the structure of a switch cell, wherein FIG. 4A is an external view thereof, FIG. 4B is a circuit diagram thereof, and FIG. 4C is a cross-sectional view of the switch transistor portion. .

FIG. 5 is an explanatory diagram of a tile.

FIG. 6 is an explanatory diagram of a structure of a flash memory type FPGA.

FIG. 7 is an explanatory diagram of the switch cell and matrix wiring connection.

[Explanation of symbols]

1, 11 tile, 2 tile connection wiring matrix, 3 tile outside wiring matrix, 4 memory cell area, 5 basic logic gate area, 6 connection formation area, 7
Matrix connection wiring, 8 FPGA (field programmable gate array), 14 bad, 20 silicon substrate (PSi-SUB), 21 N-well region, 22 field isolation region, 23 gate oxide film,
24 ... Floating gate electrode, 25 ... Interlayer insulating film.

Claims (3)

[Claims] 1. A switch memory comprising a plurality of switch cells in which respective floating gates of a transistor and a switch transistor constituting an electrically writable nonvolatile memory are coupled or integrated with each other. In a method of manufacturing a semiconductor device by a programmable gate array that can be programmed by writing data, an assembling step of writing predetermined program data into the nonvolatile memory and incorporating a predetermined device; An operation checking step of checking the operation of the device incorporated by data; and a mask in a manufacturing step for a switch transistor that is turned off in accordance with the program data for the embedded device whose operation characteristics have been checked in the operation checking step. O A process of setting an operation threshold value for maintaining an OFF state even when ON data is written to a transistor constituting the nonvolatile memory corresponding to the switch transistor set to F. . 2. The method according to claim 1, further comprising the step of writing program data for turning on a switch transistor of said switch cell into said nonvolatile memory. 3. The non-volatile memory is a flash memory, and a state of a switch transistor which is turned on when ON data is written to a transistor constituting the non-volatile memory is turned on by mask processing in a manufacturing process. 2. The method for manufacturing a semiconductor device by a programmable gate array according to claim 1, wherein the operation threshold value is set to a low operation threshold value so as to maintain the threshold voltage.