JP3515362B2 - Non-volatile semiconductor memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory using a memory transistor having a floating gate and a control gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: E) whose memory cell is a single transistor
lectricaly Erasable Programmable ROM)
2 with floating gate and control gate
Each memory cell is composed of a transistor having a double gate structure. In the case of such a transistor having a double gate structure, information is written by accelerating hot electrons generated on the drain side of the floating gate to the source side, passing through the gate insulating film and injecting the electrons into the floating gate. Then, information is read by detecting a difference in operating characteristics of the memory cell transistor depending on whether or not electric charge is injected into the floating gate.

There are roughly two types of structures of such memory cells, one is called a stack gate type and the other is called a split gate type. In particular, the split-gate memory cell has a drain 1 as shown in FIG.
A floating gate 4 is partially formed on the channel formed between the source 2 and the source 2 via the insulating film 3 so as to partially overlap the source region 2, and a control gate 5 is partially formed via the insulating film 6. Are formed so as to overlap the floating gate 4. The drain region 1 becomes a region common to the adjacent cell and is connected to the bit line 8 via the contact hole 7. Further, the source region 2 also becomes a region common to the adjacent cell.

FIG. 4 shows a schematic structure of a non-volatile semiconductor memory using such a split gate type memory cell. In a memory cell array 11 in which a plurality of memory cells 10 are arranged in n × m rows and columns, each memory cell 10 has n word lines WL (0 to n-1) and m bit lines. The control gate (5 in FIG. 3) of the memory cell 10 arranged at the intersection of BL (0 to m-1) has the word line W
It is connected to L, and the drain (1 in FIG. 3) is connected to the bit line BL. The sources (2 in FIG. 3) of the memory cells 10 in each row connected to the adjacent word line WL are connected to the common source line SL (0 to n / 2-1), respectively. For example, the memory cells connected to the word lines WL0 and WL1 are connected to the common source line SL0. Row address decoder 12
Selects one of the word lines WL based on the applied row address data RAD, and signals ES and P indicating an erase mode, a program mode and a read mode, respectively.
A voltage according to each mode is supplied to the selected word line WL based on G and RE. Further, the row address decoder 12 supplies a voltage according to each mode to the common source line SL associated with the selected word line WL. The column address decoder 13 selects one of the bit lines BL based on the applied column address data CAD, and the write / read control circuit 14 writes to the selected bit line BL according to the program mode signal PG and the read mode signal RE. Apply a controlled voltage.

On the other hand, each bit line BL and potential line ARGND
In order to prevent the bit line from being discharged in the erase mode and the read mode and erroneous writing in the program mode, it is controlled by the inversion signals * Y0 to * Ym-1 of the decode output of the column address decoder 13. MOS transistors 15 are provided respectively. For example,
As a result of decoding the column address data CAD in the read mode and the program mode, the bit line B
When L0 is selected, its decode output * Y0 is "L"
It becomes the level, and other decode outputs * Y1 to * Ym-1
Becomes "H" level. Therefore, the selected bit line B
The bit lines BL1 to BLm-1 other than L0 are connected to the potential line ARGND via the MOS transistor 15 which is turned on.

Next, the erase mode, program mode, and read mode of the nonvolatile semiconductor memory will be described with reference to FIGS. 3 and 4. (1) Erase Mode When the erase mode signal ES becomes active, the row address decoder 12 applies the erase voltage Ve (eg, 14.5V) to the word line WL (eg, WL0) selected by the row address data RAD. However, other non-selected word lines WL1 to WLn-1 are connected to the ground voltage (0
V) is applied. Further, the row address decoder 12 is
A ground potential is applied to all common source lines SL0 to SLn / 2-1.

On the other hand, since the column address decoder 13 sets all the decode inversion outputs * Y0 to * Ym-1 to the "H" level, all the MOS transistors 15 are turned on and all the bit lines BL are potential lines. Connected to ARGND. At this time, since the potential line ARGND is at the ground potential, all the bit lines BL are in the state where the ground potential is applied. Therefore, the erase voltage 14.5 is applied to the control gates 5 of all the memory cells 10 connected to the word line WL0, and 0 V is applied to the drain 1 and the source 2. In the memory cell 10, the capacitive coupling between the source 2 and the floating gate 4 is significantly larger than the capacitive coupling between the control gate 5 and the floating gate 4. Therefore, the potential of the floating gate 4 at this time is It is fixed to 0V which is the same as the source 2 by the capacitive coupling of the source 2, the potential difference between the control gate 5 and the floating gate 4 becomes 14.5V, and the F-N tunnel current (Fowler-Nordheim Tunnel Current) becomes a tunnel oxide film (6a in FIG. 3). Flowing through. That is, the electrons injected into the floating gate 4 are extracted from the protruding portion of the floating gate 4 to the control gate 5. Thus, the memory cells 10 connected to one word line WL are collectively erased. (2) Program Mode (Write Mode) When the program mode signal PG becomes active, the row address decoder 12 causes the word line WL (eg, W) selected based on the applied row address data RAD.
Select voltage Vgp (for example, 2.0 V) is applied to L0), and the other unselected word lines WL1 to WLn-
A ground wire pressure of 0 V is applied to 1. Further, the row address decoder 12 applies the program voltage Vp (for example, 12.2) to the common source line SL0 related to the selected word line WL0.
V) is supplied. On the other hand, the column address decoder 13
Connects the bit line BL (for example, BL0) selected based on the column address data CAD to the write / read circuit 14. Therefore, the selected bit line B
A voltage based on the write data applied to the input / output terminal I / O is applied to L0. For example, when "0" is applied to the input / output I / O, the writable source voltage Vse (0.9V) is applied to the bit line BL0 and "1" is applied to the input / output I / O. If yes,
The write inhibit source voltage Vsd is applied to the bit line BL0.
(4.0V) is applied. Further, the other unselected bit lines BL1 to BLm-1 are connected to the potential line ARGND set to the write inhibit voltage Vsd (4.0V) by the MOS transistor 15.

Therefore, in the memory cell 10 designated by the word line WL0 and the bit line BL0, the input / output I / O is "0".
In case of, the source 2 is 12.2V and the drain 1 is 0.9.
V, 2.0 V is applied to the control gate 5. As a result, carriers flow from the drain 1 to the source 2. However, due to the capacitive coupling between the floating gate 3 and the source 2, the voltage of the floating gate 4 becomes almost the same as the potential of the source 2. Therefore, carriers are injected as hot electrons into the floating gate 4 through the insulating film 3. On the other hand, in the memory cell 10 which is not selected, the voltage of the drain 1, the source 2 and the control gate 5 does not satisfy the program condition, so that the floating gate 4 is not injected. (3) Read Mode When the read mode signal RE becomes active, the row address decoder 12 applies the selection voltage Vgr (4.0 V) to the word line WL (eg, WL0) selected based on the row address data RAD. At the same time, the ground voltage (0V) is applied to all the common source lines SL. On the other hand, the column address decoder 13 selects the bit line BL (for example, B) selected based on the column address data CAD.
L0) is connected to the write / read circuit 14. As a result, the data held in the memory cell 10 selected by the word line WL0 and the bit line BL0 is read. On the other hand, the unselected bit lines BL1 to BLm-1 are
MO to the potential line ARGND held at the ground voltage (0V)
It is connected through the S transistor 15. This allows
When the column address transitions, the initial state of reading of the other bit line BL is 0V to the write / read circuit 1
It is biased by 4, so that a malfunction of reading can be prevented.

As described above, in each mode, the erase condition, the program condition and the read condition of the memory cell 10 are satisfied by selectively applying a predetermined voltage to the word line WL, the bit line BL and the common source line SL. it can.
In standby modes other than the above modes, the MOS
All the transistors 15 are turned on, connected to the potential line ARGND set to the ground voltage 0V, and all the bit lines BL are discharged to 0V.

[0010]

In the non-volatile semiconductor memory of FIG. 4, as semiconductor manufacturing technology advances, miniaturization further advances, and if the storage capacity increases to 16 Mbits, 32 Mbits, and even 64 Mbits, the bit line becomes larger. The parasitic capacitance of BL increases dramatically. That is, since the junction capacitance of the drain 1 is connected in parallel to one bit line BL, if the number of connected memory cells 10 is doubled or quadrupled, the parasitic capacitance is also doubled or quadrupled. Of. As a result, the load of the write calling circuit 14 increases, and the write time and the read time increase. Further, the bit line BL is connected to the potential line ARGN by the MOS transistor 15.
The time for connecting to D and discharging (or precharging) to a predetermined voltage also becomes long. As a result, the operation speed of the non-volatile semiconductor memory is reduced and the characteristics are deteriorated.

[0011]

The present invention has been made in view of the above points, and firstly, a memory in which a plurality of nonvolatile memory cells are arranged in a plurality of word lines and bit lines. In a nonvolatile semiconductor memory including a cell array, a row decoder that selects the word line based on row address data, and a column decoder that selects the bit line based on column address data, the memory cell array includes the column address. A plurality of main bit lines connected to the decoder, a plurality of divided bit lines connected to each of the main bit lines, and a selection for selecting any one of the plurality of divided bit lines and connecting to the main bit lines A transistor is provided, which allows the divided bit lines to be selectively connected to the column address decoder. So that the capacitive load seen readout circuit is reduced.

Secondly, the gate electrode of the select transistor related to one main bit line is extended and the gate electrode of the discharge transistor related to the adjacent main bit line is shared by one gate electrode wiring. As a result, it becomes possible to lay out selection transistors and the like having an arrangement pitch larger than that of the memory cells without increasing the chip size.

[0013]

1 is a plan view showing a pattern layout of a memory cell array portion, and FIG. 2 is a circuit diagram showing a circuit configuration thereof. First, referring to FIG.
The circuit configuration of this embodiment will be described. In FIG. 2, a row address decoder 12 and a column address decoder 13
Since the write / read circuit 14 is almost the same as the circuit shown in FIG. 4, the description thereof will be omitted.

The memory cell array has a structure in which memory cells 7 are arranged in rows and columns of k × 2 m. Word lines are WL0 to WLk-1, and common source lines are SL0 to SLk / 2-1. The main bit lines derived from the column address decoder 13 are BL0 to BLm-1. Main bit line BL
The first divided bit lines BLa0 to BLa0 to each of 0 to BLm-1.
Two divided bit lines, Lam-1 and second divided bit lines BLb0 to BLbm-1, are provided, and this memory cell array is connected to the first divided bit lines BLa0 to BLam-1 in a first cell array. Block and second divided bit lines BLb0 to BLb
It is separated into two blocks, that is, a second cell array block connected to Lbm-1. As a result, m main bit lines B
The number of divided bit lines is twice that of L0 to BLm.

A control signal DCB is provided between each of the first divided bit lines BLa0 to BLam-1 and each of the main bit lines BL0 to BLm-1.
A first select transistor Q0 controlled by La
Q4 is provided. Furthermore, each first divided bit line BLa0
Between BLam-1 and the potential line ARGND, a control signal DC
Select transistors (first discharge transistors) Q2 and Q7 controlled by BLb are provided.
Similarly, second selection transistors Q1 and Q5 controlled by a control signal DCBLb are provided between the second bit lines BLb0 to BLbm-1 and the main bit lines BL0 to BLm-1, respectively. 2 bit lines BLb0 to BLbm-1 and potential line A
Select transistors (second discharge transistors) Q3 and Q6 controlled by the control signal DCBLa are provided between RGND.

The control signals DCBLa and DCBLb are output from an address data detection circuit (not shown) according to the content of the address data. That is, the control signal DC
BLa has the first divided bit line BLa0 whose address data is first.
~ BLam-1 is a signal that goes to "H" level when the first cell array block connected to BLam-1 is selected, and the control signal DCBLb has address data of the second divided bit lines BLb0 to BLbm-1. It is a signal that becomes "H" level when the second cell array block connected to is selected. Therefore, when the control signal DCBLa becomes "H", the selection transistors Q0 and Q3 are turned on and the first transistor
Divided bit line BLa0 is connected to the main bit line BL0, and the second divided bit line BLb0 is connected to the potential line ARGND.
Connected to. Further, when the control signal DCBLb becomes the “H” level, the above operation is reversed.

The potential relation of the memory cell array 11 in each operation mode (erase mode, program mode, read mode) of this embodiment is the same as that of the conventional example, and therefore its explanation is omitted. Since the control signals DCBLa and DCBLb are mutually inverted signals, that is, complementary signals, one of the divided bit lines BLa0 and BLb0 is connected to the main bit line BL0, and the other is connected to a predetermined potential by the ARGND wiring. Thus, the operation of selecting a specific cell in the memory cell array is different from the conventional example.

In addition, in the standby modes other than the above-mentioned operation modes, it is necessary to discharge all the bit lines of the memory cell array to the ground voltage in order to prevent malfunction and to rapidly rise to the next mode. . Therefore, the control signals DCBLa and DCBLb are set to the “H” level, and the column address decoder 1
All 0 outputs * Y are also at "H" level. This allows
The selection and discharge transistors Q0 to Q7 are all turned on, and the main bit line BL and the divided bit lines BLa, B
Lb is connected to the potential line ARGND set to the ground voltage and discharged.

FIG. 1 is a plan view showing a pattern layout of an integrated circuit device embodying the above-mentioned circuit configuration.
In the memory cell array 11 arranged near the center of the drawing, each memory cell 10 is composed of the floating gate type flash memory device shown in FIG. That is,
The word lines WL0 to WLk-1 are formed by extending the control gates 5 of the elements, and the common source lines SL0 to SLk-1 are formed by extending the source region 2 across each memory cell 10. Further, the first and second divided bit lines BLa0 to BLam-1, BLb0 to BLbm-1 are connected to the drain region 1 of each memory cell 10 through the contact holes 7.

Select transistors Q0, Q1, Q4, and Q5 are arranged on both sides of the memory cell array 11 (upper and lower sides of the memory cell array 11 in FIG. 1), and discharge transistors Q2, Q4, Q6, and
Q7 is placed, and further outside it, there is a predetermined potential AR
Electrode wiring 20 for applying GND and control signal DCBL
Electrode wirings 21 and 22 for applying a and DCBLb are arranged. First and second divided bit lines BLa0, BL
With b0 and one set of select transistors Q0 and Q1 and one set of discharge transistors Q2 and Q3 as one unit, these are formed in a repeating pattern of substantially the same pitch. Further, the other two divided bit lines BL are arranged so that the target pattern is centered on the memory cell array 11.
a1, BLb1, a set of select transistors Q4, Q5, and a set of discharge transistors Q6, Q7 are arranged on the opposite side of the memory cell array 11. Furthermore, the first and second divided bit lines BLa related to the main bit line BL0
0 and BLb0 extend from the lower part of the drawing where the selection transistors Q0 and Q1 are located to the upper part of the drawing where the selection transistors Q4 and Q5 are located, and are terminated, while the first and the first ones involved in the adjacent main bit line BL1 The second divided bit line BLa1,
BLb1 extends from the upper side of the drawing to the lower side of the drawing and is terminated.
These divided bit lines are alternately staggered like a first divided bit line BLa0 related to one main bit line BL0 and a first divided bit line BLa1 related to an adjacent main bit line BL1 next to it. Deploy. That is, the divided bit lines are arranged in parallel in the order of BLa0, BLb0, BLa1, BLb1 ... At equal intervals. By alternately arranging the memory cells in this manner, the selection and discharge transistors having a pattern size larger than the cell pitch of the memory cell array 11 were housed within the cell pitch range.

Select transistors Q0, Q1 and Q4, Q5
Is a MOS-type transistor in which two gate electrodes are arranged in a common active region 30 (a sand-like filled portion in the drawing) surrounded by a LOCOS oxide film, and a common source (or drain) is formed. Composed of. The common source (or drain) is connected through a through hole to main bit lines BL0 and BL1 which are simply shown by bidirectional arrows, and the connected main bit lines are connected to a column address decoder 13. The main bit lines BL0 and BL1 are divided into first and second divided bit lines BLa0 to BLam-1 and BLb0 to B.
It is composed of electrode wirings extending in parallel with Lbm-1 and having interlayer insulation. In this embodiment, the select transistors Q0 and Q1 installed below the memory cell array are the main bit lines BL.
0, select transistors Q4 and Q5 installed above the memory cell array are connected to the main bit line BL1.

Similarly, the discharge transistor Q2,
Q4, Q6, and Q7 also have a common active region 31 surrounded by a LOCOS oxide film (sand-like filled portion in the figure).
In addition, it is composed of a MOS type transistor in which two gate electrodes are arranged and the source (or drain) is commonly used. The common source (or drain) has a predetermined potential ARG
It is connected to the electrode wiring 20 which applies ND. The select transistors Q0 and Q1 and the discharge transistors Q2 and Q4 are arranged so that their active regions 30 and 31 are staggered.

The first divided bit line BLa0 related to the main bit line BL0 is connected to the drain (or source) of the first select transistor Q0 via a contact hole, and is oblique as it is at an angle of about 45 degrees. The first discharge transistor Q2 is connected to the drain (or the source) of the first discharge transistor Q2 via the contact hole. Second
The divided bit line BLb0 is connected to the drain (or source) of the second select transistor Q1 and also extends diagonally in parallel with the divided bit line BLb0 to the drain (or source) of the second discharge transistor Q3. Connected. Similarly, the first divided bit line BLa1 involved in the main bit line BL1 is connected to the selection transistor Q4 and the discharge transistor Q7, and the second divided bit line BLb1 is connected to the selection transistor Q5 and the discharge transistor Q6.

The first gate electrode wiring 25 of the second selection transistor Q1 extends linearly on the chip to serve as the gate electrode of the first discharge transistor Q2,
It further extends and is connected to the wiring 22 of the selection signal DCBLb via a through hole. At this time, the first gate electrode wiring 25 is composed of a polysilicon wiring layer continuously extending from the gate electrodes of the transistors Q1 and Q2. Similarly, the second gate electrode wiring 23 of the first selection transistor Q0 extends on the chip so as to be orthogonal to the diagonal portion of the first divided bit line BLa0 and is connected to the adjacent main bit line. It becomes the gate electrode of the second discharge transistor (corresponding to the transistor Q3) and is connected to the wiring 21 of the selection signal DCBLa. This is also composed of a polysilicon wiring layer continuous from the gate electrode of each transistor. The first divided bit line BLa0 and the second gate electrode wiring 23, and the second divided bit line BLb0 and the second gate electrode wiring 27 are insulated by interlayer insulation and intersect with each other.

Since each transistor is constituted by a continuous repeating pattern, the second gate electrode wiring 27 of the second discharge transistor Q3 has a select transistor (corresponding to the select transistor Q0) related to the adjacent main bit line. Gate electrode wiring (second gate electrode wiring 23
Is equivalent to). Further, the gate electrode wiring 26 of the selection transistor Q4 and the gate electrode of the discharge transistor Q6, and the gate electrode wiring 24 of the selection transistor Q5 and the adjacent bit are formed in a shape symmetrical with the arrangement of the memory cell array 11 therebetween. The gate electrode of the discharge transistor related to the line is connected.

As is clear from the above circuit operation, the control signals DCBLa and DCBLb are complementary signals to each other, so that the main bit line BL0 is selected and the control signal D is selected, for example.
When CBLa is "H", the second gate electrode wiring 2
3 turns on the first selection transistor Q0,
The second selection transistor Q1 and the first discharge transistor Q2 are turned off by the gate electrode wiring 25 of
Therefore, only the first divided bit line BLa0 can be connected to the main bit line BL0. Also, since the second discharge transistor Q3 is turned on by the second gate electrode wiring 27, the second divided bit line BLb0 can be connected to the predetermined potential ARGND. On the other hand, when the control signal BLb0 becomes “H”, the second selection transistor Q1 and the first discharge transistor Q2 are turned on by the first gate electrode wiring 25, so that the second
Selected divided bit line BLb0, and the first divided bit line B
La0 can be connected to the predetermined potential ARGND.

In this way, in view of the combination of the transistors that apply the complementary signals, the first selection transistor Q0 and the second discharge transistor that apply the same signal are connected to the second selection transistor Q1 and the first discharge transistor. The number of wirings is reduced and the pattern is simplified by connecting the transistor Q2 with one gate electrode wiring 23 and 25, respectively. In addition, the second gate electrode wiring 23 can shorten the wiring length by connecting the first select transistor Q0 and the second discharge transistor related to the main bit line adjacent to the first select transistor Q0.

In the embodiment shown in FIG. 1, the memory cell array is divided into the first and second cell array blocks, but it is divided into 4 blocks or 6 blocks. You may. For example, in the case of dividing into four blocks, a pattern having the same configuration as the pattern of FIG. 1 is repeatedly arranged to form third and fourth cell array blocks. In this case, the control signals corresponding to the control signals DCBLa and DCBLb are, for example, DCBLc and DCBLd,
Although the signals are complementary to each other, the row address data RA
When either the first cell array block or the second cell array block is selected by D, the control signals DCBLc and DCBLd are selected.
Sets the bit lines of the third and fourth cell array blocks to the floating state at the "L" level so that they are not connected to the main bit lines. Conversely, when the third and fourth cell array blocks are selected, the control signal DCBL
a and DCBLb become "L" level.

[0029]

As described above, the first and second divided bit lines BLa and BL of the divided cell array block are divided.
Since b is connected to the main bit line BL of the column address decoder 10 only when the block is selected, the capacitive load of the write / read circuit 11 is reduced. In addition, the divided bit lines of the cell array block which are not selected are connected to the potential line ARG by the discharge transistor.
Since the block is connected to the ND, the initial value becomes constant when the block is selected, and malfunction can be prevented. Moreover, since the applied voltage condition in each mode can be achieved by the low capacitive load, high-speed operation of the nonvolatile semiconductor memory can be realized.

Furthermore, the arrangements of the selection transistors Q0 and Q1 and the discharge transistors Q2 and Q3 are shifted,
By connecting the elements by connecting the gate electrodes like the first and second gate electrode wirings 23 and 25, the number of wirings can be reduced and the pattern can be simplified. At this time, by connecting the second gate electrode wiring 23 to the first select transistor Q0 and the second discharge transistor related to the main bit line adjacent to the first select transistor Q0, the wiring can be shortened. By simplifying the wiring between the select transistors Q0 and Q1 and the discharge transistors Q2 and Q3 and narrowing the arrangement interval, the chip size can be reduced without unnecessarily increasing the cell pitch of the memory cell array 11.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a cell structure of a nonvolatile semiconductor memory.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

10 memory cells 11 memory cell array 12 row address decoder 13 column address decoders BL0, BL1 main bit lines BLa, BLb divided bit lines Q0, Q1, Q4, Q5 select transistors Q2, Q3, Q6, Q7 discharge transistors

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (56) Reference JP-A-7-235650 (JP, A) JP-A-8-203291 (JP, A) JP-A-9 -331030 (JP, A) JP 11-232891 (JP, A) JP 11-250680 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/06 H01L 27/10 H01L 27/115 H01L 29/788

Claims (4)

(57) [Claims] 1. A memory cell array in which a plurality of non-volatile memory cells are arranged in a plurality of word lines and bit lines, a row decoder for selecting the word lines based on row address data, and a row decoder based on column address data. In a non-volatile semiconductor memory including a column decoder that selects a bit line, a plurality of main bit lines connected to the column address decoder are connected to the bit line, and first and second main bit lines are respectively connected to the main bit line. Divided bit lines are provided, first and second select transistors for selecting one of the first and second divided bit lines and connecting to the main bit line are provided in the peripheral portion of the memory cell array, First and second
First provided between the divided bit lines and the predetermined potential
And a second discharge transistor are provided, and the gate electrode of the second select transistor provided between the main bit line and the second divided bit line serves as the first gate electrode wiring and has the predetermined potential. And the first selection bit provided between the main bit line and the first divided bit line, the selection being continuous with the gate electrode of the first discharge transistor provided between the main divided bit line and the first divided bit line. The gate electrode of the transistor serves as the second gate electrode wiring, and is used as the first discharge transistor.
A non-volatile semiconductor memory characterized by being connected to a gate electrode of another discharge transistor adjacent to the transistor . 2. The nonvolatile semiconductor memory according to claim 1, wherein the second gate electrode wiring extends so as to intersect with the first divided bit line. 3. The first and second selection transistors,
2. The non-volatile semiconductor memory according to claim 1, wherein the source (or drain) is a transistor having a common region. 4. The non-volatile semiconductor memory according to claim 1, wherein the first and second discharge transistors are transistors whose sources (or drains) are formed in a common region.