JPH02310683A - Formation of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the developing period of a semiconductor integrated circuit device by a portion corresponding to the test period of a peripheral circuit by converting an EPROM into a mask ROM without changing the peripheral circuit such as a microcomputer, etc. CONSTITUTION:The oscillation circuit OSC of the semiconductor integrated circuit device LSI forms a clock pulse necessitated for a CPU by using a crystal oscillator Xtal. A RAM is a volatile storage circuit, and is used mainly as the temporary storage circuit of a program during execution or data in the course of calculation. A ROM is a non-volatile storage circuit, and stores the program of these RAM and ROM is provided with a control circuit necessary for the reading operation or the writing operation of a storage element. Besides, the above-mentioned ROM is constituted of the EPROM or the mask ROM. The EPROM is used exclusively for the write-in and the erasure of information after the manufacturing process of the LSI, and the mask ROM is used exclusively for the read-out of the information, and the write-in of the information to them is made capable of being executed during the manufacturing process of the LSI.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device mounted in an electronic device, and is particularly applicable to a semiconductor integrated circuit device having a microcomputer equipped with a nonvolatile memory circuit. It is about effective techniques.

[Conventional technology]

Semiconductor integrated circuit devices (LSIs) that have microcomputers installed in electronic devices undergo sufficient initial evaluation (debugging) such as system checks and circuit checks in the early stages of development, which prevents damage to internal data and internal logic. It is desirable to be able to do this easily, and for this reason, EPR is used as a storage element for writing microprograms, data programs, etc.
OM (Eraaable and Electrica
lly Progranyna-ble Read 0
There is a trend to mount large amounts of memory (nly memory) on semiconductor integrated circuit devices.

EPROM is a nonvolatile memory circuit that electrically writes information and erases information using ultraviolet light, and the information can be rewritten after the manufacturing process. The technology for this ridge is described in, for example, Japanese Patent Laid-Open No. 188234/1983.

That is, a semiconductor integrated circuit device equipped with an EPROM is used as a storage element in which a program is written until an initial evaluation is performed and a program for controlling the microcomputer is determined.

When the initial evaluation is completed and the program to be controlled by the microcomputer is determined, the EPR is used as a storage element.
There is no need to use OM.

E''FROM has a memory cell formed by a field effect transistor with a fake two-layer gate electrode, so the manufacturing process is complicated and requires a large number of manufacturing steps.EpROM also requires an outdoor erase window. This increases the manufacturing cost of the package.For this reason, the manufacturing cost of a semiconductor integrated circuit device having a microcomputer equipped with an EPRUM becomes high.Furthermore, when the semiconductor integrated circuit device is mass-produced, Since it is necessary to write the determined program to EPRO 1, the information writing time becomes long.

Therefore, after determining the program in a semiconductor integrated circuit device having a microcomputer equipped with the EPROM, a new semiconductor integrated circuit device having a microcomputer equipped with a mask ROM was developed, and the program was determined in the mounted mask ROM. The program is being written. The mask ROM is a non-volatile memory circuit dedicated to displaying information, and information is written therein during the manufacturing process. The mask ROM has a simple structure in which a field effect transistor with a single-layer gate electrode structure is used as a memory cell, and the manufacturing process is simple and requires a small number of manufacturing process types. Also, the mask ROM.

Since the UV-erasing window used in EPROMs is not required, the cost of manufacturing the package can be reduced. In other words, a semiconductor integrated circuit device having a microcombination device equipped with a mask ROM is low in price and suitable for mass production, and as a result, the cost of electronic equipment can be reduced.

(Original Problem to be Solved by the Invention) The present inventor discovered the following problem during the development of a semiconductor integrated circuit device having the above-mentioned microcomputer.

However, the areas other than the mask ROM of the semiconductor integrated circuit device having a microcomputer equipped with the mask ROM, that is, the peripheral circuits such as the microcomputers, are the same as those of the semiconductor integrated circuit device having a microcomputer equipped with an EPROM. The peripheral circuits of these microcomputers and the like are formed using newly created manufacturing masks used throughout the manufacturing process. For this reason, it is necessary to check the manufactured mask itself and perform the same evaluation as the initial evaluation described above again, which is essentially equivalent to developing a new semiconductor integrated circuit device. There has been a problem in that the development period for a semiconductor integrated circuit device including a computer is extremely long.

An object of the present invention is to provide a technology that can shorten the development period in a semiconductor integrated circuit device having a microcomputer (CPU) equipped with a nonvolatile memory circuit.

Another object of the invention is to provide a technique that can reduce the cost of electronic equipment in which the semiconductor integrated circuit device is mounted.

Another object of the present invention is to provide a semiconductor integrated circuit device having a microcomputer equipped with a first non-volatile memory circuit, in which the first non-volatile memory circuit is replaced with a second non-volatile memory circuit as much as possible.
The object of the present invention is to provide a technology that can be converted into a nonvolatile memory circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Means to solve the problem]

A brief overview of one typical invention disclosed in this application is as follows.

Forming a first semi-integrated circuit device having a CPU equipped with an EPROM (or EEPROM), and controlling the CPU while loading and erasing information in the EPROM mounted on the first semi-integrated circuit device. A program or logic is determined, the EPROM of the first semi-isolated integrated circuit device is converted into a mask ROM, and the determined program is written into the mask ROM to form a second semi-isolated integrated circuit device.

In addition, by converting this EPROM to a mask ROM, the peripheral circuits of the mask ROM have basically the same circuit configuration as the peripheral circuits of the EPROM, and the unique peripheral circuits used only for the EPROM are logically inactive. Configure.

[Effect]

According to the above-mentioned means, since the EPROM is converted into a mask ROM without changing the peripheral circuits of the microcomputer, etc., the second
The development period of a semiconductor integrated circuit device can be shortened.

As a result, the first semiconductor integrated circuit device mounted on the electronic device can be easily and quickly replaced with the second semiconductor integrated circuit device, which is cheaper than the first semiconductor integrated circuit device, so that the cost of the electronic device can be reduced.

Hereinafter, the configuration of the invention will be described together with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Embodiment) A semiconductor integrated circuit device having a microcomputer, which is an embodiment of the present invention, is shown in FIG. 1 (block diagram).

As shown in FIG. 1, the semiconductor integrated circuit device LSI is a portion surrounded by a dotted line, and constitutes one chip microcombination unit.

The CPU is a microcomputer (microprocessor)
, Ilo is an input/output port, and this input/output port 10 has a data transfer direction register inside. OSC is an oscillation circuit. l! Although not limited to #, the oscillation circuit O8C includes a crystal resonator Xt
A high-precision reference frequency signal is formed using Al, and a lock pulse required for the microcomputer CPU is formed. RAM is a random access memory (volatile memory circuit), and is mainly used as a temporary storage circuit for programs being executed or data in the middle of an operation.

The ROM is a read-only memory (nonvolatile memory circuit), and stores various information processing programs, dictionary data, and the like. This random access memory RAM,
Each read-only memory ROM includes a control circuit necessary for reading and writing operations of the storage element. Furthermore, these circuit blocks are interconnected by an input/output bus l10BUS centered around the microcomputer CPU. This input/output path l10BUS includes a data bus and an address bus.

The read-only memory ROM mounted on the semiconductor integrated circuit device LSI is configured as shown in FIG. 2 (block diagram of the ROM).

The memory cell array M-A It Y has a plurality of storage elements (memory cells) arranged in rows and columns, and has word! Wt～W
Each of the ms data $D□ to Dn is extended. The X-decoder circuit X-DEC is configured to select a word line W. The Y-decoder circuit Y-DEC is configured to select a data line. Although not particularly limited, X decoder circuit X-DEC, Y decoder circuit Y-DE
Each of C is controlled by a microcomputer CPU via a control circuit C0NT.

The sense amplifier SA sets the signal of the storage element (memory cell) output to the data line to Hi during the information read operation.
It is configured to determine whether the level is gh level or low level, and output it to the input/output bus l10BUS via the data out buffer DOB. This output is controlled by the microcomputer CPU via the first control path C0NT.

X decoder circuit X-DEC and Y decoder circuit Y-DE
C constitutes a decoder circuit. The sense amplifier≦A, the data out buffer DOB, and the control circuit C0NT constitute a read-related circuit.

This read-only memory ROM is composed of an EPROM shown in FIG. 3A (equivalent circuit diagram) or a mask ROM shown in FIG. 3B (equivalent circuit diagram).

EPROM is a nonvolatile memory circuit in which information is electrically written and erased using ultraviolet light, and is configured so that information can be written and erased after the manufacturing process of the semiconductor integrated circuit device LSI. Read Only Memo'Jl
X-decoder circuit X-DE, which is a direct peripheral circuit of tOM
E P ROM is installed in the semiconductor integrated circuit device LSI that performs initial evaluation (debugging) of C, Y decoder circuit Y-DEC, etc. and its indirect peripheral circuits such as microcomputer CPU, random access memory, JRAM, etc. be done. In this initial evaluation, a system check and a circuit check are performed on the circuit block, and in particular, a microprogram and a data program for controlling the microcomputer CPU are determined. In other words, E P R
The OM is configured to be able to perform initial evaluation such as determining the program while repeatedly writing and erasing information.

As shown in FIG. 3A, the memory cell array M-ARY of the EPROM includes words fdW, ~Wm and data '+
Storage element (memory cell) at the intersection with HD 1 to Dn
Qll...Qmn are arranged. The storage element Q has a basic structure of a field effect transistor (FET) having a two-layer gate turtle structure having a floating gate electrode for storing charges serving as information and a control gate electrode.

The X-decoder circuit X-DEC is mainly a unit X-decoder circuit
□~Xm and X level shifter circuit Lxl~LXm,
It is configured.

Unit X decoder circuits X1 to Xm and X level footer circuits Lx, to Lxm are connected to correspond to words mWx to Wm, respectively.

Read i W is selected i4 by the unit X decoder circuit. And the X level shifter circuit is that a? The boosted voltage VPPI (approximately 14V
) and the power supply voltage Vcc (approximately 5 V) in the read mode.

Y-decoder circuit Y-DEC is a raw unit Y-decoder circuit Y
1~Yn, Y level shifter circuit L□~LYn and column switch MIS (Metal-Insulat
or-;emiconductor) FET
It is composed of Y□s to Y□yl.

Unit Y decoder circuits Y1 to Yn and Y level shifter circuits w
! rLyx~Lyn are the corresponding data lines,~
Column switch MISFETY01 to Y to select Dn
onl'l: Connected.

The unit Y decoder circuit and the Y level shifter circuit have basically the same structure as the unit X decoder circuit and the X level shifter circuit, respectively.

Column switch MISFET by unit Y decoder circuit
is selected, thereby selecting the data line.

Then, in the read mode, re is sent from the control circuit C0NT.
ad signal R is output and read selection MISFET Y
Turn RO ON. The signal MS of the storage element (memory cell) output from this K to the data iD is detected by the sense amplifier SA.

In the write mode, the write signal W is output from the control circuit C0NT, and the write selection MISF and ETYwo are set to O.
At the same time, the voltage Vt is set to the write voltage VPP by a program circuit PGC, which will be described later. The data line selected by K is set to the write voltage VPP, and information is written into the selected memory element (memory cell).

The convolution voltage VPP is set to approximately the same level as the convolution base voltage of approximately 12.5V supplied from the outside. (Hereinafter, the write reference voltage will be simply referred to as write voltage vpp.) Column switch MISFET, write selection MISFET
And the read selection MISFET 1c is applied with a high voltage (boosted voltage VPPI, etc.) in the write mode, so for example, nu
(1) i%ilt pressure M I S F E T (HM
IS).

As shown in Figure 48, the X level shifter circuit is
□f OS (Complementary-Meta)
The circuit is composed of inverter circuits IV1 and IV based on l-Oxide-8-layer microconductor.

Inhani 1 time '1151V, k't, pm, MI
It consists of an S FET QHl and an n-type MISFET QHI.

MISFETs QHl, QHz, Qns, and QH4 are composed of high voltage MISFETs (JIS to H).

High pressure MISFET (HMIS) Qas and brass.

One of the sources and drains of is set to a predetermined voltage of 7 times by the side-inverted 1 circuit C0NT.

The control circuit C0NT boosts the write voltage VPP by increasing the voltage Vp.
It includes a booster circuit BCV that boosts the voltage to p-voltage, and sets the voltage V1 to the boosted voltage Vpp* in the write mode. In the read mode, voltage v1 is set to power supply voltage VCC.

Inverter circuit I Vs kt p type M I S F
It consists of E T QLs and nWMIsFET QLx.

The potential V of one of the source or drain of MISFET QLI and the gate electrode of MISFET QL3 is set (connected) to power supply potential VCC.

MISFET QLJ and QL! gate insulating film thickness t
oxx is formed to have the same film thickness as the gate insulating film thickness of MISFET of a circuit (eg, sense amplifier SA, data out buffer DOB, etc.) to which a high voltage (11-inclusive voltage VPP, etc.) is not applied.

The gate insulating film thickness tox1 of the high voltage MI SFET (HMI S ) is formed to be thicker than the gate insulating film thickness tozl of the MISFET 5 to which no high voltage (write voltage VPP, etc.) is applied.

In this way, in EPROM, the gate insulating film thickness to
MISF with gate insulating film thickness tox2 larger than xl
It is composed of ET5.

In addition, M where high withstand voltage (soaking voltage VPP, etc.) is not applied
The gate insulating film thickness of OSFET is not limited to the film thickness tOXl,
MISF E T a with multiple film thicknesses thinner than toxl
It may be composed of

The mask ROM is a nonvolatile memory circuit used only for reading information, and is configured so that information can be written during the manufacturing process of the semiconductor integrated circuit device LSI. Mask ROM
The same program as the program (emotion) for controlling the microcomputer CPU written in the EPROM in the initial evaluation is written in the .

As shown in FIG. 3B, the memory cell array M-ARY of the mask ROM has storage elements (memory cells) Q at the intersections of words tiiW, ~Wrn and data lines D1 to Dn.
11'...Qmn' are arranged. Memory element Q'
The basic structure is a field effect transistor having a single-layer gate electrode structure.

In addition, the read-only memory ROM's X decoder circuit X-DEC, Y decoder circuit Y-DEC, sense amplifier SA, and data out buffer DOB each output information from the EPROM and mask ROM. Since it is a direct peripheral circuit that can be commonly used for operation,
Both ROM and mass ROM have substantially the same structure.

For example, as shown in FIGS. 3B and 4B,
unit X and Y decoder circuit, column switch M I
S F E T and readout selection &i I S F E
The high voltage MISFET (HMIS) with a gate insulation barrier tox* used in T etc. is converted into a MISFET with a gate insulation film thickness toxx in the mask ROM, but the circuit configuration, layout, etc. are virtually the same. It consists of a structure.

That is, column switch MISFET Yot'~
Yon' and the readout selection MISFET YRo' are composed of a MISFET Ta having a gate isolation dk thickness tox2.

MI in the X level shifter circuit as shown in Figure 4B.
SF ET QHI's Qll! ' −Q□′
and Q ii 4 ′ has a gate thickness toxl.

Further, when the EPROM is replaced with a mask ROM, the voltage (1) at one of the sources and drains of QHt' and QHI' is configured to be set (connected) to the power supply voltage VccK.

Also, in the read operation of the EP ROM,
The word line vV supplied from the outside is the power supply voltage -V
The data (ID) is set to approximately the same level as CC, and the data (ID) is set to 1/4 VCC to 1/3 Vcc, which is lower than the power supply voltage Vcc, to prevent erroneous writing during read operations. Even when replaced, the circuit configuration is such that the level of the word hiJW and the level of the data line are approximately the same as described above. Also, an EPROM and a mask ROM can be operated with such a circuit configuration.

In addition, as a direct peripheral circuit (information writing circuit) unique to EPROM, there is a booster circuit BC as shown surrounded by a broken line in FIG.

Data-in buffer DIR and program circuit PG
There is C. These peripheral circuits are used for writing information into the EPROM.

These peripheral circuits are mainly high-voltage MO8FETs.

These peripheral circuits are connected to power supply voltage VCC or write voltage V.
pp (or boosted voltage VPPI) is input. The information to be written is input to the program circuit PGC from the input/output bus l10BUS via the data in buffer DIB or directly from the outside, and the write voltage VPP and the program control signal such as the program control circuit PGM are input to the program circuit PGC. By inputting the signal to the program circuit PGC via the control circuit C0NT, the program circuit PGC outputs a write voltage VPP, thereby writing information into the EPROM.

This direct peripheral circuit (information writing circuit) with EPR (liVc!) remains in a logically inactive state in the semi-dedicated integrated circuit device LSI when replacing EPROM with mask ROM. For example, the information writing system circuit is configured to leave the circuit pattern as it is and to be logically inactive by a control signal.

This logically inactive state is, for example, t# in an EPROM, voltage VCC-? In the mask ROM, the wiring that supplies the write voltage Vpp (or boosted voltage Vpp1) to the storage circuit is connected to the ground potential (GND) V881C.
Consists of connections.

Alternatively, the output wiring of the information writing circuit may be configured not to be connected to other circuits.

Further, although the formation region of the information writing circuit remains, it may be configured to be logically inactive without forming a circuit pattern (without forming any element).

In other words, when a unique peripheral circuit used only for EPROM is replaced with a mask ROM, the circuit area remains unchanged.
By leaving it alone and not forming a circuit pattern, it is possible to reliably configure it into a logically inactive state.

For example, write select MO8FET as shown in Figure 3B.
Peripheral circuits specific to E P ROM such as ywo are configured in a logically inactive state without forming a circuit pattern.

Next, FIG. 1, FIG. 2, FIG. 3A, and FIG. 3B.

Using FIG. 4A and FIG. 4B, the semiconductor integrated circuit device LS
A method for converting the E P ROM mounted on I into a mask ROM will be explained. Here, in the EPROM, memory cells are configured with field effect transistors having a two-layer gate electrode structure, and 1! The #1 gate electrode constitutes a 70-ting gate electrode, the second layer gate electrode constitutes a control gate electrode, and a word plume extending from this.
-Also, the peripheral circuit of EPROM has gate insulating film thickness to
High voltage MISFET (HMTS) with xx and MIS with film thickness tOXz thinner than gate insulating film thickness toxl
It is composed of FETs.

Further, a case will be described in which each circuit block other than the read-only memory ROM block shown in FIG. 1 is constituted by a field effect transistor having a single-layer gate electrode structure formed of a second-layer gate electrode.

(1) Memory cell array M-ARY A mask ROM is constructed in which the 70-ting gate electrode peculiar to the field effect transistor which is the memory cell of the EPROM is deleted, and the memory cell is a field effect transistor having a single-layer gate electrode structure. In other words, in an EPROM, the floating gate'RL pole is formed by the first layer's (Goo)X pole, so if it is replaced with a mask ROM, the first layer's (Goo)! Eliminate the pole formation process. Each circuit block other than the read-only memory ROM block is composed of the second layer gate electrode, so the mask R
No structural changes or changes in electrical characteristics occur due to replacement with OM. Furthermore, as shown in FIGS. 3A and 3B, the memory cells of the g Pit OM are arranged in parallel, so it can be easily replaced with a horizontal mask ROM (a mask ROM in which memory cells are arranged in parallel). be able to.

(2) Decoder circuit DEC and read-out circuit Information written in the memory cell array M-ARY is read out by the X decoder circuit, the X decoder circuit, the sense amplifier SA, the data out buffer DOB, and the control circuit C0NT.

As mentioned above, the direct peripheral circuits used for these read operations have a circuit configuration that allows them to be used in common whether it is an EPROM or a mask ROM, so when replacing an EPROM with a mask ROM, the basic There is no need to change the circuit configuration.

However, since EPROM uses high voltage for write operation, the gate electrode of the field effect transistor of the direct peripheral circuit uses a two-layer gate electrode structure consisting of a first-layer gate electrode and a 2N1-th gate electrode. In some cases, a single-layer gate electrode structure including only a first-layer gate electrode or a second-layer gate electrode is used. In either case, when replacing the mask ROM with a mask ROM, a direct peripheral circuit is constructed using a field effect transistor having a single-layer gate electrode structure with only a second-layer gate electrode.

Note that when replacing a high breakdown voltage MISFET with a gate insulating film thickness toxl in an EPROM with a mask ROM, the gate insulation film thickness [4 thickness tox! It is composed of MISFETs with

At this time, although there is no particular restriction, the circuit constants may be changed.Also, in the former case where the peripheral circuit is configured with field effect transistors with a two-layer gate electrode structure, the first layer gate electrode and the second layer gate electrode If they intersect planarly through an interlayer insulating film, a short-circuit will occur when the mask ROM is used. A mask pattern is formed so that the two gate electrodes do not intersect in plane.

(3) 8-program circuit The information write circuit is mainly used in the case of EPROM, and mainly includes the program circuit PGC, data-in buffer DIB, program control circuit PGM, write voltage vPP, and control circuit C0NT. It consists of Of these, except for the control circuit C0NT (write circuits not used in the mask ROM), when replacing the EPROM with the mask ROM, the 51C is configured to be logically inactive as described above.

(4) Although not shown, the memory cell array M-ARY is EPRO
In the case of M, since it has a circuit that allows direct access to the EPROM from the outside, the circuit is activated so that the mask ROM can be directly accessed even when it is replaced with a mask ROM. This facilitates data checking of the mask ROM.

In this way, when replacing an EPROM with a mask ROM, the circuit area and circuit configuration of the memory cell array M-ARY and peripheral circuits remain unchanged, and the write circuit used only in the EPROM is configured to be logically inactive. .

As a result, when replacing a semiconductor integrated circuit device LSI equipped with an EPROM with a semiconductor integrated circuit device LSI equipped with a mask ROM, design changes such as the circuit configuration can be made with minimal design changes, and system checks and circuit checks can be made. The initial evaluation can be made easily. Therefore, the development period of a semiconductor integrated circuit device LSI equipped with the mask ROM can be shortened.

Next, the semiconductor integrated circuit device L equipped with the EPROM is
Replace SI EPROM with mask ROM, mask R
Regarding the case of forming a semiconductor multiplication circuit device LSI equipped with an OM, the basic concept of the forming method will be explained using FIG. 4 (manufacturing process flow diagram).

As shown in FIG. 5, first, a step (501) of forming an element isolation region is a step for isolating each semiconductor element formed on a semiconductor substrate. This is a step of forming a thick field insulating film formed by selective oxidation. Also, in this step, a p-quel region and an nff1-quel region are formed. This process is common to each of the EPROM1 mask ROM.

Next, a step of forming a gate insulating film and a gate electrode (5)
02), this gate insulating film and gate electrode forming step is as follows:
This is a step of forming each of a gate insulating film and a gate electrode of a field effect transistor. This process is performed by E F ROM
In the case of the mask ROM, since the gate electrode has a two-layer gate electrode structure, the step is to form two layers of gate electrodes, and in the case of a mask ROM, the gate electrode has a single-layer gate electrode structure, so the step is to form a gate electrode in one layer. This step includes an impurity introduction step for adjusting the threshold voltage of the field effect transistor.

Next, a step of forming a diffusion layer (503), the diffusion layer forming step is a step of forming a source region and a drain region of a field effect transistor. is a step in which p-type impurities are respectively introduced. This diffusion layer forming step is common to both EPROM and mask ROM.

Next K, the step of forming an interlayer insulating film (504), the step of forming an insulating film between the eyebrows, is a step of forming an insulating film that electrically isolates the field effect transistor and the wiring in the upper layer. As an interlayer insulating film, CVD (Chemical Va
PSG (Phospho-8Ilica) is a silicon oxide film deposited by Pour Deposition method.
teQlass) membrane, BPS G (Boron-
Doped Phosph.

-8ilicate glass), or a composite film combining them. This step of forming an insulating film between eyebrows is a step common to both EPROM and mask ROM.

Next, a step of forming a wiring (505), the wiring forming step includes a step of forming a connection hole for connecting each semiconductor element and a step of forming a wiring of aluminum or the like. The process is common to both EPROM and mask ROM.

Next, an information writing step (506) is performed by introducing a predetermined impurity, such as boron (B), into the channel formation region of a predetermined MOSFET by ion implantation K.
This is a process of changing the threshold voltage. This information writing process is a process included only in the mask ROM.

Next, a step of forming the pad page 11y&[ (507
), the badge page marking film forming step is a step of forming a final badge page marking film covering the entire surface of the semiconductor element. The badge page carbon film is formed of, for example, a PSG film, a silicon nitride film, or the like. This pad page exposure film forming process is a common process for both EPROM and mask ROM. EPRO
The structure and specific manufacturing method of a semiconductor integrated circuit device LSI equipped with M will be described. Furthermore, using FIG. 7A (cross-sectional view of main parts) and FIGS. 7B to 7F (cross-sectional views of main parts shown for each manufacturing process), the structure and structure of a semiconductor integrated circuit device LSI in which EPROM is replaced with mask ROM and A specific manufacturing method will be explained.

As shown in FIG. 6A, the semiconductor integrated circuit device LSI is an EPROM in which a field effect transistor QM is memory celled.
It is equipped with. The field effect transistor QM is formed on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon, and includes a gate insulating film 4, a floating gate electrode 5 (first layer gate electrode), a gate insulating film 6, and a control gate electrode 8. (second layer gate electrode), a pair of n-type semiconductor regions 1O, which are a source region and a drain region, and a pair of n+-type semiconductor regions 14.Field-effect transistor Q
M has a two-layer gate electrode structure.

A low impurity concentration n-type semiconductor region 0 is provided between the high impurity concentration n-type semiconductor region 14 and the channel forming region. This n-type semiconductor region 10 is a so-called LDD
A field effect transistor having a (Lightly Doped Drain) structure is configured. n-type semiconductor region 10
is constructed in a self-aligned manner with respect to the gate electrode 8. The n-type semiconductor region 14 with a high impurity concentration is self-aligned with the gate electrode 8 with a sidewall spacer 13 interposed therebetween.

Field effect transistors (MISFET) Qnrt #Q formed on the main surface of the same semiconductor substrate 1
nrz eQ ptx # Q pT! Each of these constitutes a peripheral circuit. In this example, read-only
A circuit block serving as an indirect peripheral circuit other than the memory ROM is composed of field effect transistors Qntz*QpTI. This field effect transistor Qnr2+ Qp
tz has a one-layer gate electrode structure having a gate electrode 8 formed of the same conductive layer as the control gate electrode 8 of the field effect transistor QM.

In addition, the direct peripheral circuit of the read-only memory ROM is a field effect transistor QrlTx e Qnts.
eQpTt* Qprs. The field effect transistor Qnrx*QRITl has a one-layer gate electrode structure having a gate electrode 5 formed of the same conductive layer as the floating gate electrode 5 of the field effect transistor QM.

Note that the field effect transistor Ql) Tl r QpTI
P channel M formed in one Gln-type well region
ISFET 5, and the peripheral circuit mainly consists of CMO 8 as shown in FIG. 6A.

Also, the field effect transistor Q fiTl # Q f
iTl eQpTl, Qpt2haL D Dm construction”
C"411gsh"Cil.

Field effect transistor Qltiy QpTl has high breakdown voltage M
I5FETs (HMI S), field effect transistor Qntxs QRITI gate insulating film thickness t
. xl is the gate insulating film thickness t of the field effect transistor Qntzp Qpt. The film thickness is thicker than xl.

Note that high voltage MISFETs are not limited to LDD structures;
It may be configured with another structure that further increases the margin for breakdown voltage, such as a blue drain (DD) structure.

In FIG. 5A, field effect transistors QM, QnT
The x+ Qntgs are electrically isolated from each other by a field insulating film 2 and a p-type channel stopper region 3. Field effect transistor Q M t Q fiT t
A wiring 18 is connected to each semiconductor region 14 or 15 of *QnTz e Qprs *QpTs through a connection hole 17 formed in an interlayer insulating film 16 . Wiring 1
A passibasin film 19 is provided on top of the film 8 .

On the other hand, as shown in FIG. 7A, the semiconductor integrated circuit device LS
I is replaced with a mask ROM from an EPROM in a read-only memory ROM block, and has a field effect transistor QM which is a memory cell of the replaced mask ROM. The field effect transistor QM is formed on the main surface of the semiconductor substrate 1 and includes a gate insulating film 7, a gate electrode 8, a pair of n-type semiconductor regions 10 serving as a source region and a drain region, and a pair of cross-shaped semiconductor regions 14. has been done. Direct and indirect peripheral circuit field effect transistors (MISFET) Qrtts
y Qnt* QpTt* QpTs are field effect transistors Q which are memory cells of this mask ROM.
It has the same structure as M, that is, a one-layer gate electrode structure formed of the second layer of gate electrode 8.

In this way, in this embodiment, the high breakdown voltage MISFETs Qntt and Qptt in the EPROM are replaced with basically the same structure as the field effect transistor QHtz*Qptz in the EPROM.

Next, the semiconductor integrated circuit device LSI equipped with EPROM
A manufacturing method for the semiconductor integrated circuit device LSI equipped with a mask ROM and a corresponding manufacturing method for the semiconductor integrated circuit device LSI will be described with reference to FIG.

(1) Common element isolation region forming step As shown in FIG. 6B, a semiconductor integrated circuit device LSI equipped with an EPROM has one n-type well region in a predetermined region on the main surface of the p-type semiconductor substrate 1. form.

Next, a field insulating film 2 (silicon oxide film) is formed in a predetermined region on the main surface of the semiconductor substrate l by a known selective oxidation method, and a p-type channel stopper region 3 is formed in substantially the same manufacturing process. .

When replacing the EPROM and forming a semiconductor integrated circuit device LSI equipped with a mask ROM, as shown in FIG. 7A, the n-type well region IA,
A field insulating film 2 and a channel stopper region 3 are formed.

(2) Gate insulating film and gate electrode formation process First, EPR
In a semiconductor integrated circuit device LSI equipped with an OM, after removing the insulating film 4' in the element formation region, a clean gate insulating film 4 is removed.
form.

The gate insulating film 4 is formed by thermal oxidation, for example, to a thickness of about 300 to 500
It is formed of a silicon oxide film of about 0.00 (A). Thereafter, impurities for adjusting the threshold voltage are introduced into the main surface of the semiconductor substrate 1 by ion implantation or the like in the element formation region of the field effect transistor Q n T l #Q pT 1 .

Next, after depositing a polycrystalline silicon film on the entire surface of the substrate,
Perform predetermined patterning by anisotropic etching such as tive ion etching (RIE),
As shown in FIG. 6C, the floating gate electrode 5 of the field effect transistor QM and the field effect transistor Q
A gate electrode 5 of ntt + QpTl is formed.

This polycrystalline silicon film is formed by, for example, a CVD method, and in order to lower the resistance, n-type impurities such as phosphorus (CP) or arsenic (As) are introduced by ion implantation after deposition.

A semiconductor integrated circuit device LSI equipped with a mask ROM is
Substantially, the step of forming the first layer gate electrode 5 is omitted.

Next, the semiconductor integrated circuit device LSI equipped with EPROM
Forms the gate insulating film 6 of the field effect transistor QM using a silicon oxide film in which the surfaces of the floating gate electrode 5 and the gate electrode 50 are oxidized.

Next, the gate insulating film 6 in the region excluding the floating gate electrode 5 and the gate insulating film 6 on the gate electrode 5 is selectively removed.

Next, the entire surface of the substrate is oxidized to form the gate insulating film 7 of the field effect transistor Qntzs Qptz.

This gate insulating film 7 is formed of a silicon oxide film having a thickness of approximately 200 to 300 A by, for example, thermal oxidation or CVD.

That is, the field effect transistor Qntz * QpT
The gate insulating film thickness of l is the field effect transistor Qntlt.
The film thickness is thinner than the gate insulating film thickness of QpTl. When forming a semiconductor integrated circuit device LSI equipped with a mask ROM replacing the EPROM, a clean gate insulating film 7 is formed after removing the insulating film 4' in the element formation region.

Next, the semiconductor integrated circuit device LsI equipped with EPROM
After introducing a predetermined impurity to adjust the threshold voltage into the formation region of the field effect transistor QnτxeQpt, polycrystalline silicon is deposited over the entire surface of the substrate in substantially the same manner as in the process of forming the first layer gate electrode 5. By depositing a film and performing predetermined patterning, a gate electrode 8 is formed as shown in FIG. 6D. This gate electrode 8 is formed as the control gate electrode 8 of the field effect transistor QM and the gate electrode 8 of the field effect transistor QnTQpTl in the peripheral circuit.

Note that the gate electrode 8 is not limited to a polycrystalline silicon film, but may also be formed by a high melting point metal film or a high melting point silicide film (WSil) on a polycrystalline silicon film.
etc.) may be formed from a composite film (for example, a polycide film). Note that this is a high melting point metal film.

The high melting point silicide film can be formed by a CVD method or a sputtering method.

When replacing the EPROM and forming a semiconductor integrated circuit device LSI equipped with a mask ROM, as shown in FIG. 7C, a gate electrode 8 is similarly formed on the gate insulating film 7 corresponding to the step shown in FIG. 6D. Form. This gate electrode 8
is a field effect transistor Q) If Qntx* QH
t*, Qptt* QpTs are formed as gate electrodes 8, respectively.

(3) Common diffusion layer formation process First, semiconductor integrated circuit device LSI equipped with EPROM
mainly used field effect transistor QM using thermal oxidation method.
Gate insulating film 9 covering the 70-ting gate electrode 5 (
silicon oxide film) is formed.

This can prevent written electrons serving as information from escaping from the floating gate electrode 5 of the memory cell of the EPROM. Further, this gate insulating film 9 can improve the dielectric strength of the end portion of the gate electrode 5 or 8.

Note that the gate insulating film 9 is not limited to the thermal oxidation method, and may be formed by the CVD method. Next, as shown in FIG. 6E, a field effect transistor QM is formed.
In the formation region, an n-type semiconductor region IO is formed on the main surface of the semiconductor substrate 1. For example, the semiconductor region 10 is 10
” (atoms 60 to 100 As of about 7 cm
It can be formed by ion implantation with an energy of approximately (KeV).

Next, an n-type semiconductor region 11 is formed in the formation region of the field effect transistors Qnrx and Qnt2. The semiconductor region 11 has, for example, 10" [a toms/m"
) can be formed by introducing P of about 50 to 80 (key) by ion implantation with an energy of about 50 to 80 (key).

Next, in the formation region of the field effect transistor QpTte QpTs, a p-type semiconductor region 12 is formed on the main surface of the nW well region I A (n-). Semiconductor area 1
2 can be formed by introducing, for example, about 10 atoms/11 atoms of B by ion implantation with an energy of about 10 to 20 (KeV).

Note that the order in which the semiconductor regions 10, 11, and 12 are formed may be changed.

In this way, in the formation region of the field effect transistor QM, the n-type semiconductor region 11 is formed on the main surface of the semiconductor substrate 1.
An n-type semiconductor region 10 with a higher impurity concentration is formed. The semiconductor region 101 is configured to increase the electric field strength mainly in the vicinity of the drain region to increase the amount of hot carriers generated.

A semiconductor region 10 for configuring these LDD structures,
11 and 12 are formed in self-alignment with one of the gate electrodes 5 and 8, the floating gate electrode 5, and the control gate electrode 8.

Next, sidewall spacers 13 are formed on the sidewalls of each gate electrode 5, 8, floating gate electrode 5, and control gate electrode 8. The sidewall spacer 13 is made of, for example, a silicon oxide film K deposited by CvD.
It can be formed by performing anisotropic etching such as RIE.

Next, the field effect transistor Q M # Q nt t
In the formation region of s Q fi'l' z, an n+ type semiconductor region 14 is formed. For example, the semiconductor region 14 is 1
60 to 100 As of about 0" (atoms/3 yen)
It can be formed by ion implantation with an energy of approximately (KeV). The semiconductor region 14 is
Respective gate electrodes 5, 8, floating gate electrode 5
, are formed in self alignment with the control gate electrode 8.

Next, in the formation region of the field effect transistors Qprlt-Qprs, a p-type semiconductor region 5 is formed on the main surface of one n-type well region. The semiconductor region 15 contains, for example, 10 to 2 B of about 10"[atoms/m"].
It can be formed by ion implantation with an energy of about 0 (Kee).

When replacing the EPROM and forming a semiconductor integrated circuit device LSI equipped with a mask ROM, as shown in FIG. 7D, an n-type semiconductor region 11 and an n-medium semiconductor region are formed in the same manner as in the step shown in FIG. 6E. Form 14. These semiconductor regions 11°】4 are field effect transistors QM
Each semiconductor region 11 of tQnTt*Qprs
．． 14.

(4) Common interlayer insulating film forming step In the semiconductor integrated circuit device LSI equipped with the EPR6M, an interlayer insulating film 16 is formed.

When forming a semiconductor integrated circuit device LSI equipped with an i-screen ROM instead of an EPROM, an interlayer insulating film 16 is similarly formed corresponding to the above step.

(5) Common wiring forming step In the semiconductor integrated circuit device LSI equipped with an EPROM, after forming the connection hole 17 in the glabella insulating film 16, the interlayer insulating film 1
A wiring layer is formed on the entire surface of the wiring layer 6, and a predetermined patterning is performed thereon using anisotropic dry etching such as RIE to form wiring 18 as shown in FIG. 6F.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM replacing the EPROM, as shown in FIG. 7E, connection holes 17 and interconnections 18 are sequentially formed in the same manner as in the above steps.

(6) Information writing process The semiconductor integrated circuit device LSI equipped with a mask ROM is
After the wiring 17 is formed, as shown in FIG. 7F, a photoresist containing a predetermined impurity such as boron (B) as indicated by a chain line is applied to the channel formation region of a predetermined field effect transistor QM through the interlayer insulating film 16 and the gate electrode 8. The ions are introduced by ion implantation using the film as a mask, and the threshold voltage is changed. In other words, the field effect transistor QM (memory cell) into which impurities are not introduced is ON when the word line W is selected, and the field effect transistor QM (memory cell) into which impurities are introduced is ON when the word line W is selected and [also OFF].
is formed.

Note that this information writing step is not limited to this, and may be performed after the field effect transistor QM shown in FIG. 7D is completed. Basically, it is preferable for the information writing process to be performed closer to the final stage of the manufacturing process, since this can shorten the time required to complete the product.

In addition, the information writing process is performed using a field effect transistor QM.
Whether or not to form the field insulating film 2 in the element formation region, or to form wiring (data line) in the source region or drain region (semiconductor region 14° to 15) of the field effect transistor QM.
You may decide whether or not to connect 18.

Common Passivation Film Forming Step In the semiconductor integrated circuit device LSI equipped with an EPROM, a passivation film 19 is formed as shown in FIG. 6A.

When forming a semiconductor integrated circuit device LSI equipped with a mask ROM instead of an EPROM, a passivation film 19 is similarly formed corresponding to the above steps, as shown in FIG. 7A.

By applying these pair of manufacturing processes, EPROM
A semiconductor integrated circuit device LSI mounted with a mask ROM can be formed by using this manufacturing process and a semiconductor integrated circuit device LSI mounted with a mask ROM can be formed by only partially modifying the manufacturing process. In other words, EPROM
From semiconductor integrated circuit device LSI equipped with
Replacement with a semiconductor integrated circuit device LSI equipped with
This can be done with minimal design changes to both the circuit and the mask used in the manufacturing process.

In addition, as shown in Fig. 6A, K, high voltage MISFE T
Q n t le Q I) T 1 is limited to LDD structure. Even if it is configured with a DD structure or other high breakdown voltage structure, it can be easily replaced with an LDD structure in the same manner as described above.

In this way, a semiconductor integrated circuit device LSI having a microcomputer CPU equipped with a BFROM is formed,
EPROM installed in this semiconductor integrated circuit device LSI
The semiconductor integrated circuit device LSI
KEPROM is converted into a mask ROM without changing the peripheral circuits of the microcomputer, etc., and a semiconductor integrated circuit device LSI is formed in which the determined program is written in the mask ROM. The development period of a semiconductor integrated circuit device LSI equipped with the mask ROM can be shortened by an amount corresponding to the test period.

As a result, EPR was implemented in electronic equipment during initial evaluation.
To reduce the cost of electronic equipment by easily and quickly replacing a semiconductor integrated circuit device LSI equipped with an OM with a semiconductor integrated circuit device LSI equipped with a mask ROM, which is cheaper than the LSI after initial evaluation is completed. I can do it.

In addition, the EPRO installed in the semiconductor integrated circuit device LSI
M can be easily replaced with a horizontal mask ROM by simply omitting the step of forming the floating gate electrode 5 of the field effect transistor QM, which is a memory cell of the EPROM.

In addition, since this replacement basically has the same circuit configuration as the peripheral circuits required for each of the EPROM and mask ROM, changes at the time of replacement can be minimized, and initial evaluation such as system check and circuit check can be performed. can be easily done.

In addition, when replacing the unique peripheral circuits used only in EPROM with mask ROM, the circuit area remains as a logically inactive area, so mask ROM
It is possible to make fewer changes to the mask pattern used when manufacturing a semiconductor integrated circuit device LSI equipped with a mask ROM.In other words, it is possible to change the mask pattern used when manufacturing a semiconductor integrated circuit device LSI equipped with This can be done with minimal design changes to both the circuit and the mask used in the manufacturing process.

In addition, semiconductor integrated circuit device LSI equipped with EPROM
Semiconductor integrated circuit device LSI equipped with mask ROM from
Since the ultraviolet ray erasing window can be eliminated from the package, the package cost itself can be reduced. Furthermore, since the package can be replaced from a ceramic package to a resin package, the cost of the package can be further reduced.

(Example ■) In this Example ■, in the semiconductor integrated circuit device of Example I, the memory cell of an EPROM is formed with a single-layer gate electrode structure, and an EPROM composed of the memory cell with this single-layer gate electrode structure is This is a second embodiment of the present invention in which the ROM is replaced with a mask ROM.

A memory cell of an EPROM mounted on a semiconductor integrated circuit device LSI, which is Embodiment 2 of the present invention, is shown in FIG. 7A (a sectional view of a main part).

As shown in FIG. 7A, a memory cell of an EPROM mounted on a semiconductor integrated circuit device LSI has a floating gate electrode 8 formed of a second layer gate electrode and a control gate electrode 20 formed of an n medium-sized semiconductor region. It is composed of a field effect transistor QM having The source region and the drain region are arranged in the gate length direction of the floating gate electrode 8, respectively.

Next, a specific method for manufacturing the memory cell of this EPROM will be briefly explained using FIGS. 8B and 8C (cross-sectional views of main parts shown for each manufacturing process).

First, in the same manner as in Example I, a field insulating film 2, a p-type channel stopper region 3, and a gate insulating film 7 are sequentially formed on the main surface of a p-type semiconductor substrate l, and impurities for adjusting the threshold voltage are added. Introduce.

Next, as shown in FIG. 8B, NFI impurities are introduced into the crown portion of the semiconductor substrate 1 by ion implantation or the like to form the control gate electrode 18.

Next, a polycrystalline silicon film is deposited over the entire surface of the substrate and subjected to predetermined patterning to form a floating gate electrode 8 as shown in FIG. By the same manufacturing process as this step, the gate electrode 8 of the field effect transistor of the peripheral circuit is formed.

Next, as in Example I, semiconductor regions 14°15,
By sequentially forming the interlayer insulating film 16, connection hole 17, and wiring R18, a semiconductor integrated circuit device LSI equipped with an EPROM is completed.

EPROM installed in this semiconductor integrated circuit device LSI
To replace it with a mask ROM, use one of the methods described below.

(1) Floating gate electrode 8 and control gate electrode 20 are electrically connected. This connection is made, for example, by the wiring 13.

(2) The step of forming the control gate electrode 20 is deleted, and the thick field insulating film 2 is formed in the deleted region. The floating gate electrode 8 is connected to a wiring 18 used as a word line W.

Such a trap is installed in a semiconductor integrated circuit device LSI.
Replacing an EPROM having a memory cell with a layered gate electrode structure with a mask ROM is easier than replacing an EPROM with a memory cell having a two-layered gate electrode structure.

(Embodiment ■) This embodiment ■ is a non-volatile memory circuit, that is, an E E P ROM (Electrica
This is a third embodiment of the present invention using the lly-EP ROM.

FIG. 9 (equivalent circuit diagram) shows a memory cell of an EEPROM mounted on a semiconductor integrated circuit device LSI, which is Embodiment 2 of the present invention.

As shown in FIG. 9, a memory cell of an EEPROM mounted on a semiconductor integrated circuit device LSI has a floating gate electrode that stores charges, and an F that injects electrons into the floating gate electrode by a tunneling phenomenon.
LOT OX (Float ingGate T
field-effect transistors QMII to QMmn configured of a 2-channel oxide (unnel 0xide) type, and control field-effect transistors QTII to QT' connected in series thereto.
It is composed of mn. Control field effect transistors Q T 1 to QTmn are connected to data lines Dn and word lines WT1 to WTm, and are arranged in a matrix. Further, control gate electrodes of the field effect transistors QMII to QMmn are connected to word lines WM1 to WMm arranged in parallel to the word lines WT1 to WTm.

The information writing operation and information erasing operation of this EEPROM are well known and will not be specifically explained.

Next, the EEPR installed in the semiconductor integrated circuit device LSI
A method of replacing OM with mask ROM will be explained below. Note that the method for forming the peripheral circuit is substantially the same as in Example I, and therefore will not be described here.

(1) Field-effect transistor Q for controlling memory cells
In the case of replacing T with a mask ROM, the control field effect transistor QT of the memory cell can be directly replaced with a mask ROM memory cell without changing its basic structure. When replacing with a mask ROM, the FLOTOX field effect transistor QM of the memory cell and the word line W connected to it are
M is deleted. This field effect transistor QM portion is formed as a diffusion layer and acts as a mere resistor, so it does not affect the structure of the mask ROM.

(2) When replacing the FLOTOX type field effect transistor QM of the memory cell with a mask ROM The FLOTOX type field effect transistor QM of the memory cell can be replaced with a mask ROM in substantially the same manner as in Example I above. . When replacing with a mask ROM, the control field effect transistor QT of the memory cell and the word HA W T connected thereto are deleted. This field effect transistor QT portion is formed as a diffusion layer and acts simply as a resistor, so it does not affect the structure of the mask ROM.

In this way, the E
By replacing EPROM with mask ROM,
Substantially the same effects as in Example I can be achieved.

(Example ■) In this example ■, an EPROM is used as a logic function determining element.
This is a fourth embodiment of the present invention in which the used programmable logic array PLA is replaced with a mask ROM.

FIG. 10 (equivalent circuit diagram) shows the configuration of a programmable logic array PLA mounted on a semiconductor integrated circuit device LSI, which is Embodiment 2 of the present invention.

Since the method of writing information to the programmable logic array PLA mounted on the semiconductor integrated circuit device LSI shown in FIG. 10 is known, it will be briefly explained.

First, when writing information to the logic cell Q on the AND plane (1) the control transistor Ti between the AND plane and the OR plane is turned off and the potential ■1 is set as the write voltage.

(2) After applying a write voltage to the input terminal, the load transistor TQ+ is turned on to write information to the logic cell Qo.

Next, logic cell M1 on the OR plane. When writing information to (1) Control transistors T1~Tm, t□t~
t□t is turned off, and potentials ■ and V are set to write voltages.

(2) Turn on the load transistor TMI and the control transistor t1 to write information to the logic cell MIl. Regular programmable logic array PLA
When used as a control transistor T, ~Tm
% t, ~tm are OFF, to1~tOL are ON
Conditions (1)3 and (4) are set to predetermined potentials.

The method of replacing the EPROM used in this programmable logic array PLAK with a mask ROM is as follows.
Since it is substantially the same as the above-mentioned Example I, the description thereof will be omitted here.

In this way, programmable
A semiconductor integrated circuit device LSI equipped with a logic array PLA is a semiconductor integrated circuit device L equipped with a mask ROM.
By replacing it with SI, substantially the same effect as in Example I can be achieved.

Further, in each of the embodiments (1) to (2), the present invention provides a mask R mounted on a semiconductor integrated circuit device LSI.
OM can be replaced with EPROM or EEPROM.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, the EPROM is a vertical EPROM,
This may be replaced with a vertical mask ROM. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In a semiconductor integrated circuit device having a microcomputer equipped with a nonvolatile memory circuit, the development period for converting the nonvolatile memory circuit into another nonvolatile memory circuit can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit device having a microcomputer, which is Embodiment 2 of the present invention. FIG. 2 is a block diagram of the RO of the semiconductor integrated circuit device shown in FIG.
The block configuration diagram of M, the third figure, shows the EPRO formed in the ROM block.
The equivalent circuit diagram of M, FIG. 3B, shows the mask R formed in the ROM block.
The equivalent circuit diagram of the OM, FIG. 4A, shows the EPRO formed in the ROM block.
FIG. 4B is an equivalent circuit diagram of the X-level thick circuit of the mask ROM formed in the ROM block, and FIG. 5 is an equivalent circuit diagram of the X-level thick circuit of the mask ROM formed in the ROM block. FIG. 6A is a sectional view of a main part of the semiconductor integrated circuit device; FIGS. 6B to 6F are sectional views of main parts of the semiconductor integrated circuit device for each manufacturing process; FIG. 7A is a sectional view of a main part of the semiconductor integrated circuit device; 7B to 7F are sectional views of essential parts of the semiconductor integrated circuit device showing each manufacturing process, and FIG. 8A is a sectional view of an essential part of the semiconductor integrated circuit device. EPRO installed in a semiconductor integrated circuit device with a certain microcomputer
FIGS. 8B and 8C are cross-sectional views of main parts showing the structure of the memory cell M. FIGS. 8B and 8C are cross-sectional views of main parts showing the memory cell in each manufacturing process. FIG. EEPRO installed in a semiconductor integrated circuit device with a computer
Equivalent circuit diagram of M FIG. 1θ is an equivalent circuit diagram of a PLA mounted on a semiconductor integrated circuit device having a microcomputer, which is Embodiment 2 of the present invention. In the figure, LSI...semiconductor integrated circuit device, ROM...
Read-only memory, CPU...microcomputer, M-ARY...memory cell array, DEC
...Decoder circuit, SA...Sense amplifier, DOB
...Data out buffer, DIB...Data in buffer, PGC...Program circuit, C0
NT: Control circuit. r - Figure 4A Figure 48 Figure 5 Figure 8A Figure αH Figure 8B Figure 8C Figure 9 Figure 10 LJI Uz

Claims (1)

[Claims] 1. Information having basically the same circuit configuration as a first non-volatile memory circuit which has a memory cell, an information read circuit, and an information write circuit and is capable of electrically writing information and erasing the information. A semiconductor integrated circuit device having a microcomputer equipped with a read-only second nonvolatile memory circuit. 2. The second non-volatile memory circuit of the semiconductor integrated circuit device is configured such that a part of the memory cell array of the first non-volatile memory circuit is modified, the circuit configuration of the information read circuit remains basically unchanged, and the information write circuit is modified. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by making the semiconductor device logically inactive. 3. The semiconductor integrated circuit device according to claim 2, wherein the logically inactive state is a state in which a circuit formation area remains and no circuit pattern is formed. 4. The logically inactive state is a state in which a part of the input or output wiring of the write circuit of the first nonvolatile memory circuit is modified. semiconductor integrated circuit devices. 5. The memory cells of the first nonvolatile memory circuit are composed of field effect transistors having floating gate electrodes and control gate electrodes, and the memory cells of the second nonvolatile memory circuit are the same as the memory cells of the first nonvolatile memory circuit. 5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is constituted by a field effect transistor having a gate electrode formed in a step corresponding to a control gate electrode. 6. The first nonvolatile memory circuit is an ultraviolet erasable EPR.
OM, and the second nonvolatile memory circuit is a mask ROM.
Claims 1 to 5 are characterized in that:
2. The semiconductor integrated circuit device described in 2. 7. The first nonvolatile memory circuit is an electrically erasable EEP
ROM, and the second nonvolatile memory circuit is a mask RO.
5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is M. 8. The first non-volatile memory circuit is a programmable logic array formed of EPROM, and the second non-volatile memory circuit
6. The semiconductor integrated circuit device according to claim 1, wherein the nonvolatile memory circuit is a mask ROM. 9. The memory cells of the second non-volatile memory circuit are characterized in that information is written by controlling the threshold voltage of a field effect transistor. semiconductor integrated circuit devices. 10. Forming a first semiconductor integrated circuit device having a microcomputer equipped with a first non-volatile memory circuit capable of electrically writing information and erasing the information; determining a program or logic for controlling the microcomputer while writing and erasing information in the first nonvolatile memory circuit of the first semiconductor integrated circuit device; converting it into a second non-volatile memory circuit;
forming a second semiconductor integrated circuit device in which the determined program is written in the second non-volatile memory element, The non-volatile memory circuit is constructed by modifying a part of the memory cell array of the first non-volatile memory circuit of the first semiconductor integrated circuit device, leaving the circuit configuration of the information reading circuit basically as it is, and logically changing the information writing circuit. 1. A method for forming a semiconductor integrated circuit device, characterized in that the device is formed by bringing it into an inactive state. 11. The semiconductor integrated circuit according to claim 10, wherein the second nonvolatile memory circuit of the semiconductor integrated circuit device has basically the same circuit configuration as the first nonvolatile memory circuit. A method of forming a circuit device. 12. The logically inactive state is formed by leaving a circuit forming area and not forming a circuit pattern. A method for forming a semiconductor integrated circuit device according to section 1. 13. A patent characterized in that the logically inactive state is formed by modifying a part of the input or output wiring of the write circuit of the first nonvolatile memory circuit. A method for forming a semiconductor integrated circuit device according to claim 10 or 11. 14. The memory cells of the first nonvolatile memory circuit are composed of field effect transistors having floating gate electrodes and control gate electrodes, and the memory cells of the second nonvolatile memory circuit are the same as the memory cells of the first nonvolatile memory circuit. A method for forming a semiconductor integrated circuit device according to claims 10 to 13, characterized in that the semiconductor integrated circuit device is constituted by a field effect transistor having a gate electrode formed in a step corresponding to a control gate electrode. . 15. The first nonvolatile memory circuit is an ultraviolet erasable EP.
ROM, and the second nonvolatile memory circuit is a mask RO.
15. The method for forming a semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is M. 16. The first nonvolatile memory circuit is an electrically erasable EE
PROM, and the second nonvolatile memory circuit has a mask R.
14. The method for forming a semiconductor integrated circuit device according to claim 10, wherein the method is OM. 17. Claims 10 to 14, wherein the first non-volatile memory circuit is a programmable logic array formed of EPROM, and the second non-volatile memory circuit is a mask ROM. A method for forming a semiconductor integrated circuit device according to section 1. 18. Claims 15 to 15, wherein information is written in the memory cell of the second nonvolatile memory circuit of the semiconductor integrated circuit device by controlling the threshold voltage of a field effect transistor. 18. A method for forming a semiconductor integrated circuit device according to item 17.