KR100201180B1 - Semiconductor integrated circuit device - Google Patents

Abstract

A semiconductor integrated circuit device having a non-volatile memory device having a single-layer polysilicon gate structure, wherein a part thereof is superposed over a thin insulating film with respect to a control gate formed by a diffusion layer to enable defect repair and function setting change under high reliability. A barrier layer is provided to cover a part or the entire surface of the floating gate with respect to the nonvolatile memory device having a single-layer gate structure formed by providing a floating gate formed of the formed conductor layer, and the nonvolatile memory device is used for defect repair or function change. do.

By using such a semiconductor integrated circuit device, it is possible to prevent defects and to change a function setting under high reliability while preventing an increase in the manufacturing process.

Description

Semiconductor integrated circuit device

1A to 1D are sectional views of the manufacturing process of one embodiment for explaining the nonvolatile memory device according to the present invention.

2 is a cross-sectional view of a device structure showing another embodiment of a nonvolatile memory device according to the present invention.

3 is a cross-sectional view of a device structure, showing still another embodiment of the nonvolatile memory device in accordance with the present invention.

4 is a pattern diagram showing one embodiment of a nonvolatile memory device according to the present invention;

5 is a device pattern diagram showing another embodiment of the nonvolatile memory device according to the present invention.

6 is a block diagram showing one embodiment of a mask ROM to which the present invention is applied.

Fig. 7 is a circuit diagram showing one embodiment of the redundant word line selection circuit RAST in the mask ROM.

Fig. 8 is a circuit diagram showing one embodiment of the relief address selection circuit RAS in the mask ROM.

Fig. 9 is a circuit diagram showing one embodiment of the relief address memory circuit PRADD in the mask ROM.

Fig. 10 is a circuit diagram showing one embodiment of the write data input circuit PRPGC in the mask ROM.

Fig. 11 is a circuit diagram showing one embodiment of a redundant Y decoder circuit PR-YDC in the mask ROM.

Fig. 12 is a circuit diagram showing one embodiment of redundant memory mat PR-MAT, column switch gate PR-YGT, and sense amplifier circuit PR-SAM in the mask ROM.

Fig. 13 is a circuit diagram showing one embodiment of the multiplexer MPX in the mask ROM.

Fig. 14 is a circuit diagram showing another embodiment of the mask ROM to which the present invention is applied.

Fig. 15 is a circuit diagram showing another embodiment of the redundant memory mat and its peripheral circuit.

16 is a data retention characteristic diagram of a nonvolatile memory device for explaining the present invention.

FIG. 17A is a sectional view of an element structure showing another embodiment of the nonvolatile memory device according to the present invention. FIG.

17B is a plan view thereof.

18A is a cross-sectional view of a device structure, showing another embodiment of the nonvolatile memory device according to the present invention.

18B is a plan view thereof.

Fig. 19A is a sectional view of the device structure, showing another embodiment of the nonvolatile memory device in accordance with the present invention.

19B is a plan view thereof.

20A is a plan view showing another embodiment of the nonvolatile memory device in accordance with the present invention.

20B is a plan view showing another embodiment of the nonvolatile memory device in accordance with the present invention.

21A to 21D are sectional views of the production process for illustrating another embodiment of the nonvolatile memory device according to the present invention.

Fig. 21E is a plan view thereof.

22A to 22C are sectional views of the production process for explaining still another embodiment of the nonvolatile memory device according to the present invention.

23A and 23B are cross-sectional views of a device structure showing an embodiment of a semiconductor integrated circuit device in which a nonvolatile memory device having a one-layer gate structure is used to rescue a dynamic RAM, respectively.

FIG. 23C is a plan view corresponding to FIG. 23B. FIG.

Fig. 23D is a block diagram showing one embodiment of a dynamic RAM incorporating a defect repair circuit by a nonvolatile memory device according to the present invention.

FIG. 24 is a block diagram showing one embodiment when the nonvolatile memory device according to the present invention is used for relief of a microcomputer, and the like.

Fig. 25 is a sectional view showing the device structure according to one embodiment in the case where a non-volatile memory device having a one-layer gate structure according to the present invention is mounted in a conventional two-layer gate structure EPROM.

Fig. 26A is a sectional view of the device structure, showing an embodiment in which the nonvolatile memory device according to the present invention is used for trimming a semiconductor integrated circuit device including an analog circuit.

Fig. 26B is a circuit diagram showing one embodiment of the trimming circuit.

FIG. 27A is a circuit diagram showing one embodiment of a memory array having a vertical configuration using a nonvolatile memory device according to the present invention. FIG.

27B is a plan view showing one embodiment of the memory cell.

27C is a principle diagram showing one embodiment of the write method.

FIG. 28 is a circuit diagram showing one embodiment in which the nonvolatile memory device according to the present invention can be electrically erased.

29A and 29B are layout diagrams showing one embodiment of a semiconductor integrated circuit device (mask ROM) according to the present invention.

29C and 29D are layout views showing one embodiment of a semiconductor integrated circuit device (microcomputer) according to the present invention.

30A and 30B are circuit diagrams showing an embodiment of a pad used for writing to a nonvolatile memory device.

Fig. 31A is a flowchart showing one embodiment of a trimming method.

Fig. 31B is a flowchart showing another embodiment of the trimming method.

FIG. 32 is a flowchart showing one embodiment in a case where writing is performed after a light is packaged in a nonvolatile memory device according to the present invention. FIG.

33A shows a semiconductor integrated circuit device after being sealed with a package.

33B is a top view of the pin arrangement.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technique effective for use in a semiconductor integrated circuit device having a nonvolatile memory device having a single layer polysilicon gate structure.

Mask ROM (Read Only Memory), which is a read only memory in which data is written by a mask, is described, for example, in USP 4, 939, and 386.

This type of mask ROM can be formed using a polySi (silicon) one-layer process, and can store one bit with one transistor, which is suitable for high capacity and low cost. In addition, a defect remedy technique is employed in the mask ROM to improve efficiency due to miniaturization and high integration. For the defective bit relief of the mask ROM, for example, the International Solid-State Circuit Conference (ISSCC) Dig. Tech. Papers, Feb. 1989, P. 128-129, P. 311). In this document, a redundant technology using a polycrystalline Si fuse is disclosed.

The present inventors have not found a known technique. However, the present inventors have found the following problems in developing a technique for using a EPROM for defect repair of a semiconductor integrated circuit device having a memory array such as a mask ROM or for changing memory data.

A technique of using a two-layer gate structure EPROM (Erasable Programmable Read-Only Memory) for selecting a redundant circuit is disclosed in Japanese Patent Laid-Open No. 60-83349. Here, the two-layer gate structure is a structure in which a gate insulating film, a floating gate electrode formed of the first layer of poly Si film, an insulating film, and a control gate electrode formed of the second layer of polySi film are sequentially stacked on a semiconductor substrate. In the EPROM, it is necessary to apply a predetermined high voltage (˜12 V) to the control gate electrode when writing the information. Therefore, it is necessary to use a thin insulating film whose film quality and film pressure are controlled to satisfy desired write and read characteristics. Therefore, in the technique of using a two-layered EPROM for redundant circuits, for example, it is necessary to add a special manufacturing process for forming an insulating film having high reliability formed between the floating gate and the control gate. Great. For the EPROM of the two-layer gate structure, for example, USP 4,918,501 or IEDM (International Electron Device Meeting) Tec h. Dig., P. 631-634, 1985.

In addition, as for EPROM, a technique using a single-layer polysilicon gate structure is described, for example, in "Academic Research Report of the Institute of Electronics and Information Communication" of May 21, 1990. 90, No. 47, P. 51-53.

The inventor of the present invention analyzes the data retention characteristics in an EPROM (nonvolatile memory device) as described below, and carefully analyzes the relationship between the device structure and the data retention characteristics. The present invention relates to a nonvolatile memory device having a gate structure and a semiconductor integrated circuit device using the same.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a non-volatile memory device having a single-layer gate structure for improving data retention characteristics.

Another object of the present invention is to provide a semiconductor integrated circuit device which is simple in fabrication and is capable of defect repair, function change or trimming under high reliability.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed herein are as follows. That is, a barrier is formed so as to cover a portion or the entire surface on the floating gate with respect to the nonvolatile memory device of the single-layer gate structure formed by providing a floating gate made of a conductor layer formed so that a portion of the control gate formed by the diffusion layer is overlapped through a thin insulating film. Lay the floor. Such a nonvolatile memory device is used for defect repair or function change.

According to the above means, since radical hydrogen, which is supposed to diffuse in the final passivation film of the element surface portion, is captured by the barrier layer, it is possible to prevent destruction of the information charge accumulated in the floating gate. This makes it possible to correct a defect and to change a function of the semiconductor integrated circuit device under high reliability.

First, the relationship between the data retention characteristics of the device structure found by the inventors will be described.

The present inventors found out that the following phenomenon occurred as a result of analyzing the data retention characteristics in the EPROM.

16 shows data retention characteristics of EPROMs having different structures. In the same figure, the horizontal axis represents time, and the vertical axis represents the variation rate (ΔVth _t ÷ ΔVth ₀ × 100)% of the threshold voltage. Here, DELTA Vth ₀ represents the threshold voltage at the time of writing, and DELTA Vth _t represents the threshold voltage after elapse of t time. In addition, data retention characteristics in an environment which is left in the air at a temperature of 300 ° C are investigated.

In FIG. 16, the element structure of the characteristic B is EPROM of the single layer polysilicon gate structure, and the characteristic D is EPROM of the two layer gate structure. The present inventors speculate that the control gate in the two-layer gate structure acts as a barrier layer to prevent the reduction of information charge accumulated in the floating gate from the difference in data retention characteristics of both EPROMs. In order to confirm this, an EPROM having a single layer polysilicon gate structure having an aluminum layer formed on the upper surface of the floating gate made of the single layer polysilicon was formed, and the data retention characteristics were examined. Showed. In addition, when an oxide film (P-SiO) formed by plasma CVD (Chemcal Vapor Deposition) method is provided on the device in a two-layer gate structure, it has been found that good data retention characteristics such as property C can be obtained. The oxide film (P-SiO) is formed as an interlayer insulating film for two-layer aluminum wiring.

That is, the first aluminum layer is formed on a BPSG (Boron-doped Phospho-Silcate Glass) film, and a two-layer gate structure in which the second aluminum layer is formed through the oxide film (P-SiO) thereon. EPROM.

From the results of careful analysis of the relationship between the device structure and the data retention characteristics described above, the present invention relates to a non-volatile memory device having a single-layered gate structure and a semiconductor integrated circuit device using the same, which have improved data retention characteristics.

1A to 1D are shown together with an N-channel MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) and a P-channel MISFET in which a cross-sectional view of the manufacturing process for explaining the nonvolatile memory device according to the present invention is formed at the same time. In addition, in this specification, MISFET is used by the meaning of an insulation gate type field effect transistor (IGFET).

In Figs. 1A to 1D, nonvolatile memory elements QE, N-channel MISFET QN, and P-channel MISFET QP of the one-layer polysilicon gate structure are shown from the left side. The N-channel MISFET QN and P-channel MISFET QP are used to configure peripheral circuits such as the address selection circuit of the nonvolatile memory element QE or other memory circuits or digital circuits formed on the same semiconductor substrate as the EPROM of the present invention. The nonvolatile memory device QE has a cross sectional view of the source and drain in the vertical direction on the left side and in the parallel direction on the right side.

In FIG. 1A, the P type well 2 and the N type well 102 are formed on one main surface of the P type semiconductor substrate 1 by known means. Subsequently, a thick channel insulating film 3 and a P-channel sputter 4 shown by a dotted line in the same drawing are formed below.

In FIG. 1B, an N-type diffusion layer 6 to be a control gate of the nonvolatile memory device QE is formed. The N-type diffusion layer 6 is not particularly limited, but phosphorus is implanted at an acceleration energy of 80 Kev at about 1 × 10 ¹⁴ cm ^-2 through the insulating film 5 by ion implantation, and then contains about 1% oxygen in nitrogen. It is formed by performing heat treatment for about 30 minutes at a temperature of 950 ° C in the atmosphere. Of course, as the impurity, only arsenic or both arsenic and phosphorus may be used. In addition, although it is not necessary to perform heat processing basically, it is good to perform the said heat processing for the damage recovery of the semiconductor substrate 1 damaged by ion implantation.

Next, after the insulating film 5 damaged by the ion implantation is removed, a clean gate insulating film 7 is formed by, for example, a thermal oxidation method.

At this time, the film thickness of the gate insulating film 7 above the N-type diffusion layer 6 is formed to be about 1 to 2 thicker than the region without the N-type diffusion layer 6.

Then, a conductor layer 8 made of a floating gate of the nonvolatile memory element QE and a gate electrode of the N-channel MISFET QN and the P-channel MISFET QP is formed. The conductor layer 8 is composed of a polycrystalline film in which a silicide film is laminated on a polycrystalline silicon (polysilicon) film or a polycrystalline silicon film.

As shown in FIG. 1C, the N-type diffusion layers 9 and 10 and the P-type diffusion layer 109 are formed. For example, the N-type diffusion layer 9 is formed by implanting phosphorus with acceleration energy of 50KeV at about 2 x 10 ¹³ cm ^-2 by ion implantation method, and the N-type diffusion layer 10 is phosphorus acceleration energy by ion implantation method. 5 × 10 ¹⁵ cm ^{−2 at} 50 KeV. The P-type diffusion layer 109 is formed by, for example, injecting boron at an acceleration energy of 15 KeV by about 1 × 10 ¹³ cm ⁻² by ion implantation.

Next, after the CVD insulating film is formed on the entire surface, the sidewalls 11 are formed by anisotropic etching. Then, the N type diffusion layer 12 and the P type diffusion layer 112 are formed. The N type diffusion layer 12 is formed by implanting about 5 x 10 ¹⁵ cm ^-2 of arsenic with an acceleration energy of 80 KeV by ion implantation. The P-type diffusion layer 112 is formed by implanting boron about 2 × 10 ¹⁵ cm ⁻² with an acceleration energy of 15 KeV by ion implantation.

In this embodiment, the N-type diffusion layer 10 is formed to be formed before the sidewall 11 is formed, but may be formed after the sidewall 11 is formed.

In addition, the manufacturing process of the P type diffused layer 109 may be abbreviate | omitted, and the P type diffused layer 112 may be formed before formation of the sidewall 11. FIG. In this case, the N-type diffusion layer 9 can be formed by ion implantation onto the entire surface without using a mask.

In FIG. 1D, the nonvolatile memory device QE includes the control gate as the diffusion layers 6 and 10, the floating gate 8, the gate insulating film 7, the interlayer insulating film 7 between the control gate and the floating gate, the source and the like. The drain becomes a one-layer gate structure constituted by the N-type diffusion layer 10. The source and the drain are formed by the N-type diffusion layer 10 in order to improve the light characteristics. The N type diffusion layer 10 has the same configuration as the source and drain of the N channel MISFET QN constituting the input / output. The N-channel MISFET QN has a so-called LDD (Lightly Doped Drain) structure in which the gate electrode 8, the gate insulating film 7, and the source and drain are formed by the N-type diffusion layers 9 and 12. The P-channel MISFET QP has a so-called LDD structure in which the gate electrode 8, the gate insulating film 7, and the source and drain are formed by the P-type diffusion layers 109 and 112. Each element is dispersed by the field insulating film 3 and the P-type channel stopper 4. Each element is connected by a wiring 15 made of aluminum via a contact hole drilled through the insulating film 13. N-type diffusion layers 6 and 10, which are control gates of the nonvolatile memory device QE, are shunted by the wiring 15 to reduce parasitic capacitance. That is, the wiring 15 forms a word line and is connected to the control gates of the respective nonvolatile memory elements. The N type diffusion layer 10 is provided to improve the negative contact with the wiring 15.

In this embodiment, an aluminum layer 15 covering the entire surface of the floating gate 8 is formed as a barrier layer via the insulating film 13 in order to improve the data retention characteristics of the nonvolatile memory device QE having the one-layer gate structure. do.

The insulating film 13 is made of, for example, a Phospho-Silicate Glass (PSG) film or a BPSG film. Although not particularly limited, the aluminum layer 15 as a barrier layer formed to cover the entire surface of the floating gate via the insulating film 13 is integrally formed with a word line to which the control gate of the nonvolatile memory element QE is connected.

In addition, when the nonvolatile memory device QE of this embodiment is used for defect relief of a mask ROM as described later, the N-channel MISFET QN has a structure similar to that of the memory device. In FIG. 1A, however, the N-type impurity is introduced into the portion where the mask ROM is formed by ion implantation, and the N-channel MISFET formed thereon is provided as a depletion type.

4 shows a device pattern diagram of one embodiment of the nonvolatile memory device QE.

The N-type diffusion layer 6, which is a control gate, is connected to the word line WL made of the aluminum layer 15, which is indicated by a dotted line in the same drawing, through the contact hole 14. The aluminum layer 15 is formed to extend in the right direction along the floating gate 8 so as to cover the entire surface of the floating gate 8 hatched by dotted lines on the same drawing for use as a barrier layer of the floating gate 8. do. In the same drawing, two memory cells are shown symmetrically with respect to the dashed line a-b. That is, the drain of the upper nonvolatile memory device QE is connected to the aluminum layer 15 via the contact hole 14. The aluminum layer 15 is connected to a data line DL made of a polysilicon layer extending from side to side through the contact hole 14. In addition, the N-type diffusion layer 10 constituting the source of the nonvolatile memory device QE is integrally formed with the source of the nonvolatile memory device QE on the lower side, and the aluminum layer 15 or the drain constituting the barrier layer is made of polysilicon. Aluminum extending in the right direction along the centerline ab to the region not intersecting with the aluminum layer connected to the word line made of the silicon layer, and extending in the longitudinal direction, that is, parallel to the word line, through the contact hole 14 formed therein. It is connected to the source line SL which consists of layers.

The nonvolatile memory device QE of the single-layer gate structure of this embodiment is provided with a barrier layer made of an aluminum layer formed to cover the entire surface of the upper portion of the floating gate. In this embodiment, a barrier layer having a large size having a margin exceeding the size of the floating gate 8 in order to prevent injection into the floating gate by diffusion of radical hydrogen as described later.

The following is estimated from the data retention characteristics shown in FIG. The improvement of the data retention characteristic is shown in comparison with the characteristic B. Subsequent differences between them are that the feature D is a two-layer gate structure, while the feature B is a single-layer gate structure. The inventors inferred from this as that the control gate in the two-layer gate structure has a function of preventing a factor of invading the floating gate and dissipating the maintenance charge. In order to confirm this, the aluminum layer as shown in FIG. 1D or FIG. 4 was provided and the element was formed as a barrier layer on the floating gate in a single-layer gate structure. As shown by characteristic A, the data retention characteristic is markedly improved.

One of the factors causing the loss of the information charge accumulated in the floating gate is radical hydrogen in the final passivation film for the following reason. That is, although omitted in FIG. 16, it has been found that the data retention characteristics are poor when the plasma nitride (P-SiN) film is used as the final passivation film compared with the case where the CVD oxide (PSG) film is used. The difference between the two is a large difference in the amount of radical hydrogen. And it was concluded that the aluminum layer as the barrier layer itself contained a large amount of hydrogen and acted as a dam to prevent radical hydrogen, thereby preventing the diffusion of hydrogen into the floating gate.

The barrier layer may be a polysilicon layer. The polysilicon layer also has a property of easily containing hydrogen, and when it is used as a floating gate, it traps hydrogen diffused in the final passivation film and loses information charge. This is used inversely to prepare a polysilicon layer as a barrier layer on the floating gate. The polysilicon layer as this barrier layer first captures and fetches the radical hydrogen diffused from the final passivation film, and acts to prevent diffusion to the floating gate provided thereunder. As a result, as in the case of the aluminum layer, the polysilicon layer as the barrier layer serves as a so-called dam for radical hydrogen to prevent intrusion into the floating gate.

The above phenomena are inferred to the last, but as apparent from the data retention characteristics shown in FIG. 16, by providing the barrier layer as described above, a clear improvement of the data retention characteristics of the nonvolatile memory device having the single-layer gate structure is seen. .

In addition, when plasma nitride (P-SiN) is used as the final passivation layer, a plastic package that does not transmit inexpensive ultraviolet rays may be used. Therefore, by providing the barrier layer as in this embodiment, a semiconductor integrated circuit device using an inexpensive package can be obtained while improving data retention characteristics.

The nonvolatile memory device is sealed with a package such as plastic that does not transmit ultraviolet rays as shown in FIGS. 33A and 33B.

2 is a cross-sectional view of the device structure of another embodiment of a nonvolatile memory device according to the present invention.

This embodiment is suitable for the case where the semiconductor integrated circuit device provided with the nonvolatile memory device uses two layers of aluminum wiring. That is, instead of using the aluminum layer 15 of the first layer as the barrier layer as shown in FIG. 1d, the interlayer insulating film 17 formed on the aluminum layer 15 is formed on the entire surface of the floating gate made of the polysilicon layer 8. Form to cover. In this case, when the second layer aluminum layer 17 is used as a word line, the first layer aluminum layer 15 is used for the contact holes 14 provided in the interlayer insulating films 13 and 16. It is connected to the control gate which consists of the diffusion layers 6 and 10 of the volatile memory element QE.

Although not shown, when the aluminum layer 15 of the first layer is used as a word line, the second layer aluminum layer 17 formed as the barrier layer is electrically floating and is only floating gate 8. It is formed to cover the image.

In addition, when the above-mentioned 2nd aluminum layer is formed, the structure which uses the aluminum layer of the said 2nd layer as a word line, and uses the aluminum layer of the 1st layer as a data line, or 1st layer on the contrary May be used as the word line, and the second aluminum layer may be used as the data line. The two aluminum layers may be used as a common source line or a subword line described later.

Also shown in the same drawing are N-channel MISFETs and P-channel MISFETs. Since the N-channel MISFET and the P-channel MISFET are the same as those of the first diagram, the description thereof is omitted.

3 is a cross-sectional view of the device structure of another embodiment of a nonvolatile memory device according to the present invention.

In the characteristic diagram of FIG. 16, characteristic C is a non-volatile memory device having a two-layer gate structure, and is an interlayer insulating film provided between the aluminum layer of the first layer and the aluminum layer of the second layer in order to form two layers of aluminum wiring. An oxide film (P-SiO) formed by plasma CVD is disposed. In addition, the present inventors have found that the oxide film (P-SiO) itself is also radical, since even in the same two-layer gate structure, a significantly better data retention characteristic is obtained compared to the characteristic D of the nonvolatile memory device having no oxide film (P-SiO). It has been found to have a function of preventing the diffusion of hydrogen. That is, the oxide film (P-SiO) is a monosilane (SiH ₄ ) + nitrogen oxide (N ₂ O) as a raw material gas to be introduced and attached to the plasma reaction chamber, the radical amount of hydrogen itself is small, diffused radical It is presumed to have a function of absorbing one hydrogen.

Thus, in the embodiment of the same drawing, the interlayer insulating film 13 of the first layer is constituted by the PSG film or the BPSG film, and the interlayer insulating film 16 of the second layer is constituted by the oxide film (P-SiO). The plasma nitride film (P-SiN) is used as the passivation film 18.

The structure of such an interlayer insulating film is the same as that of the two-layer aluminum wiring shown in FIG. Therefore, on the interlayer insulating film (PSG or BPSG) 13, the aluminum layer 15 of the first layer constitutes a word line or the like, and although not shown, the aluminum layer of the second layer on the interlayer insulating film (P-SiO) 16 is not shown. It may be formed as this data line, common source line, or other wiring.

Further, in the embodiment of FIG. 2, when the oxide film (P-SiO) formed by the plasma CVD method is used as the interlayer insulating film 16, the barrier layer can be made double of the oxide film (P-SiO) and the aluminum layer. It can be inferred that a good data retention characteristic comparable to the characteristic C in FIG. 16 is obtained.

Hereinafter, the defect repair circuit of the mask ROM using the nonvolatile memory device having the single-layer gate structure as described above will be described.

6 shows a block diagram of one embodiment of a mask ROM to which the present invention is applied.

The memory mat MR-MAT is formed by arranging a mask ROM memory element in a matrix. The memory mat PR-MAT is constructed by arranging the above-described nonvolatile memory devices having a single-layer gate structure in a matrix shape and is used for the relief of the defect data.

In the memory mat MR-MAT, as in the known mask ROM, a memory element is disposed at each intersection of a word line and a data line, and the gate of the memory element is connected to a word line, a drain is connected to a data line, and a source is connected to a legal line of a circuit. .

The word line of this memory mat MR-MAT is selected by the X decoder circuit MR-XDC. The X decoder circuit MR-XDC decodes the complementary internal address signal formed by the address buff ADB that receives the X address signals A _{i + 1} -A _n to select one word line of the memory mat MR-MAT.

The data line of the memory mat MR-MAT is connected to the common data line by the column switch gate MR-YGT. The column switch gate MR-YGT is in the memory mat MR-MAT in accordance with the decode signal formed by the Y decoder circuit YDC for decoding the complementary internal address signal formed by the address buffer ADB receiving the Y address signals A _{0 to} A _i . In this example, one data line is connected to the common data line for each output mat.

The common data line is connected to the input terminal of the sense amplifier circuit MR-SAM. The sense amplifier circuit MR-SAM amplifies the memory information read in the memory device at the intersection of the selected word line and data line.

In the memory mat PR-MAT, a non-volatile memory device having a single-layer gate structure as described above is disposed at each intersection of a word line and a data line, and is used as a redundancy circuit for defect data in the memory mat MR-MAT. The control gate of the nonvolatile memory device is connected to the word line, the drain is connected to the data line, and the source is connected to the ground line of the circuit. The redundant word line selection circuit formed by the relief address memory circuit PR-ADD described later is supplied to the word line of the redundant memory mat PR-MAT.

The data line of the redundant memory mat PR-MAT is connected to the write data input circuit PR-PGT and the column switch gate PR-YGT. The write data input circuit PR-PGT uses the redundant memory mat by the complementary internal address signal formed by the address buffer ADB receiving Y address signals A _{0 to} A _i and the data signal formed by the input buffer DIB receiving the write data input DI. An operation of transferring a write signal to one data line in the PR-MAT is performed. The column switch gate PR-YGT is a redundant memory mat PR-MAT according to the output signal of the Y decoder PR-YDC which decodes the complementary internal address signal formed by the address buffer ADB receiving the Y address signals A _{0 to} A _i . One data line is connected to the common data line for each of the output mats. The common data line is connected to the input terminal of the sense amplifier circuit PR-SAM. The sense amplifier circuit PR-SAM amplifies the memory information read from the memory cell (nonvolatile memory device) at the intersection of the selected word line and data line in the read mode.

The output signal of the sense amplifier circuit PR-SAM is input to the multiplexer circuit MPX which performs the sense amplifier switching. The multiplexer circuit MPX selects either the output signal of the sense amplifier circuit PR-SAM for the mask ROM or the output signal of the sense amplifier circuit PR-SAM for the redundant memory mat PR-MAT and transfers it to the output buffer DOB. . The output buffer DOB sends the read data transmitted through the multiplexer MPX from the output terminals DO _{0 to} DO _m .

Although not particularly limited, in this embodiment, the nonvolatile memory device is used to store a rescue address. The storage method of the rescue address converts the address signal formed in the address buffer circuit ADB which receives the X-based address signals A _{i + 1 to} A _n into write data by the rescue address selection circuit RAS, and is arranged in the rescue address memory circuit PR-ADD. Stored in a nonvolatile memory device. Although not particularly limited, a plurality of rescued word lines can be stored in the rescue address memory circuit PR-ADD. These rescue word lines are allocated by redundant word line select circuit RAST for decoding the complementary address signal formed by address buffer circuit ADB which receives Y-based address signals A ₀ -A _i to convert relief address storage positions.

The relief address memory circuit PR-ADD forms the word line selection signals / RWS ₁ to RWS ₀ of the address written together with the storage of the relief address and executes the word line selection operation of the redundant memory mat PR-MAT. In addition, the output switching complementary signals RSDA and / RSDA of the multiplexer circuit MPX are formed.

The control circuit CONT receives the chip enable signal / CE for activating the present semiconductor integrated circuit device and the output enable signal / OE for output buffer control at read time, and receives the respective circuit block activation signal / ce and sense amplifier circuit MR-. High voltage terminal Vpp for writing of nonvolatile memory devices (PR-MAT, PR-ADD) arranged for redundancy at the same time forming SAM activation signal / sac and output buffer circuit DOB activation signal / doc, although not particularly limited The write enable signal / WE for executing the write control is received to form the internal write control signal / we, the relief signal storage write signal RS, RWNS and the like.

7 shows a circuit diagram of one embodiment of the redundant word line selection circuit RAST.

The address signal of the Y-A _{0 h} ~A complementary address signal address buffer circuit formed by the ADB receiving _{(h≤i) a 0, / a} 0 ~a h, / a h received the relief address storage circuit of the PR-ADD The allocation signals AST _{1 to} AST _i of the storage positions are formed by the signal RWNS that is activated at the time of writing to the memory element. For example, when the three-bit address signals A _{0 to} A ₂ are used, the allocation signals AST _{1 to} AST ₈ of _eight storage positions can be formed. As a result, a word line having up to eight relief bits of the memory mat MR-MAT can be replaced with a memory cell of the redundant memory mat PR-MAT. Therefore, when the above-described rescue address memory circuit PR-ADD is used, the nonvolatile memory elements corresponding to the eight word lines are arranged in a matrix in the redundant memory mat PR-MAT.

8 shows a circuit diagram of one embodiment of the rescue address selection circuit RAS.

The relief address selection circuit RAS receives each of the address signals ai + 1 to an formed by the address buffer circuit ADB that receives the X-based address signals A _{i + 1 to} A _n , respectively, and the nonvolatile memory device of the relief address memory circuit PR-ADD. The address signals a _{i + 1 to a n} inputted by the signal RWNS activated at the time of write to the row are transferred to the rescue address memory circuit PR-ADD as write data RAW _{ai + 1 to} RAWa _n . Address signal for executing a memory address and a relief-based address signal X _{i + 1} A comparison of ~A _n Ca _{i + 1} ~Ca _n are formed on the portion previously assigned to the relief address storage.

9 shows a circuit diagram of one embodiment of the rescue address memory circuit PR-ADD.

Memory address data RAWa _{i + 1 to} RAWa _n formed on the relief address selection circuit RAS while being transferred to the word line to which the nonvolatile memory elements of the above-described single-layer gate structure in which the relief address memory write signal RS is arranged as a memory element are combined. The data is written to the memory device by being transferred to this data line.

The data line to which the storage element storing the rescue address is connected is connected to the input terminal of the sense amplifier SA, and is amplified by the sense amplifier SA during the read operation. Although not particularly limited in this embodiment, as a storage device for storing the rescued address, a 1-bit storage device is provided in addition to the rescued address. By storing arbitrary data of " 1 " information or " 0 " information in the 1-bit memory element, it is confirmed whether or not the storage of the relief address is executed and the activation signal of the sense amplifier SA and the rescue address selection circuit RAS Activation signals / RS ₁ to / RS ₀ for forming the address comparison signals Ca _{i + 1 to} Ca _n are formed.

When the readout of the memory device storing the relief address is executed, each output signal of the sense amplifier SA is input to an exclusive logic circuit for checking the coincidence / unmatch with the address comparison signals Ca _{i + 1 to} Ca _n . The output of this exclusive logic circuit is " 0 " when the output of the sense amplifier SA and the address comparison signals Ca _{i + 1 to} Ca _n match, and " 1 " When all the data of the memory element for the rescue address storage match, any one of the redundant word line selection signals RWS _{1 to} RWS ₀ is activated as the selection signal. When any one of the redundant word line selection signals RWS _{1 to} RWS ₀ is selected, activation of the sense amplifier circuit PR-SAM provided in the redundant memory mat PR-MAT and switching signals RSAD and / RSAD supplied to the multiplexer MPX are performed. Is formed.

10 shows a circuit diagram of one embodiment of the write data input circuit PR-PGC.

Decoding the data data with the complementary internal address signals a ₀ , / a _{0 to a i} , / a _i formed by the address buffer circuit ADB receiving the Y-based address signals A _{0 to} A _i and for redundancy by the write signal we. The write data Dv _{0 to} D _vk are supplied to each data line of the memory mat PR-MAT.

11 shows a circuit diagram of one embodiment of the redundant Y decoder circuit PR-YDC.

The redundant Y decoder circuit PR-YDC decodes the complementary internal address signals a ₀ , / a _{0 to a i} , and / a _i formed by the address buffer circuit ADB receiving the Y-based address signals A _{0 to} A _i . The column select signals y _{0 to} y _k supplied to the column switch gate PR-YGT are formed.

12 shows a circuit diagram of one embodiment of a redundant memory mat PR-MAT, a column switch gate PR-YGT, and a sense amplifier circuit PR-SAM.

FIG. 13 shows a circuit diagram of one embodiment of the multiplexer MPX.

In this embodiment, a clocked inverter circuit having a tri-state output function is used. When the inverted switching signal RSDA is activated, the clocked inverter circuit which receives the read signal of the memory element selected by the memory mat PR-MAT constituting the mask ROM is activated and transfers it to the output buffer circuit DOB. When the non-inverting switching signal RSDA is activated, the clocked inverter circuit receiving the read signal of the memory element selected by the redundant memory mat PR-MAT is activated and transferred to the output buffer circuit DOB. That is, the correct data stored in the redundant memory mat PR-MAT is output instead of the read data including the defect bits present in the memory mat MR-MAT.

14 shows a circuit diagram of another embodiment of the mask ROM to which the present invention is applied. The mask ROM of this embodiment is composed of several series circuits of an N-channel type storage MISFET. Each of the storage MISFETs Qm is formed in a depletion type or an enhancement type in accordance with the storage information. As described above, writing of the storage information to the storage element is performed by the ion implantation method. In the same drawing, the depletion type MISFET is classified into an enhancement type MISFET by adding a straight line to the channel portion.

A series circuit corresponding to one data line D1, which is exemplarily shown as a representative, is composed of MISFETs T1 and T2 for column selection and storage MISFETs Q1 to Q3 for data storage and the like. Adjacent to this, a series circuit corresponding to another data line D2, which is exemplarily shown as a representative, is connected to MISFETs T3 and T4 for column selection and MISFETs Q4 to Q6 for data storage.

For example, the MISFETs T1 and T4 for column selection, which are illustrated by way of example, are configured by a depletion type MISFET, and T2 and T3 are each formed by an enhancement type MISFET, and other series MISFETs omitted in the same drawing are turned on. In the state, when the selection signal supplied to the gates of T1 and T3 by the column selector is at a low level and the selection signal supplied to the gates of T2 and T4 is at a high level, both T1 and T2 are turned on to the data line D1. Serial memories MISFET Q1 to Q3 and the like are connected. When the selection signal supplied to the gates of T1 and T3 by the column selector is at a high level and the selection signal supplied to the gates of T2 and T4 is at a low level, both T3 and T4 are turned on and in series with the data line D2. Memory MISFETs Q4 to Q6 are connected. Therefore, although not shown, it is possible to provide a plurality of series circuits in parallel with respect to each of the data lines D1, D2 and the like in the same drawing.

The gates of the storage MISFET Qm corresponding to the lateral direction among the storage MISFETs of each serial type of the memory array are commonly connected to word lines W1, W2, W3, and the like, which are exemplarily shown as representatives. These word lines W1 to W3 are connected to respective output terminals of the X decoder.

The data lines D1, D2 and the like are connected to the common data line CD via a Y decoder. The Y decoder in the same drawing also shows a column switch circuit composed of the Y decoder itself and a switch element controlled by the selection signal.

The common data line CD is connected to the input terminal of the sense amplifier SA. The sense amplifier SA sense-amplifies the high and low levels of the read signal of the selected memory cell with reference to the reference voltage formed by the reference voltage generation circuit VRF.

Although not particularly limited, the sense operation may be performed by referring to the reference voltages formed by the dummy arrays formed of the same memory circuit as the memory array unit as the reference voltage of the sense amplifier SA. The dummy array can be used in which the storage MISFET Qm is constituted by a mode-enhanced MISFET, and the gate is normally turned on by supplying a power supply voltage Vcc to the gate thereof.

The address selection operation of the vertical type ROM in this embodiment will be described next.

The X decoder decodes the internal address signal supplied from the row address buffer to form a decode output having the selection level low and the non-selection level high. For example, when the number of word lines is 512, one selected word line is set at low level, and the remaining 511 word lines are all set at high level. As a result, a current path is formed in the series circuit if the memory MISFET coupled to the selected word line is depleted, and no current path is formed in the enhanced type. The Y decoder YDCR decodes the internal address signal supplied through the address buffer, selects one data line out of 512, and connects it to the common data line CD. As a result, one read signal corresponding to one selected data line is amplified by the sense amplifier SA. When reading in units of several bits such as 8 bits or 16 bits as read data, 8 or 16 similar memory arrays are provided or 8 or 16 data lines are simultaneously selected by the Y decoder, respectively. In response, a sense amplifier and an output circuit may be provided. Such a nonvolatile memory device is used for the defect repair of such a vertical ROM. As the relief address memory circuit and redundant memory mat using this nonvolatile memory device, the circuit shown in Fig. 6 or the like can be used.

Fig. 15 shows a circuit diagram of another embodiment of the redundant memory mat and its peripheral circuit. Although the circuit symbols added to each element of the same drawing overlap with the element shown in FIG. 14, they are understood to be separate.

In the same drawing, one word line W1 and several memory elements Qm connected thereto are exemplarily shown. The selection circuit of the word line W1 is constituted by a proportional logic circuit. That is, the select signal formed by the NAND gate circuit G is supplied to the gate of the N-channel driving MISFET Q1. The source of this MISFET Q1 is connected to the ground potential of the circuit, and an N-channel MISFET Q2 receiving a selection signal by the CMOS (Complementary MOS) inverter circuit N is provided between the drain side and the power supply voltage Vcc. The drain output of the driving MISFET Q1 is connected to the word line W1 via the depletion type MISFET Q3 supplied with the write control signal WE to the gate. The word line W1 is provided with a depletion type load MISFET Q4. The power supply terminal to which the depletion type load MISFET Q4 is connected is supplied with a high voltage Vpp during a write operation and a low power supply voltage Vcc such as 5V during a read operation.

In this embodiment, in the write operation of the memory element Qm, in order to prevent the leakage current from flowing in the channel as the potential of the floating gate increases due to the write high level of the data line in the memory element provided in the unselected word line. The source of the storage MISFET Qm corresponding to the line is connected to the common source line S1, and the ground potential is applied to the source line via the switch MISFET Q7.

In this embodiment, since it is formed by a proportional logic circuit as described above, when the word line corresponding thereto is not selected, the level becomes higher than the ground potential according to the conductance ratios of the MISFET Q1, Q3 and the load MISFET Q4. It is not possible to reliably turn off the MISFET Q7. That is, during the write operation, the write control signal WE is at the low level. When the output signal of the gate circuit G is at the non-selected state at the high level, the MISFET Q1 is turned on, and the word line is turned low at the ground potential side of the circuit. However, the level is higher than the ground potential according to the conductance ratio of the load MISFET Q4 and the conductance ratio of the MISFETs Q3 and Q1. Therefore, the sub word line SW1 to which the output signal of the CMOS inverter circuit N1 is supplied is provided, and the selection signal corresponding to the word line W1 is supplied to the gate of the switch MISFET Q7. In this configuration, when the word line W1 is in the unselected state, the output signal of the CMOS inverter circuit N is at the same low level as the ground potential, so that the switch MISFET Q7 can be reliably turned off.

As a result, when the word line W1 is in an unselected state such as a low level, when the high level is supplied to the data lines D1 to D16 or the like, the write operation is performed to the memory element Qm coupled to another word line not shown. The leakage current can be prevented from flowing to the storage MISFET Qm provided in the unselected word line W1 in which is not executed. In this way, no current flows through the non-selected memory element Qm, thereby improving the breakdown voltage of the MISFET. This is because the MIS breakdown voltage when the channel current flows is due to the parasitic bipolar operation composed of the source, the substrate and the drain, and is lower than the MIS breakdown voltage due to the surface breakdown when the channel current does not flow.

In the case where the word driver for forming the word line selection signal is constituted by the CMOS circuit, the switch control of the switch MISFET Q7 may be executed by the word line W1. In this case, since the potential of the word line at the time of the write operation becomes high as with the high voltage Vpp, the switch MISFET Q7 needs to be increased withstand voltage.

In this embodiment, the write circuit WA having the latch circuit FF, like the data line D1, which is exemplarily shown as a representative example for shortening the write time, has all data lines D2 to D16. It is provided on the back. The memory element Qm is composed of a nonvolatile memory element having a single-layer gate structure as shown in Figs. 1D and 4D. Therefore, the size is larger than that of the nonvolatile memory device having the two-layer gate structure. Thus, the data circuits can be provided with the above write circuit WA in each data line without regenerating the pitch between the data lines relatively and regenerating the data line spacing of the memory mat.

As described above, in the configuration in which the write circuit WA is provided in each data line, the write operation consisting of two steps is executed. That is, the write operation of the first step is an operation of storing write data in the latch circuit FF. At this time, the data input through the data input circuit DIB selects a sequential data line passing through the column switch CW, and data transmission to the latch circuit FF provided therein is performed. In this manner, when the data transfer to all the data lines corresponding to one word line or the latch circuit FF corresponding to the predetermined several data lines ends, the write operation of the second step is started. In the write operation of the second step, the switch MISFET Q6 switches the word line to the write high voltage and supplies the write high voltage to the data line D1 according to the data fetched into the latch circuit FF of each write circuit WA. Control is performed and charge is injected into the floating gate of the memory element Qm.

In this case, since the write current flows simultaneously to the plurality of memory elements as described above, it is necessary to provide the above-mentioned leakage current prevention circuit in the sense of preventing the write current from expanding.

In addition, when a write operation is simultaneously performed on a plurality of memory elements Qm as described above, a relatively large current flows through the memory element Qm where charge injection is performed to the floating gate, so that a large current flows through the source line S1. It is necessary to prevent disconnection of the wiring. In order to prevent disconnection by such migration, the wiring width of the source line may be thickened. However, for high integration, it is not profitable to increase the wiring width. Thus, by providing a plurality of switches MISFET Q7 at regular intervals of the source line S1 and dispersing the write current, disconnection due to the migration can be prevented without forming the source line as thick as that.

The above write operation is not particularly limited, but is performed by a probing process when a circuit is completed on a semiconductor wafer. That is, in the probing process, a read test of the mask ROM is executed, and a bad bit is detected from the inspection result, and writing of the rescue address and writing of the stored data corresponding to the rescue address are executed. In the case of performing the defect repair, writing is executed in the profiling process in this manner, so that at the time when the mask ROM is completed, no special control terminal is required for writing the relief address or data corresponding thereto.

In addition, when the user is required to change or correct data, it is necessary to execute writing after the semiconductor integrated circuit device is completed. Therefore, a proper external terminal or a ternary input circuit including a high voltage input may be provided. One terminal may be multiplexed.

In addition, the write voltage applied to the data line is not changed from the power supply voltage Vcc to the high voltage Vpp, and the power supply voltage Vcc of about 5V is generally raised to about 7V to 8V within the allowable voltage range of the MISFET, as shown in the same drawing. (Vcc ') may be used. In this case, it is not necessary to increase the breakdown voltage of the light-based MISFETs Q6 and Q5, thereby simplifying the manufacturing process. In the case where the high voltage Vpp is used only as the selection level at the time of writing the word line, it is possible to prevent the DC current from flowing in the high voltage terminal Vpp, so that the high voltage Vpp can be formed by a relatively simple internal boost circuit.

In addition, when the write voltage applied to the data line at the time of writing is relatively low as about 7V to 8V as described above, the write time becomes relatively long. However, when the nonvolatile connectivity memory device having a one-layer gate structure is used for defect relief, function change, or the like as in this embodiment, the number of write data is relatively at least good, so even if the write time of a unit becomes longer, it is a big problem. Does not.

As described above, in the write operation of the nonvolatile memory device having the one-layer gate structure, the method of increasing the high voltage applied to the drain thereof, such as the power supply voltage Vcc, such as Vcc ', is performed by using the latch circuit FF as in the embodiment of FIG. In addition to using the circuit WA, it can be used for inputting data from an external terminal shared with another terminal such as a pad, an external terminal or an address terminal.

FIG. 5 shows a pattern diagram of one embodiment of the memory element having the above-described subword line.

In this embodiment, the subword line SW made of the same aluminum layer as the source line SL is disposed in parallel with the source line SL. In the configuration in which the subword line SW is arranged in this manner, the size of the memory cell is increased by that much, so that the source diffusion layer is formed small so as to prevent it, and the source line wiring is formed so as to extend therefrom.

17A to 20B show another embodiment of the present invention. In these embodiments, a portion of the floating gate is exposed in the barrier layer covering the upper portion of the floating gate. That is, the barrier layer does not cover the entire surface on the floating gate but has a structure that covers a portion thereof.

As described above, in order to improve the data retention characteristic, it is preferable to form a barrier layer to cover the entire surface on the floating gate. However, if the entire surface on the floating gate is covered, the size of the nonvolatile memory device is increased. For this reason, when a nonvolatile memory device having a large-capacity single-layer gate structure is required, such as the rescue of a mask ROM, it is disadvantageous from the viewpoint of integration degree. Therefore, since the size of the nonvolatile memory device is reduced, a portion of the floating gate is exposed in the barrier layer, that is, the barrier layer does not cover the entire surface of the floating gate, but can have the shape of a word line, a data line, or a source line. Some modifications intentionally in the range extend over the top of the floating gate. In this way, even if the floating gate is partially covered by the barrier layer, it is possible to reliably improve the data retention characteristic.

That is, it is assumed that the cause of damaging the data retention characteristics is that the radical hydrogen from the final passivation film reacts with the electrons accumulated in the floating gate, resulting in a decrease in the accumulated electrons. In this case, the rate at which the accumulated electrons decrease in unit time is considered to be proportional to the product of the electron density of the surface of the floating gate and the radical hydrogen density. Therefore, when the area ratio exposed by the floating gate in the barrier layer decreases, the reaction of radical hydrogen and electrons accumulated in the floating gate decreases, so that the rate of decrease of accumulated electrons also decreases. As a result, the data retention characteristic can be improved as described above.

17A shows a cross-sectional view of an element structure of another embodiment of a nonvolatile memory device according to the present invention, and FIG. 17B shows its plan view.

17A and 17B, the aluminum layer 15 constituting the word line WL is intentionally extended to the right side (source line side) in the same drawing to be used as a barrier layer of the floating gate 8.

FIG. 18A shows a cross-sectional view of the device structure of another embodiment of the nonvolatile memory device according to the present invention, and FIG. 18B shows its plan view.

18A and 18B, slits are provided in the aluminum layer 15 constituting the word line WL, so that a part of the floating gate 8 is exposed. This slit is not particularly limited, but has a rectangular shape so as to be parallel to the word line across the two floating gates. When the word line is extended to cover the entire surface on the floating gate to form the barrier layer as described above, the word line becomes thicker by that amount. When the word line becomes thick in this manner, cracks are formed in the aluminum layer 15 as the word line and the lower insulating film 13 of the aluminum layer 15 due to the stress of the final passivation film, which may damage the device characteristics. Thus, in this embodiment, slits are provided in the aluminum layer serving as the barrier layer, and the actual thickness is thinned to prevent the occurrence of such cracks.

17A to 18B, the aluminum layer 15 constituting the word line WL is extended to cover a part of the floating gate. Instead, the aluminum layer constituting the data line DL or the source line SL ( 15) may be extended to form a barrier layer covering part or the entire surface of the floating gate. As described above, slits may be provided to prevent cracking.

19A shows a cross-sectional view of the device structure of another embodiment of the nonvolatile memory device according to the present invention, and FIG. 19B shows its plan view.

19A and 19B, part of the floating gate 8 is covered by extending the aluminum layers 15 constituting the word line WL and the data line DL, respectively. In such a case, although the ratio of the individual aluminum layers constituting the word line WL and the data line DL covers the upper portion of the floating gate is small, the floating gate ( The ratio which covers the upper part of 8) can be made substantially large. When the barrier layer is formed in two ways as described above, the thickness of each aluminum layer can be made thin, so that the occurrence of cracks can be prevented without providing the slits as described above.

In the above embodiment, at the same time, the word line WL is constituted by the aluminum layer 15, and the data line DL is constituted by the conductor layer 8 such as polysilicon or polyside. This configuration is suitable for the case where the number of nonvolatile memory elements connected to the word line WL of the nonvolatile memory elements connected to the data line DL is smaller. That is, since the word line WL is made of the aluminum layer 15 having a small resistance value, the delay time of the word line WL at the time of reading can be reduced.

20A shows a plan view of another embodiment of a nonvolatile memory device according to the present invention.

In this embodiment, the word line WL is constituted by the conductor layer 8 made of polysilicon, polyside, or the like. This configuration is suitable for the case where the number of nonvolatile memory elements connected to the word line WL is smaller than the number of nonvolatile memory elements connected to the data line DL. The data line DL is composed of the aluminum layer 15 as indicated by the tangent lines in the same drawing. Therefore, the barrier layer is formed by forming the aluminum layer 15 constituting the data line DL so as to extend with respect to a part of the upper portion of the floating gate 8.

20B shows a plan view of another embodiment of the nonvolatile memory device according to the present invention.

In this embodiment, the word line WL is constituted by the conductor layer 8 made of polysilicon, polyside, or the like. This configuration is suitable for the case where the number of nonvolatile memory elements connected to the word line WL is smaller than the number of nonvolatile memory elements connected to the data line DL. The data line DL and the source line SL are composed of the aluminum layer 15 as indicated by the dotted lines in the same drawing. In this embodiment, the aluminum layer 15 constituting the source line SL is formed so as to extend with respect to a part of the upper part of the two floating gates 8 constituting the two nonvolatile memory elements formed therebetween. The barrier layer is constructed.

Similarly to the embodiments shown in FIGS. 19A and 19B, the aluminum layers 15 on both the data line DL and the source line SL may be extended so as to share part of the floating gate 8 respectively.

21A to 21D show a manufacturing process cross-sectional view for explaining another embodiment of the nonvolatile memory device according to the present invention together with an N-channel MISFET and a P-channel MISFET.

In this embodiment, unlike the nonvolatile memory device shown in Figs. 1A to 1D, the formation process of the N-type diffusion layer 6 is omitted. That is, the control gate of the nonvolatile memory device QE of this embodiment is composed of the N type well region 102 (n-) constituting the P-channel MISFET QP. In addition, the N-type diffusion layer 10 is formed so that the nonvolatile memory device QE extends below the floating gate, similarly to the nonvolatile memory device QE shown in FIGS. 1A to 1D. That is, the capacitive coupling between the floating gate and the control gate is determined by the capacitance between the N-type well region 102 and the floating gate and the capacitance between the N-type diffusion layer and the floating gate. Since the capacity coupling can be made larger than the capacity alone, the cell size can be made smaller.

FIG. 21E shows a plan view of the nonvolatile memory device corresponding to FIGS. 21A to 21D. In this case, when a deflation type N-channel MISFET is formed on the same semiconductor substrate, the implantation of an N type impurity used for deflation type has an effect of further increasing the capacitance between the N type well region 102 and the floating gate. have. Of course, the control gate may be formed only of the N-type well region 102. Alternatively, a diffusion layer extending below the floating gate, such as the N-type diffusion layer 10, without using the N-type well region 102 may be used as the control gate.

In the present embodiment, an N-type well region formed on a P-type semiconductor substrate is used as a control gate. However, when an N-type semiconductor substrate is used, it may be a nonvolatile memory device having a PMOS structure using the P-type well region as a control gate. Many variations are possible.

According to the present embodiment, a nonvolatile memory device having a control gate composed of a diffusion layer can be obtained without adding any manufacturing process, so that it can be applied to any semiconductor integrated circuit device.

In the nonvolatile memory device of this embodiment, the distance for separating the N type well region and other diffusion layers such as the N type diffusion layer 10 is increased, so that the cell size is the cell of the above embodiment such as FIG. 4 or FIG. It is bigger than size. However, as will be described later, in the case of only address conversion as in the case of RAM rescue, the number of nonvolatile memory elements required is small, so that even if the cell size becomes large, there is no problem.

22A to 22C form an N-channel MISFET and a P-channel MISFET and a mask ROM of a two-layer gate structure formed simultaneously with a cross-sectional view of a manufacturing process for explaining another embodiment of the nonvolatile memory device according to the present invention. Is shown with a memory MISFET QM.

In this embodiment, in order to form the degree of integration of the mask ROM, adjacent word lines are constituted by different conductor layers 8 and 108. That is, the word line of the odd-numbered MISFET is formed by the polysilicon layer 8 of the first layer among the plurality of storage MISFETs in series. By making such adjacent word lines have a two-layer gate structure, the actual word line spacing (the spacing of the MISFETs) is narrowed, so that the degree of integration can be improved. Also in this case, the nonvolatile memory element QE used for defect relief has a single-layer gate structure in which a control gate is formed of a diffusion layer.

Although the polysilicon layer has a two-layer structure as described above, it is for the following reason that the nonvolatile memory device has a single-layer gate structure. In the nonvolatile memory device of the two-layer gate structure, the gate insulating film provided between the first and second polysilicon layers is similarly different from that of the mask ROM of the two-layer gate structure. In other words, the two-layer gate structure of the mask ROM may be an insulating film only for the purpose of simply electrically separating the gates of the first and second layers, whereas in the nonvolatile memory device having the two-layer gate structure, It is necessary that the pressure be a thin insulating film that is controlled to meet the desired light and lead characteristics. Therefore, in the nonvolatile memory device having a two-layer gate structure, it is necessary to add a special manufacturing process for forming an insulating film to be formed between the floating gate and the control gate. Therefore, by using the nonvolatile memory device having the one-layer gate structure as described above, the bonding relief and the like can be executed without increasing the actual manufacturing process.

In FIG. 22A, a mask ROM including an N-type diffusion layer 6 serving as a control gate, a first gate insulating film 7, and a first gate electrode 8 is formed as in the embodiment shown in FIGS. 1A to 1D. To form the first MISFET. Insulation layers 201 and 211 are formed on the upper and side surfaces of the first gate electrode 8 to insulate the mask ROM from the second MISFET.

In FIG. 22B, a second MISFET of a mask ROM including the second gate insulating film 107 and the second gate electrode 108 is formed. In the present embodiment, the gate electrodes of the N-channel MISFET QN and the P-channel MISFET QP constituting the floating gate of the nonvolatile memory device QE and the peripheral circuit of the mask ROM are formed of the conductor layer 108 of the second layer. Of course, you may comprise these gate electrodes by the conductor layer 8 of a 1st layer.

As shown in FIG. 22C, each of these circuit elements is completed in the same manner as in the above embodiment. However, in the same drawing, the passivation film is omitted.

In this embodiment, as described above, even if the original semiconductor integrated circuit device has a two-layer gate structure, the manufacturing process is simplified by using the nonvolatile memory device as the one-layer gate structure.

23A and 23B show a sectional view of the device structure of one embodiment of a semiconductor integrated circuit device when a nonvolatile memory device having a one-layer gate structure is used for the rescue of a dynamic RAM.

In the dynamic memory cell of FIG. 23A, an information storage capacitor has a so-called STC structure composed of a conductor layer 203, a dielectric film 204, and a conductor layer 205. In FIG. In the dynamic memory cell shown in Fig. 23B, the information storage capacitor has a so-called planar structure in which an N-type diffusion layer 6, a dielectric film 204, and a conductor layer 205 are formed. In the same drawing, the passivation layer is omitted.

In any of the embodiments of FIGS. 23A and 23B, as in the embodiments shown in FIGS. 21A to 21E, the nonvolatile memory device having the one-layer gate structure is controlled by the N-type well region 102. There is no addition of a manufacturing process since it is constituted. Since the defect relief in the dynamic RAM only performs the address conversion, the number of nonvolatile memory elements required is at least good, so there is no practical problem even if the cell size becomes large.

In addition, when the wiring layers 15 and 17 which consist of two layers are provided, as shown in the sectional drawing of FIG. 23B, and the top view shown in FIG. 23C, the front surface of the floating gate of a nonvolatile memory element has two layers. It is covered by the combination of the wiring layers 15 and 17 which consist of these. That is, in this embodiment, the word line WL is composed of the aluminum layer 15 of the first layer, and the data line DL is composed of the aluminum layer 17 of the second layer. Therefore, the two aluminum layers 15 and 17 overlap each other and cover the floating gate provided thereunder.

FIG. 23D shows a block diagram of one embodiment of a dynamic RAM incorporating a defect repair circuit by a nonvolatile memory device according to the present invention.

The memory section of the dynamic RAM includes a memory mat DR-MAT, a Y gate circuit DR-YGT, and a sense amplifier circuit DR-SAM. The memory mat DR-MAT is constructed by arranging memory cells formed of an information storage capacitor as shown in FIG. 23A or 23B and a transfer MISFET for address selection in a matrix form. In the case of the dynamic RAM, there is no need for a nonvolatile memory device for storing data later, such as a mask ROM, and a spare memory mat dr which is arranged in a matrix form consisting of the same memory cells as the memory mat DR-MAT. -MAT, Y gate circuit dr-MAT, sense amplifier circuit dr-SAM. In the dynamic RAM, the substrate bias generation circuit VBBG is incorporated. That is, as described above, the spare memory mat dr-MAT uses the same volatile memory cell as the memory mat DR-MAT, there is no circuit for writing to the spare memory mat dr-MAT, and the substrate bias generation circuit VBBG is mounted. Except for this, the dynamic RAM can be repaired in the same manner as in the case of address translation of the mask ROM.

Although not particularly limited, the substrate bias generation circuit VBBG becomes inactive when writing to the nonvolatile memory device, and the semiconductor substrate is set to the ground potential of the circuit. This is to prevent the voltage of the PN junction from becoming too high because the voltage of the PN junction applies an excessively high voltage because the control gate made of the diffusion layer formed on the semiconductor substrate applies a high voltage when writing to the nonvolatile memory element. . In other words, this enables writing to a non-volatile memory device having a one-layer gate structure using the diffusion layer as a control gate, without applying a special high breakdown voltage to the PN junction.

Of course, the defect relief of the static RAM can be realized by the same method as the defect relief of the dynamic RAM as in the present embodiment.

FIG. 24 shows a block diagram of an embodiment in the case where a nonvolatile memory device having a one-layer gate structure according to the present invention is used for relief of a microcomputer, and the like.

The microcomputer of this embodiment is composed of a CPU (microprocessor), ROM, RAM, and I / O (input / output) ports configured on the same semiconductor substrate, and each circuit block is connected to each other by a BUS (bus). The CPUs are indicated by diagonal lines for μROM, ROM, RAM, and I / O ports. These rescue circuits have a configuration similar to the circuits shown in Figs. 6 to 15, and in the ROM and the ROM, data storage is performed along with address conversion using nonvolatile memory elements, and in the RAM, nonvolatile memory elements. Address conversion is performed using. Since these remedies are the same as in the above embodiment, description thereof is omitted. In addition, for example, the I / O port changes input / output at the TTL level and input / output at the CMOS level. As in the present embodiment, the nonvolatile memory device of the one-layer gate structure in which the control gate is formed of a diffusion layer can easily execute logic change such as relief of each logic block mounted on the microprocessor or I / O port.

It is also possible to provide a spare BUS and convert the address of each logical block connected to the defective BUS.

FIG. 25 is a cross-sectional view showing the device structure of one embodiment in the case where a nonvolatile memory device having a one-layer gate structure according to the present invention is mounted in a conventional two-layer gate structure EPROM.

The control gate of the nonvolatile memory device QE of the one-layer gate structure according to the present invention is constituted by the N-type well region 102 without the need for additional manufacturing process as described above. The N-channel MISFET QHN and the P-channel MISFET QHP are high voltage resistance MISFETs used to write a nonvolatile memory device (EPROM) QEP having a two-layer gate structure, and are used as the first gate insulating film 7 and the first gate electrode 8. Consists of. The N-channel MISFET QN and the P-channel MISFET QP are MISFETs used at normal operating voltages, and are composed of a second gate insulating film 107 and a second gate electrode 108. The nonvolatile memory device QEP of the two-layer gate structure is composed of a floating gate composed of the first gate electrode 8 and a control gate composed of a second gate electrode 108 provided through the insulating film 207 thereon.

In the case of only the rescue of the EPROM having the two-layer gate structure as described above, it is simple to use the EPROM having the two-layer gate structure as the nonvolatile memory device for relief. However, in the case of the microcomputer shown in FIG. 24, an EPROM that can easily change data is used as a data ROM in the early stages of product development, but an inexpensive mask ROM is used even if the function is the same after the temporary data is determined. . At this time, if the relief is performed by the EPROM of the two-layer gate structure, the EPROM of the two-layer gate structure must be changed to the nonvolatile memory device of the one-layer gate structure, and the debug circuit of the relief circuit or the chip configuration (layout) can be greatly reduced. Changes occur. Therefore, in this case, as in the present embodiment, the portion of the relief circuit is composed of a circuit including a nonvolatile memory device having a one-layer gate structure from the beginning. As a result, for example, a microcomputer in which the data ROM is changed from the EPROM having the two-layer gate structure to the mask ROM can be easily obtained. Alternatively, it is convenient when the number of nonvolatile memory elements mounted in the microcomputer is at least good. Techniques for forming a microcomputer in which the EPROM is changed to a mask ROM are described, for example, in US Patent Application No. 362,249 filed in the United States on June 6, 1989. Reference is made to the content of this document.

FIG. 26A is a sectional view showing the device structure of one embodiment when the nonvolatile memory device according to the present invention is used for trimming a semiconductor integrated circuit device including an analog circuit. FIG. 26B is a circuit diagram of one embodiment of a trimming circuit. Is shown.

A semiconductor integrated circuit device including an analog circuit is composed of an N-channel MISFET QN, a P-channel MISFET QP, a capacitor element QC, and a resistor element QR as shown in FIG. 26A, which constitute an operational amplifier circuit AM of a digital unit or an analog unit.

The trimming circuit shown in Fig. 26B performs trimming of the reference voltage used by the analog circuit, and sets the internally generated voltage Vin to the desired voltage Vout by 3-bit data. A series resistor circuit R0 is provided between the voltage Vout and the ground potential, and each of the mutual terminals is connected to one terminal of the operational amplifier AMP via the decoder DEC. The decoder DEC is operated on the data generated by the trimming circuits TRC1 to TRC3 to change the resistance ratio to perform trimming.

First, the PC terminal is set to the ground potential, and predetermined data is input to the PD terminal to determine the trimming data. Next, the Vcc terminal is set to the ground potential, the write voltage Vpp is applied to the PC terminal, and the data determined before is input to the PD terminal to write the nonvolatile memory device QE.

In this embodiment, the data is directly input from the PD terminal via the resistor R, but may be the same as in the above embodiment. Alternatively, only one terminal for data input may be provided, and the write may be performed by changing serial data into parallel data by means of a shift register.

Moreover, in the semiconductor integrated circuit device including an analog circuit, it is often operated by a battery of about 1V. The threshold voltage before the write of the nonvolatile memory device QE is usually about 1 V, and thus the determination before and after the write is impossible. In such a case, (1) the gate voltage of the nonvolatile memory device QE is boosted to a voltage that can be determined before and after writing, for example, about 3 to 5V. (2) The state before writing is set to the depletion mode, and the writing mode is set after the writing. Then, the gate voltage is read at the ground potential. (3) By the method described below, the state before writing is set to the enhancement mode, and the writing mode is set to the depletion mode after writing. Then, the gate voltage is read at the ground potential.

FIG. 27A shows a circuit diagram of one embodiment of a memory array having a vertical (NAND) configuration using a nonvolatile memory device according to the present invention. FIG. 27B shows a partial plan view thereof, and FIG. 27C shows a write method. The principle diagram is shown.

In FIG. 27A, in the NAND-configured memory array, nonvolatile memory devices are connected in series, MISFETs forming column switches are provided on the data lines (or bit lines) D0 and D1, and the other end and the ground potential of the circuit are provided. Between the points there is a switch MISFET. This configuration is basically the same configuration as the vertical mask ROM except that the memory MISFET is a nonvolatile memory element and a switch MISFET is provided.

In FIG. 27B, a floating gate in which the word line WL made of the aluminum layer extending in the longitudinal direction is in common contact with a diffusion layer constituting a control gate corresponding to two adjacent data lines DL, and is overlapped with the diffusion layer. Is extended so as to cross over the data lines DL constituting the source and drain extending in the lateral direction, thereby forming a nonvolatile memory device having a one-layer gate structure connected in series. By employing such a layout, the occupied area can be reduced to about 42% as compared to the conventional NOR memory array.

In Fig. 27C, writing is performed sequentially from the source side of the nonvolatile memory devices in series. At this time, the control signal SW is set at the same low level as the ground potential and the switch MISFET is turned off so that a DC current does not flow in the series circuit during writing. In the initial state, the threshold voltage of the nonvolatile memory device has a positive voltage (enhanced mode).

In this state, writing is performed in the nonvolatile memory device connected to the word line W7, and the word line W7 is at the same low level as the ground potential, and the other word lines W6 to W1 and the control signals Y0 and Y1 of the column switch have a relatively high voltage. Becomes When the write data D0 is at the low level, no electric field is applied between the control gate and the drain, so that no tunnel current flows from the floating gate toward the drain, thereby maintaining the threshold voltage Vth 0. On the other hand, when the write data D0 is at a high level with a relatively high voltage, a high electric field is applied between the control gate and the drain, and the tunnel current flows from the floating gate toward the drain, and is converted to the threshold voltage Vth 0.

In the same manner, writing is performed with the selected word line at the low level in the order of W6 to W0. Since only the tunnel current flows in such a light angle, the light current is reduced, so that the current crack or the like as in the case of the NOR type configuration is unnecessary, thereby simplifying the circuit configuration.

At the time of read, the control signal SW is set high and the switch MISFET is turned on. In this state, since the depletion type is the enhancement type in accordance with the storage information as described above, the conventional memory cell is read in the same manner as the conventional vertical ROM.

FIG. 28 shows a circuit diagram of one embodiment in the case where the nonvolatile memory device according to the present invention is also electrically erasable.

In this embodiment, data is written using a thermal carrier as in the conventional EPROM, and data is erased using a tunnel current as shown in Fig. 27C. In other words, writing of data is performed in the same manner as shown in FIG. In the case of erasing data, the word line of the nonvolatile memory device to be erased is set at the low level. As a result, the P-channel MISFET Q2 is turned on to supply the high level (Vpp) to the source line, and as shown in FIG. 27, a high electric field is applied between the control gate and the source, thereby floating the gate and the source. The tunnel current flows in between. The MISFET Q3 is turned off at the time of writing and on at the time of erasing by the control signal RW. The MISFET Q1 is turned on in accordance with the selection of the word line.

Since the source of the nonvolatile memory device connected to the unselected word line at the time of reading is open by the OFF state of the MISFET Q1, no leakage current flows in the memory device even when the nonvolatile memory device is erased and depleted. Therefore, no problem occurs at the time of lead.

29A and 29B show a layout diagram of one embodiment of a semiconductor integrated circuit device according to the present invention. The embodiment of the same drawing is suitable for a case where a relief circuit using a nonvolatile memory device according to the present invention is mounted in a mask ROM.

In FIG. 29A, a pad is provided at the center of the chip, and a relief circuit is provided as indicated by the diagonal lines between the pad and the memory mat MAT.

In Fig. 29B, a relief circuit is provided as indicated by diagonal lines between pads arranged in two rows in a jig-zag shape provided in the center portion of the chip.

In the above configuration, 1) the central portion of the chip has a small stress when the package is encapsulated, so that the characteristics of the nonvolatile memory element can be small and the reliability can be improved. 2) When the mask ROM becomes large in capacity, the power supply line, ground line, or signal line becomes long. As a result, malfunctions due to signal delay or noise become a problem. As a countermeasure, it is necessary to arrange the pad in the center of the chip. In this case, the position where the relief circuit is arranged is preferably around the pad where the space is most easily obtained. In this way, an increase in chip size can be prevented.

29C and 29D show a layout of another embodiment of the semiconductor integrated circuit device according to the present invention. The embodiment of the same drawing is suitable for the case where a microcomputer is equipped with a relief circuit using the nonvolatile memory device according to the present invention.

In Fig. 29C, the relief circuits indicated by the oblique lines are collectively located at one location of the chip. In this configuration, the data line can be easily input from the outside to the relief circuit.

In Fig. 29d, the relief circuit is distributed to each of the functional blocks to be saved, for example, in a micro ROM, a ROM, a RAM, or an ADC (analog / digital conversion circuit). In this configuration, since the relief circuit is provided in close proximity to the circuit corresponding thereto, the delay time at the time of rescue can be shortened.

30A and 30B show a circuit diagram of one embodiment of a pad used for writing to a nonvolatile memory device. In FIG. 30A, a P-channel MISFET having a high resistance value for pulling up the pad to the power supply voltage Vcc is provided. In FIG. 30B, an N-channel MISFET having a high resistance value for pulling down the pad to the ground potential of the circuit is provided.

In this way, a pull-up or pull-down resistor is provided for pads used for writing to a nonvolatile memory device having a two-layer gate structure at the time of relief or function change, and these pads are not directly connected to external terminals.

Such a configuration can prevent an increase in the number of external terminals. Further, in the semiconductor integrated circuit device in which the above-described defect repair or function change has been performed, the pad used for it is pulled up or pulled down to a fixed level, thereby preventing malfunction due to the pad having an undesirable potential. As the pull-up or pull-down resistor, polysilicon or the like may be used instead of the high-resistance MISFET.

FIG. 31A is a flowchart for explaining an embodiment of a trimming method.

In this embodiment, the trimming data is determined after sealing in a package by an external terminal or a terminal shared with other terminals.

FIG. 31B is a flowchart for explaining another embodiment of the trimming method.

In this embodiment, trimming is performed by determining the upper bits in the probing process when the chip is completed on the semiconductor wafer, that is, when the chip is completed on the semiconductor wafer, and the chip is encapsulated in the package. After that, the remaining low bit is determined to perform a minute trimming. By employing such a trimming method, it is possible to precisely trim a small amount of device characteristic caused by heat treatment or the like when the chip is sealed in a package.

FIG. 32 shows a flow chart of one embodiment in the case where writing is performed after encapsulating a light in a nonvolatile memory device according to the present invention.

In the chip forming step, as described above, the desired semiconductor integrated film is formed on the semiconductor wafer.

In the test process, a test of a semiconductor integrated circuit including a nonvolatile memory device is performed. The test of the nonvolatile memory device performs both a state before writing data and a state after writing data. In the erase process, the nonvolatile memory device is returned to its initial state. That is, it is set as the state before writing data. In the erase process, the nonvolatile memory device is returned to its initial state. In other words, it is set as before the data is written. Erasing is performed by irradiating ultraviolet rays when the nonvolatile memory element is an EPROM. In the nonvolatile memory device of the one-layer gate structure of this embodiment, a barrier layer made of aluminum or the like is provided on the floating gate. The aluminum layer itself does not transmit ultraviolet rays, but can be erased by diffraction or diffuse reflection of ultraviolet rays. In particular, in the case where only a part of the barrier layer is provided on the floating gate or when the slit is provided as in the above-described embodiment, the erase can be performed efficiently. Even when the front surface of the floating gate is covered with aluminum to prevent radical hydrogen from the final passivation film from reaching the floating gate, the distance of the barrier layer extending from the floating gate is short. It can be sufficiently erased by.

In the case of using the address conversion using the two-layer gate structure EPROM similarly to the defect in the EPROM having the two-layer gate structure as in the prior art, the erasing operation of the memory array unit prevents the erase from the address conversion unit. In order to cover the entire surface of the address conversion section, an aluminum layer is performed. In this case, a shielding film of aluminum is formed to a large size in consideration of diffraction and diffuse reflection of ultraviolet light for erasing the memory array unit. Therefore, even in the same aluminum layer, in the nonvolatile memory device of the one-layer gate structure according to the present invention, the aluminum layer serves as a barrier layer for preventing radical hydrogen from entering the floating gate in the final passivation film. It is essentially different.

In the encapsulation process, the test results and the good ones of the chips separated from the semiconductor wafer are encapsulated in a package.

In the data storage process, desired data is stored in a nonvolatile memory device.

Since the test of the nonvolatile memory device is performed in the test step, a good semiconductor integrated circuit device can be obtained in the data storage step even if any data is stored for the nonvolatile memory device.

Although the above test step is effective for any nonvolatile memory device, in particular, when the nonvolatile memory device is an EPROM and is sealed with a package such as a plastic that does not transmit ultraviolet light as shown in Figs. This function is effective when the nonvolatile memory device is used as a write only once and the erase function is disabled.

The nonvolatile memory device having the single-layer gate structure according to the present invention may be used for data change or correction of the mask ROM in addition to the defect relief of the mask ROM. In addition, the nonvolatile memory device may be applied to a PLD used as a logic crystal device and used to set / change a circuit function. In the case of using a non-volatile memory device having a single-layer gate structure for setting or changing a function of such a mask ROM or a digital integrated circuit, it is only necessary to add a diffusion layer forming a control gate, and a well region can be used in a CMOS circuit. This also becomes unnecessary, and the manufacturing process can be simplified as compared with the case of using a nonvolatile memory device having a two-layer gate structure. In addition, since the barrier layer is provided in the nonvolatile memory device having the one-layer gate structure, high reliability can be obtained. The nonvolatile memory device of the two-layer gate structure of this embodiment may itself constitute one semiconductor memory device. However, the cell size is significantly larger than that of the nonvolatile memory device having the two-layer gate structure. Therefore, the nonvolatile memory device of the single-layer gate structure of this embodiment is suitable for the defect storage of memory circuits such as the mask ROM and the like and the small capacity memory circuits for setting / changing the functions of the digital circuits.

The working effect obtained in the above Example is as follows. That is, (1) a significant improvement in data retention characteristics can be obtained by forming a front wall layer covering the upper entire surface of the floating gate made of a conductor layer formed so that a part thereof overlaps with a thin insulating film with respect to the control gate formed by the diffusion layer. The effect that it becomes possible is obtained.

(2) In the case of a nitride film formed by plasma CVD as a final passivation film in a semiconductor integrated circuit device, an inexpensive plastic package can be used, and the barrier layer is used to improve data retention characteristics. The effect that an inexpensive semiconductor integrated circuit device can be obtained is obtained.

(3) By using the oxide layer formed by the conductor layer or the plasma CVD method, the barrier layer can obtain the effect of improving the data retention characteristics of the nonvolatile memory device having the single-layer gate structure without adding a special manufacturing process. .

(4) The barrier layer can be formed integrally with a word line made of an aluminum layer to which the control gate is connected, whereby the barrier layer can be easily formed.

(5) By using the non-volatile memory device of the single-layer gate structure provided with the barrier layer for use in defect repair or function setting / change of the mask ROM or digital circuit, the defect repair under high reliability while preventing an increase in the manufacturing process. And the effect that the function setting / change is enabled.

(6) In a semiconductor integrated circuit device including an analog circuit and a ROM or a RAM, the effect of executing the rescue of the ROM or the RAM before sealing with a package and trimming the analog circuit after the sealing with the package is obtained.

(7) By using a non-volatile memory device having a single-layer gate structure provided with a barrier layer for defect repair or data correction and modification of the mask ROM, these defect relief or data correction and alteration can be made with high reliability without increasing the manufacturing process or the occupied area. The effect that this becomes possible is obtained.

(8) The source of the nonvolatile memory device having a plurality of single-layer gate structures corresponding to the word line is connected to the common source line, and the grounding potential of the circuit is controlled by a switch element that is controlled by the selection signal of the corresponding word line. By applying it, it is possible to prevent the occurrence of leakage current in the memory element of the non-selected word line, thereby achieving the effect of improving the breakdown voltage.

(9) The nonvolatile memory elements arranged in the matrix form are simultaneously written to a plurality of memory cells connected to one word line in accordance with write data held in a chip circuit provided in a data line coupled thereto. The effect that the write time can be shortened is obtained.

(10) The selection signal of the word line can be simplified by using a driving circuit which forms an output level in accordance with the conductance ratio of the load MISFET and the driving MISFET, and is grounded to a common source of the nonvolatile memory device. In the switch element to which the potential is applied, the effect that the leakage current can be reliably prevented is obtained by transmitting the selection signal formed by the CMOS circuit via the subword line.

(11) As in the case where the nonvolatile memory device is an EPROM, the voltage Vcc for performing a normal operation is set to a relatively small voltage such as 5 V in a normal state, and a high voltage such as 7 V or 8 V in a write operation. This achieves the effect that the manufacturing process of the semiconductor integrated circuit can be simplified without the need for using a high breakdown voltage MISFET as the light circuit.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the Example, this invention is not limited to the said Example, Of course, can be variously changed in the range which does not deviate from the summary. For example, the barrier layer may be formed above the floating gate layer as a lower layer than the final passivation film. Various embodiments of the pattern of the nonvolatile memory device having the one-layer gate structure can be adopted.

The non-volatile memory device of the one-layer gate structure according to the present invention executes the light as a thermal carrier, and erases the light by applying a high voltage to the source or drain to perform a tunnel current or electrically and writes and erases to the tunnel current. It can also be used as an erasable nonvolatile memory device.

INDUSTRIAL APPLICABILITY The present invention can be widely used for a nonvolatile memory device having a one-layer gate structure itself and a semiconductor integrated circuit device using the same for setting or changing a function or redundancy circuit.

The effects obtained by the representative ones of the inventions disclosed herein will be briefly described as follows. That is, by forming a barrier layer so as to cover the entire surface or part of the floating gate formed of a conductor layer formed so that a part of the control gate formed by the diffusion layer overlaps with a thin insulating film, a significant improvement in data retention characteristics is possible. do. In addition, by using the non-volatile memory device having a single-layer gate structure provided with the barrier layer for use in defect repair or function setting / change of a mask ROM or digital circuit, the defect repair can be performed under high reliability while preventing an increase in the manufacturing process. Function setting / change is possible.

Claims (17)

A memory matrix including a plurality of read-only memory cells, a decoder for selecting a memory cell in the memory matrix according to an address signal, a redundant memory matrix including a plurality of electrically programmable memory cells, and separated from the decoder A redundancy decoder for selecting an electrically programmable memory cell in the redundant memory matrix in accordance with a signal and an output circuit coupled to the decoder and the redundant decoder and selectively outputting data in any one of the memory matrix and the redundant memory matrix And a semiconductor memory device for outputting data stored in an electrically programmable memory cell instead of data stored in the selected memory cell when the selected memory cell has a combination according to the address signal. . 2. The memory matrix of claim 1, wherein each of the memory matrices includes a plurality of data lines coupled to read only memory cells and a plurality of word lines coupled to read only memory cells, and the decoder includes a plurality of word lines in the plurality of word lines in the memory matrix. A redundancy memory matrix including a first decoder circuit for selecting a line, a second decoder circuit for forming a selection signal, and a column selection circuit for selecting data lines from a plurality of data lines in the memory matrix in accordance with the address signal; A redundant decoder data line, each of which is electrically coupled with a programmable memory cell, wherein the redundant decoder is divided into the first decoder circuit and the second decoder circuit and forms a redundant select signal and the column; Separated into a selection circuit, and the plurality of Chapter data includes a redundant column selection circuit for selecting a redundant data lines in a line, wherein the output circuit includes a semiconductor memory device to which is bonded with the column select circuit the redundancy column selection circuit. 3. The semiconductor memory device according to claim 2, wherein each of said electrically programmable memory cells comprises a control gate formed by an impurity layer and a floating gate having a conductive layer and having an overlapping portion through an insulating layer. 4. The semiconductor memory device according to claim 3, wherein each of said electrically programmable memory cells further comprises a barrier layer provided to cover a portion of said floating gate. 5. The semiconductor memory device according to claim 4, comprising write means coupled to said redundant memory matrix to electrically write data to said electrically programmable memory cell. 6. The semiconductor memory device according to claim 5, further comprising a defect address memory circuit including a plurality of electrically programmable memory cells and storing an address signal of a defective memory cell. 7. The semiconductor memory device according to claim 6, further comprising write means coupled to said defect address memory circuit and electrically writing data to a plurality of electrically programmable memory cells in said defect address memory circuit. 3. The semiconductor memory device according to claim 2, comprising write means coupled to said redundant memory matrix to electrically write data to said electrically programmable memory cell. 3. The semiconductor memory device according to claim 2, wherein said redundant memory matrix is separated from said memory matrix. A memory matrix including a plurality of data lines, a plurality of word lines, and a plurality of read-only memory cells respectively coupled to the data lines and word lines, a row decoder for selecting a word line from the plurality of word lines according to a row address signal, and a column A column decoder for forming a selection signal according to an address signal, a column selection circuit for selecting data lines from the plurality of data lines in accordance with the formed selection signal, several redundant word lines, several redundant data lines, and each redundant word A redundant memory matrix comprising a plurality of electrically programmable memory cells coupled to a line and a redundant data line, a redundant decoder separate from the column decoder and forming a redundant select signal in accordance with a column address signal, separate from the column select circuit And the plurality of dragons according to the redundancy selection signal. A redundant column selection circuit that selects a redundant data line from a data line, and if a match is detected between a row address signal to be supplied to the row decoder and a defective row address signal representing a combined word line in the memory matrix, the plurality of redundant words A read-only memory having a detection circuit for forming a redundant word line selection signal for selecting a redundant word line from a line, and an output circuit for outputting a signal from any one of the column selection circuit and the redundant column selection circuit; A semiconductor memory device for outputting data stored in an electrically programmable memory cell instead of data stored in an accessed read-only memory cell when the cell was a memory cell coupled to a defective word line. 12. The semiconductor memory device according to claim 10, wherein each of said electrically programmable memory cells comprises a control gate formed by an impurity layer and a floating gate including a conductive layer and having a portion overlapping through an insulating layer. 12. The semiconductor memory device according to claim 11, wherein each of said electrically programmable memory cells further comprises a barrier layer provided to cover a portion of said floating gate. 13. The semiconductor memory device according to claim 12, comprising write means coupled to said redundant memory matrix to electrically write data to said electrically programmable memory cell. The semiconductor memory device according to claim 13, wherein the detection circuit comprises a plurality of electrically programmable memory cells and a defect address memory circuit for storing a defective row address signal. 15. The semiconductor memory device according to claim 14, comprising write means coupled to said defect address memory circuit and electrically writing data to a plurality of electrically programmable memory cells in said defect address memory circuit. 11. The semiconductor memory device according to claim 10, comprising write means coupled to said redundant memory matrix to electrically write data to said electrically programmable memory cell. The semiconductor memory device of claim 10, wherein the redundant memory matrix is separated from the memory matrix.