JP3565762B2 - Trimming method and semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit function setting method and a semiconductor integrated circuit device using the same, for example, used in a probing process including a defect remedy technique of a memory matrix including a read-only memory cell and a method of setting a circuit function after sealing. And effective technology.
[0002]
[Prior art]
2. Description of the Related Art A technique using an EPROM (erasable & electrical read only memory) for repairing a defect in a mask ROM and changing stored data is known. A technique using a single-layer polysilicon gate structure as the EPROM is described in, for example, "Technical Report of the Institute of Electronics, Information and Communication Engineers," Vol. 90, no. 47, pages 51-53. A technique using a two-layer gate structure as the EPROM is described in, for example, JP-A-61-47671.
[0003]
[Problems to be solved by the invention]
The inventor of the present application has analyzed the data retention characteristics of the EPROM and found that the following phenomenon occurs. FIG. 16 shows data retention characteristics of EPROMs having different structures. In the figure, the horizontal axis represents time, and the vertical axis represents the threshold voltage variation rate [ΔVth _t ÷ ΔVth ₀ × 100]%. Here, ΔVth ₀ Indicates a threshold voltage at the time of writing, and ΔVth _t Indicates the threshold voltage after elapse of the time t. In addition, data retention characteristics in an environment where the device is left in air at a temperature of 300 ° C. are examined.
[0004]
In FIG. 16, the element structure of the characteristic B is an EPROM having a single-layer polysilicon gate structure, and the characteristic D is an EPROM having a two-layer gate structure. The inventor of the present application does not mean that the control gate in the two-layer gate structure acts as a barrier layer to prevent a reduction in information charges accumulated in the floating gate due to the difference in data retention characteristics between the two EPROMs. I guessed.
[0005]
To confirm this, an EPROM having a single-layer polysilicon gate structure in which an aluminum layer is provided on the entire upper surface of the floating gate made of the single-layer polysilicon is formed. Data retention characteristics were improved. Further, it has been found that when an oxide film (P-SiO) formed by a plasma-CVD method is provided on the upper part of the device with a two-layer gate structure, good data retention characteristics such as characteristic C can be obtained. The oxide film (P-SiO) is formed as an interlayer insulating film for a two-layer aluminum wiring. That is, the first aluminum layer is formed on the BPSG film, and the second aluminum layer is formed thereon via the oxide film (P-SiO). EPROM.
[0006]
As a result of careful analysis of the relationship between the element structure and the data retention characteristics as described above, the present invention relates to a nonvolatile memory element having a single-layer gate structure with improved data retention characteristics and a semiconductor integrated circuit device using the same. It came to be.
[0007]
An object of the present invention is to provide a circuit function setting method which is simple to manufacture and has high reliability, and a semiconductor integrated circuit device using the same. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a nonvolatile memory element having a single-layer gate structure for improving data retention characteristics. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. That is, using a function block and a function setting circuit for setting a circuit function of the function block, the circuit function of the function block is set in a first function setting step of the integrated circuit formed on the semiconductor wafer, and sealing is performed. In a step, the integrated circuit is sealed in a package, and in a second function setting step, the circuit function of the function block is set for the integrated circuit sealed in the package, and the second function setting is performed. In the process, the setting of the circuit function of the functional block is electrically performed.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cross-sectional view showing a manufacturing process for explaining a nonvolatile memory element according to the present invention, together with an N-channel MOSFET and a P-channel MOSFET formed simultaneously. In this specification, MOSFET is used to mean an insulated gate field effect transistor (IGFET).
[0010]
1A to 1D, a nonvolatile memory element QE having a single-layer polysilicon gate structure, an N-channel MOSFET QN, and a P-channel MOSFET QP are shown from the left. The N-channel MOSFET QN and the P-channel MOSFET QP constitute a peripheral circuit such as an address selection circuit of the nonvolatile memory element QE, and other memory circuits and digital circuits formed on the same semiconductor substrate as the EPROM according to the present invention. Used for Further, the nonvolatile memory element QE is a cross-sectional view in which the left side is perpendicular to the source and the drain and the right side is parallel.
[0011]
1A, a P-type well 2 and an N-type well 102 are formed on one main surface of a P-type semiconductor substrate 1 by a known means. Next, a thick field insulating film 3 and a P-channel stopper 4 indicated by a dotted line in FIG.
[0012]
In FIG. 1B, an N-type diffusion layer 6 to be a control gate of the nonvolatile memory element QE is formed. Although the N-type diffusion layer 6 is not particularly limited, phosphorus is accelerated to 1 × 10 at an acceleration energy of 80 Kev through the insulating film 5 by an ion implantation method. ¹⁴ cm ^-2 After the implantation, a heat treatment is performed for about 30 minutes at a temperature of 950 ° C. in an atmosphere containing about 1% of oxygen in nitrogen. Of course, the impurities may be arsenic alone or both arsenic and phosphorus. Although it is basically unnecessary to perform the heat treatment, it is better to perform the heat treatment in order to recover the semiconductor substrate 1 damaged by the ion implantation.
[0013]
Next, after the insulating film 5 damaged by the ion implantation is removed, a clean gate insulating film 7 is formed by a thermal oxidation method. At this time, the thickness of the gate insulating film 7 on the N-type diffusion layer 6 is formed to be about 10 to 20% thicker than the region without the N-type diffusion layer 6.
[0014]
Then, a conductor layer 8 serving as a floating gate of the nonvolatile memory element QE and gate electrodes of the N-channel MOSFET QN and the P-channel MOSFET QP is formed. The conductor layer 8 is formed of a polycrystalline silicon (polysilicon) film or a polycide film in which a silicide film is stacked on the polycrystalline silicon film.
[0015]
As shown in FIG. 1C, N-type diffusion layers 9 and 10 and a P-type diffusion layer 109 are formed. The N-type diffusion layer 9 is ion-implanted with phosphorus at an acceleration energy of 50 Kev and 2 × 10 2. ^Thirteen cm ^-2 It is formed by being implanted to a certain degree. The N-type diffusion layer 10 is formed by ion implantation at a rate of 5 × 10 5 at an acceleration energy of 50 KeV. ^Fifteen cm ^-2 It is formed by being implanted to a certain degree. The P-type diffusion layer 109 is formed by boron ion implantation at an acceleration energy of 15 KeV and 1 × 10 ^Thirteen cm ^-2 It is formed by being implanted to a certain degree.
[0016]
Next, after the CVD insulating film is formed on the entire surface, the sidewalls 11 are formed by anisotropic etching. Then, an N-type diffusion layer 12 and a P-type diffusion layer 112 are formed. The N-type diffusion layer 12 is formed by arsenic by ion implantation at an acceleration energy of 80 Kev and 5 × 10 5. ^Fifteen cm ^-2 It is formed by being implanted to a certain degree. The P-type diffusion layer 112 is formed by ion implantation at a rate of 2 × 10 3 at an acceleration energy of 15 Kev. ^Fifteen cm ^-2 It is formed by being implanted to a certain degree. In this embodiment, the N-type diffusion layer 10 has been described as being formed before the formation of the sidewalls 11, but may be formed after the formation of the sidewalls 11. Further, the manufacturing process of the P-type diffusion layer 109 may be omitted, and the P-type diffusion layer 112 may be formed before the formation of the sidewall 11. In this case, the N-type diffusion layer 9 can be formed by ion-implanting the entire surface without using a mask.
[0017]
In FIG. 1D, in the nonvolatile memory element QE, the control gates are diffusion layers 6 and 10, the floating gate 8, the gate insulating film 7, the interlayer insulating film 7 between the control gate and the floating gate, and the source and the drain are N. It has a one-layer gate structure constituted by the mold diffusion layer 10. The reason why the source and the drain are formed by the N-type diffusion layer 10 is to improve the writing characteristics.
[0018]
The N-type diffusion layer 10 has the same configuration as the source and drain of the N-channel MOSFET QN constituting the input and output. The N-channel MOSFET QN has a so-called LDD structure in which a gate electrode 8, a gate insulating film 7, and sources and drains are formed by N-type diffusion layers 9 and 12. The P-channel MOSFET QP has a so-called LDD structure in which the gate electrode 8, the gate insulating film 7, and the source and the drain are constituted by the P-type diffusion layers 109 and 112.
[0019]
Each element is separated by a field insulating film 3 and a P-type channel stopper 4. Each element is connected by a wiring 15 made of aluminum through a contact hole formed in the insulating film 13. The N-type diffusion layers 6 and 10, which are control gates of the nonvolatile element QE, are shunted by the wiring 15 to reduce parasitic resistance. That is, the wiring 15 forms a word line and is connected to the control gate of each nonvolatile memory element. The N-type diffusion layer 10 is provided to improve ohmic contact with the wiring 15.
[0020]
In this embodiment, an aluminum layer 15 covering the entire surface of the floating gate 8 via an insulating film 13 is formed as a barrier layer in order to improve the data retention characteristics of such a nonvolatile memory element QE having a single-layer gate structure. Is done. The insulating film 13 is composed of a PSG film or a BPSG film. Although not particularly limited, the aluminum layer 15 as a barrier layer formed so as to cover the entire surface of the floating gate via the insulating film 13 is integrally formed with the word line to which the control gate of the nonvolatile memory element QE is connected. Be composed.
[0021]
When the nonvolatile memory element QE of this embodiment is used for relieving defects of a mask ROM as described later, the N-channel MOSFET QN has a structure similar to that of the memory element. However, in FIG. 1A, an N-type impurity is introduced by ion implantation into a portion where a mask ROM is formed, and an N-channel MOSFET formed there is placed in a depletion type.
[0022]
FIG. 4 shows an element pattern diagram of one embodiment of the nonvolatile memory element QE. The N-type diffusion layer 6 serving as a control gate is connected via a contact hole 14 to a word line WL composed of an aluminum layer 15 indicated by a dotted line in FIG. The aluminum layer 15 extends rightward along the floating gate 8 so as to cover the entire surface of the floating gate 8 hatched by a broken line in FIG. It is formed as follows.
[0023]
In the figure, two memory cells are shown symmetrically up and down with respect to the alternate long and short dash line ab. That is, the drain of the upper nonvolatile memory element QE is connected to the aluminum layer 15 via the contact hole 14. The aluminum layer 15 is connected to a data line DL made of a polysilicon layer extending to the left and right via a contact hole 14. Further, the N-type diffusion layer 10 constituting the source of the nonvolatile memory element QE is integrally formed with the source of the lower nonvolatile memory element QE, and the aluminum layer 15 and the drain constituting the barrier layer are made of poly-silicon. It extends rightward along the center line ab to a region that does not intersect with an aluminum layer connected to a word line made of a silicon layer, and extends vertically through a contact hole 14 formed therein, in other words, a word. It is connected to a source line SL made of an aluminum layer extending in parallel with the line.
[0024]
The nonvolatile memory element QE having the single-layer gate structure of this embodiment is provided with a barrier layer made of an aluminum layer formed so as to cover the entire upper surface of the floating gate. In this embodiment, a large-sized barrier layer having a margin so as to exceed the size of the floating gate 8 is used in order to prevent the diffusion of radical hydrogen into the floating gate as described later.
[0025]
From the data holding characteristics shown in FIG. 16, the following is presumed. As compared with the characteristic B, the characteristic D has an improved data retention characteristic. The subsequent difference between the two is that the characteristic B has a single-layer gate structure while the characteristic D has a two-layer gate structure. The inventor of the present application has presumed from this fact that the control gate in the two-layer gate structure has an effect of preventing a factor that penetrates into the floating gate to eliminate the retained charge. In order to confirm this, an element having an aluminum layer as a barrier layer shown in FIG. 1D or 4 was formed on a floating gate in a single-layer gate structure. As shown in the characteristic A, the data retention characteristic is greatly improved.
[0026]
The reason that one of the factors for losing the information charges stored in the floating gate is assumed to be radical hydrogen from the final passivation film is as follows. That is, although omitted in FIG. 16, it is recognized that the data retention characteristics are poorer when a plasma nitride (P-SiN) film is used as the final passivation film than when a CVD oxide (PSG) film is used. Was done. The difference between the two is large in the amount of radical hydrogen. And, it was concluded that the aluminum layer as a barrier layer itself plays a role of a dam for blocking radical hydrogen containing a large amount of hydrogen, thereby preventing diffusion of hydrogen to the floating gate.
[0027]
Further, the barrier layer may be a polysilicon layer. The polysilicon layer also has a property of easily containing hydrogen, and when used as a floating gate, captures hydrogen diffused from the final passivation film and loses information charges. Taking advantage of this fact, a polysilicon layer is provided as a barrier layer on the floating gate. The polysilicon layer serving as the barrier layer first captures and takes in radical hydrogen diffused from the final passivation film, and acts to prevent diffusion to a floating gate provided thereunder. As a result, as in the case of the aluminum layer, the polysilicon layer as the barrier layer functions as a dam for radical hydrogen, so as to prevent intrusion into the floating gate.
[0028]
Although the above phenomenon is merely speculation, as is apparent from the data retention characteristics shown in FIG. 16, the provision of the barrier layer as described above makes it clear that the data retention characteristics of the nonvolatile memory element having a single-layer gate structure are apparent. Significant improvement is observed.
[0029]
When plasma nitride (P-SiN) is used as the final passivation film, an inexpensive plastic package that does not transmit ultraviolet light can be used. Therefore, by providing the barrier layer as in this embodiment, it is possible to obtain a semiconductor integrated circuit device using an inexpensive package while improving data retention characteristics.
[0030]
FIG. 2 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention. This embodiment is directed to a case where a semiconductor integrated circuit device provided with a nonvolatile memory element uses two-layer aluminum wiring. That is, as shown in FIG. 1D, instead of using the first aluminum layer 15 as a barrier layer, a first aluminum layer 15 is formed on an interlayer insulating film 16 formed on the aluminum layer 15. A second aluminum layer 17 is formed to cover the entire surface of the floating gate made of polysilicon layer 8. In this case, when the second aluminum layer 17 is used as a word line, the nonvolatile storage element is formed by using the contact holes 14 provided in the interlayer insulating films 13 and 16 and the first aluminum layer 15. It is connected to a control gate composed of diffusion layers 6 and 10 of QE.
[0031]
Although not shown, in the case where the first aluminum layer 15 is used as a word line, the second aluminum layer 17 formed as the barrier layer is electrically placed in a floating state and is simply placed on the floating gate 8. Formed so as to cover
[0032]
When the two aluminum layers are formed as described above, the second aluminum layer is used as a word line, and the first aluminum layer is used as a data line, or vice versa. Alternatively, the first aluminum layer may be used as a word line, and the second aluminum layer may be used as a data line. Alternatively, the two aluminum layers may be used as a common source line or a sub-word line described later.
[0033]
It should be noted that FIG. 2 also shows an N-channel MOSFET and a P-channel MOSFET. Since the N-channel MOSFET and the P-channel MOSFET are the same as those in FIG. 1D, description thereof will be omitted.
[0034]
FIG. 3 is a sectional view showing the element structure of still another embodiment of the nonvolatile memory element according to the present invention. In the characteristic diagram of FIG. 16, the characteristic C is between the first aluminum layer and the second aluminum layer in order to form a nonvolatile memory element having a two-layer gate structure and a two-layer aluminum wiring. An oxide film (P-SiO) formed by a plasma-CVD method is provided as an interlayer insulating film to be provided.
[0035]
Even with the same two-layer gate structure, a much better data retention characteristic can be obtained as compared with the characteristic D of the nonvolatile memory element having no oxide film (P-SiO). It has been noticed that the oxide film (P-SiO) itself has an action of preventing the diffusion of the radical hydrogen. That is, the oxide film (P-SiO) is made of monosilane (SiH). ₄ ) + Nitric oxide (N ₂ O) as a source gas is introduced into the plasma reaction chamber and adhered to the plasma reaction chamber. The amount of radical hydrogen itself is small, and it is presumed to have an effect of absorbing diffused radical hydrogen.
[0036]
For this reason, in the embodiment shown in the figure, the first interlayer insulating film 13 is formed of a PSG film or a BPSG film, and the second interlayer insulating film 16 is formed of the oxide film (P-SiO). Then, the plasma nitride film (P-SiN) is used as the final passivation film 18.
[0037]
The structure of such an interlayer insulating film is the same as that of the two-layer aluminum wiring shown in FIG. Therefore, on the interlayer insulating film (PSG or BPSG) 13, the first aluminum layer 15 constitutes a word line or the like, and although not shown, on the interlayer insulating film (P-SiO) 16. The second aluminum layer may be formed as a data line, a common source line, or another wiring.
[0038]
In the embodiment of FIG. 2, if an oxide film (P-SiO) formed by the above-mentioned plasma-CVD method is used as the interlayer insulating film 16, the barrier layer is composed of an oxide film (P-SiO) and an aluminum layer. It can be assumed that a good data retention characteristic comparable to the characteristic C of FIG.
[0039]
Hereinafter, a defect relief circuit of a mask ROM using a nonvolatile memory element having a single-layer gate structure as described above will be described.
[0040]
FIG. 6 is a block diagram showing one embodiment of a mask ROM to which the present invention is applied. The memory mat MR-MAT is configured by arranging mask ROM memory elements in a matrix. The memory mat PR-MAT has a configuration in which the nonvolatile memory elements having the single-layer gate structure as described above are arranged in a matrix, and is used for repairing the above-described defect data.
[0041]
In the memory mat MR-MAT, a memory element is arranged at each intersection of a word line and data, similarly to a known mask ROM. The gate of the memory element is a word line, the drain is a data line, and the source is a circuit ground line. Connected to.
[0042]
The word line of the memory mat MR-MAT is selected by the X decoder circuit XDC. The X decoder circuit XDC has an X-system address signal A. _{i + 1} ~ A _n It decodes the complementary internal address signal formed by the received address buffer ADB, and selects one word line of the memory mat MR-MAT.
[0043]
The data line of the memory mat MR-MAT is connected to a common data line by a column switch gate MR-YGT. The column switch gate MR-YGT is connected to the Y-system address signal A. ₀ ~ A _i In accordance with a decode signal formed by a Y decoder circuit YDC for decoding a complementary internal address signal formed by an address buffer ADB receiving the data, one data line is commonly used for each output mat from the memory mat MR-MAT in accordance with the decode signal. Connects to the data line.
[0044]
The common data line is connected to an input terminal of the sense amplifier circuit MR-SAM. The sense amplifier circuit MR-SAM amplifies storage information read from the memory element at the intersection of the selected word line and data line.
[0045]
The memory mat PR-MAT includes a nonvolatile memory element having a single-layer gate structure as described above, arranged at each intersection of a word line and a data line, and is used as a redundant circuit for defective data in the memory mat MR-MAT. Can be The control gate of the nonvolatile memory element is connected to a word line, the drain is connected to a data line, and the source is connected to a ground line of the circuit. A word line of the redundant memory mat PR-MAT is supplied with a redundant word line selection signal formed by a relief address storage circuit PR-ADD described later.
[0046]
The data line of the redundant memory mat PR-MAT is connected to the write data input circuit PR-PGT and the column switch gate PR-YGT. The write data input circuit PR-PGC outputs the Y-system address signal A ₀ ~ A _i A write signal is applied to one data line in the redundant memory mat PR-MAT by a complementary internal address signal formed by an address buffer ADB receiving the write data input and a data signal formed by an input buffer DIB receiving the write data input DI. Is performed.
[0047]
The column switch gate PR-YGT is connected to the Y-system address signal A. ₀ ~ A _i One data line is connected to a common data line for each output mat of redundant memory mat PR-MAT in accordance with an output signal of Y decoder PR-YDC for decoding a complementary internal address signal formed by address buffer ADB receiving the data. Operate. The common data line is connected to an input terminal of the sense amplifier circuit PR-SAM. The sense amplifier circuit PR-SAM amplifies storage information read from a memory cell (nonvolatile storage element) at the intersection of a word line and a data line selected in the read mode.
[0048]
The output signal of the sense amplifier circuit PR-SAM is input to a multiplexer circuit MPX for switching the sense amplifier. This multiplexer circuit MPX selects either the output signal of the sense amplifier circuit MR-SAM for the mask ROM or the output signal of the sense amplifier circuit PR-SAM for the redundant memory mat PR-MAT, and outputs the output buffer DOB. Tell The output buffer DOB outputs the read data transmitted through the multiplexer circuit MPX to the output terminal DO. ₀ ~ DO _m Sent from.
[0049]
Although not particularly limited, in this embodiment, the nonvolatile storage element is used to store the relief address. The method of storing the rescue address is as follows. _{i + 1} ~ A _n The address signal formed by the received address buffer circuit ADB is converted into write data by the relief address selection circuit RAS, and is stored in the nonvolatile memory element arranged in the relief address storage circuit PR-ADD. Although not particularly limited, the relief address storage circuit PR-ADD can store a plurality of relief word lines. The plurality of relief word lines are used to convert a relief address storage position into a Y-system address signal A. ₀ ~ A _i The address is assigned by a redundant word line selection circuit RAST which decodes a complementary address signal formed by an address buffer circuit ADB receiving the data.
[0050]
The rescue address storage circuit PR-ADD stores the rescue address and the word line selection signal / RWS of the written address. ₁ ~ / RWS _p Is formed, and a word line selecting operation of the redundant memory mat PR-MAT is performed. Further, it forms output switching complementary signals RSDA and / RSDA of the multiplexer circuit MPX. In the present specification, an overbar of a logic symbol having a low level as an active level is replaced with /.
[0051]
The control circuit CONT receives a chip enable signal CE for activating the present semiconductor integrated circuit device and an output enable signal / OE for controlling an output buffer at the time of reading, and receives each circuit block activation signal / ce and a sense signal. An activation signal / sac for the amplifier circuit MR-SAM and an activation signal / doc for the output buffer circuit DOB are formed and used for writing in nonvolatile memory elements (PR-MAT, PR-ADD) arranged for redundancy. The high voltage terminal Vpp receives, but is not limited to, a write enable signal / WE for performing write control, and forms an internal write control signal / we, a write signal RS for relief address storage, RWNS, and the like.
[0052]
FIG. 7 is a circuit diagram showing one embodiment of the redundant word line selection circuit RAST. Y-system address signal A ₀ ~ A _h (H ≦ i) Complementary address signal a formed by address buffer circuit ADB receiving ₀ , / A ₀ ~ A _h , / A _h Receiving signal RWNS activated at the time of writing into the storage element of the relief address storage circuit PR-ADD, the storage position allocation signal AST ₁ ~ AST _j Is formed. For example, a 3-bit address signal A ₀ ~ A ₂ Is used, an allocation signal AST of eight storage locations is obtained. ₁ ~ AST ₈ Can be formed. As a result, the word lines of the memory mat MR-MAT in which up to eight defective bits exist can be replaced with the memory cells of the redundant memory mat PR-MAT. Therefore, when the above-described relief address storage circuit PR-ADD is used, the nonvolatile memory elements corresponding to the eight word lines are arranged in a matrix in the redundant memory mat PR-MAT.
[0053]
FIG. 8 is a circuit diagram of an embodiment of the relief address selection circuit RAS. The relief address selection circuit RAS outputs the X-address signal A _{i + 1} ~ A _n Address signals a formed by the address buffer circuits ADB respectively receiving _{i + 1} ~ A _n Receiving the signal RWNS activated when the rescue address storage circuit PR-ADD is written to the nonvolatile storage element, the input address signal a _{i + 1} ~ A _n Is the write data RAWa _{i + 1} ~ RAWa _n To the relief address storage circuit PR-ADD. The stored rescue address and X-system address signal A _{i + 1} ~ A _n Address signal Ca for comparison with _{i + 1} ~ Ca _n Are formed in the previously assigned relief address storage unit.
[0054]
FIG. 9 is a circuit diagram of one embodiment of the relief address storage circuit PR-ADD. The rescue address storage write signal RS is transmitted to the word line to which the nonvolatile memory element having the single-layer gate structure arranged as the storage element is coupled, and the memory formed by the rescue address selection circuit RAS. Address data RAWa _{i + 1} ~ RAWa _n Is transmitted to the data line, whereby writing to the memory element is performed.
[0055]
The data line to which the memory element storing the relief address is connected is connected to the input terminal of the sense amplifier SA, and is amplified by the sense amplifier SA during a read operation. In this embodiment, although not particularly limited, an extra 1-bit memory element is provided as a memory element for storing the relief address in addition to the above-described relief address. By storing arbitrary data of “1” information or “0” information in the 1-bit memory element, it is determined whether or not the relief address is stored, and the activation signal of the sense amplifier SA and the The address comparison signal Ca of the relief address selection circuit RAS _{i + 1} ~ Ca _n Activation signal / RS for formation ₁ ~ / RS _p Is formed.
[0056]
When reading of the memory element storing the relief address is performed, each output signal of the sense amplifier SA becomes the address comparison signal Ca. _{i + 1} ~ Ca _n Is input to an exclusive-OR circuit to confirm the match / mismatch with The output of this exclusive OR circuit is the output of the sense amplifier SA and the address comparison signal Ca. _{i + 1} ~ Ca _n Is "0" if the two match, and "1" otherwise. When all the data in the memory element for storing the relief address match, the redundant word line selection signal RWS is output. ₁ ~ RWS _p Is activated as a selection signal. Further, the redundant word line selection signal RWS ₁ ~ RWS _p Is selected, activation of the sense amplifier circuit PR-SAM provided in the redundant memory mat PR-MAT and switching signals RSAD and / RSAD supplied to the multiplexer MPX are formed.
[0057]
FIG. 10 is a circuit diagram of one embodiment of the write data input circuit PR-PGC. Y-system address signal A ₀ ~ A _i Complementary internal address signal a formed in the address buffer circuit ADB receiving the data. ₀ , / A ₀ ~ A _i , / A _i And the data Data, and write data Dy to each data line of the redundant memory mat PR-MAT by the write signal we. ₀ ~ Dy _k Supply.
[0058]
FIG. 11 shows a circuit diagram of one embodiment of the Y decoder circuit PR-YDC for redundancy. The Y decoder circuit PR-YDC for redundancy uses the Y address signal A ₀ ~ A _i Complementary internal address signal a formed in the address buffer circuit ADB receiving the data. ₀ , / A ₀ ~ A _i , / A _i And the column selection signal y supplied to the column switch gate PR-YGT ₀ ~ Y _k To form
[0059]
FIG. 12 is a circuit diagram showing one embodiment of the redundant memory mat PR-MAT, column switch gate PR-YGT, and sense amplifier circuit PR-SAM.
[0060]
FIG. 13 shows a circuit diagram of an embodiment of the multiplexer MPX. In this embodiment, a clocked inverter circuit having a three-state output function is used. When the inversion switching signal RSDA is activated, the clocked inverter circuit receiving the read signal of the memory element selected by the memory mat MR-MAT constituting the mask ROM is activated, and the clocked inverter circuit is supplied to the output buffer circuit DOB. Tell When the non-inverted switching signal RSDA is activated, the clocked inverter circuit receiving the read signal of the memory element selected by the redundant memory mat PR-MAT is activated and transmits it to the output buffer circuit DOB. . That is, the correct data stored in the redundant memory mat PR-MAT is output instead of the read data including the defective bit existing in the memory mat MR-MAT.
[0061]
FIG. 14 is a circuit diagram showing another embodiment of the mask ROM to which the present invention is applied. The mask ROM of this embodiment includes a plurality of series circuits of N-channel type storage MOSFETs. Each of the storage MOSFETs Qm is formed as a depletion type or an enhancement type according to stored information. Writing of storage information to such a memory element is performed by the ion implantation method as described above. In the figure, the depletion type MOSFET is distinguished from the enhancement type MOSFET by adding a straight line to the channel portion.
[0062]
A series circuit corresponding to one data line D1 exemplarily shown as a representative includes MOSFETs T1 and T2 for column selection and storage MOSFETs Q1 to Q3 for data storage. In the series circuit adjacent to this and corresponding to another data line D2 exemplarily shown as a representative, storage MOSFETs Q4 to Q6 for data storage are connected to MOSFETs T3 and T4 for column selection.
[0063]
For example, when the MOSFETs T1 and T4 for column selection shown by way of example are constituted by depletion type MOSFETs, and T2 and T3 are constituted by enhancement type MOSFETs, respectively, and when other series MOSFETs omitted in FIG. When the selection signal supplied to the gates of T1 and T3 by the column selector is at a low level and the selection signal supplied to the gates of T2 and T4 is at a high level, both T1 and T2 are turned on and serially connected to the data line D1. Storage MOSFETs Q1 to Q3 and the like are connected. When the selection signal supplied to the gates of T1 and T3 by the column selector is at a high level and the selection signal supplied to the gates of T2 and T4 is at a low level, both T3 and T4 are turned on and the data line D2 Are connected to storage MOSFETs Q4 to Q6 in series. Therefore, although not shown, a plurality of series circuits can be provided in parallel with respect to each of the data lines D1, D2, and the like in FIG.
[0064]
Of the storage MOSFETs in the serial form of the memory array, the gates of the storage MOSFETs Qm corresponding to the lateral direction are commonly connected to word lines W1, W2, W3, etc., which are exemplarily shown as representatives. These word lines W1 to W3 are connected to corresponding output terminals of the X decoder.
[0065]
The data lines D1, D2, etc. are connected to a common data line CD via a Y decoder. The Y decoder of FIG. 1 shows the Y decoder itself and a column switch circuit including a switch element that is switch-controlled by a selection signal thereof.
[0066]
The common data line CD is connected to the input terminal of the sense amplifier SA. The sense amplifier SA senses and amplifies the high level and the low level of the read signal of the selected memory cell with reference to the reference voltage generated by the reference voltage generation circuit VRF.
[0067]
Although not particularly limited, the sense operation may be performed with reference to a reference voltage formed by a dummy array including a memory circuit similar to the memory array unit as a reference voltage of the sense amplifier SA. As the dummy array, a memory array in which all of the storage MOSFETs Qm are constituted by enhancement MOSFETs and whose gate is constantly supplied with the power supply voltage Vcc to be constantly turned on can be used.
[0068]
Next, the address selection operation of the vertical ROM in this embodiment will be described. The X decoder decodes the internal address signal supplied from the row address buffer and forms a decode output in which the selected level is set to the low level and the non-selected level is set to the high level. For example, when the number of word lines is 512, one selected word line is set to low level, and all the other 511 word lines are set to high level. Thus, if the storage MOSFET coupled to the selected word line is a depletion type, a current path is formed in the series circuit, and if the storage MOSFET is an enhancement type, no current path is formed.
[0069]
The Y decoder YDCR decodes the internal address signal supplied through the address buffer and selects, for example, one of the 512 data lines and connects it to the common data line CD. Thus, one read signal corresponding to one selected data line is amplified by the sense amplifier SA. When the read data is read in units of a plurality of bits such as 8 bits or 16 bits, 8 or 16 memory arrays similar to the above are provided, or 8 or 16 data lines are simultaneously selected by a Y decoder, What is necessary is just to provide a sense amplifier and an output circuit corresponding to each.
[0070]
To remedy such a vertical ROM defect, the above-mentioned nonvolatile memory element is used. The circuit shown in FIG. 6 and the like can be used for the relief address storage circuit and the redundant memory mat using this nonvolatile storage element.
[0071]
FIG. 15 is a circuit diagram showing another embodiment of the redundant memory mat and its peripheral circuits. Although the circuit symbols given to the respective elements in FIG. 14 partially overlap with the elements shown in FIG. 14, it should be understood that they are different from each other.
[0072]
In the same drawing, one word line W1 and a plurality of storage elements Qm connected thereto are exemplarily shown. The selection circuit for the word line W1 is constituted by a ratio type logic circuit. That is, the selection signal formed by the NAND gate circuit G is supplied to the gate of the N-channel drive MOSFET Q1. The source of the MOSFET Q1 is connected to the ground potential of the circuit, and an N-channel MOSFET Q2 receiving a selection signal inverted by the CMOS inverter circuit N is provided between the drain side and the power supply voltage Vcc. The drain output of the drive MOSFET Q1 is connected to the word line W1 via the depletion type MOSFET Q3 whose gate is supplied with the write control signal / WE. The word line W1 is provided with a depression type load MOSFET Q4. The power supply terminal to which the depletion type load MOSFET Q4 is connected is supplied with a high voltage Vpp during a write operation and a low power supply voltage Vcc such as 5 V during a read operation.
[0073]
In this embodiment, at the time of the write operation of the storage element Qm, in the storage element provided on the non-selected word line, a leak current flows through the channel in response to the potential of the floating gate being raised by the write high level of the data line. In order to prevent this, the source of the storage MOSFET Qm corresponding to the word line is connected to the common source line S1, and a ground potential is applied to this source line via the switch MOSFET Q7.
[0074]
In this embodiment, since the logic circuit is formed by the ratio type logic circuit as described above, when the corresponding word line is in the non-selected state, the level is set to a level higher than the ground potential according to the conductance ratio between the MOSFETs Q1, Q3 and the load MOSFET Q4. The MOSFET Q7 cannot be reliably turned off. That is, at the time of the write operation, the write control signal / WE is at the low level, and when the output signal of the gate circuit G is at the non-selected state of the high level, the MOSFET Q1 is turned on and the word line is connected to the ground potential side of the circuit. However, the level rises above the ground potential in accordance with the ratio of the conductance of the load MOSFET Q4 to the combined conductance of the MOSFETs Q3 and Q1.
[0075]
Therefore, a sub-word line SW1 to which the output signal of the CMOS inverter circuit N1 is supplied is provided, and a selection signal corresponding to the word line W1 is supplied to the gate of the switch MOSFET Q7. With this configuration, when the word line W1 is in the non-selected state, the output signal of the CMOS inverter circuit N is at a low level such as the ground potential, and the switch MOSFET Q7 can be reliably turned off.
[0076]
Accordingly, when the word line W1 is in a non-selected state such as a low level, a high level is supplied to the data lines D1 to D16 and the like, whereby a write operation to the storage element Qm coupled to another word line (not shown) is performed. In this case, it is possible to prevent a leak current from flowing through the storage MOSFET Qm provided on the non-selected word line W1 where writing is not performed. Since the channel current does not flow through the non-selected storage element Qm, the breakdown voltage of the MOSFET is also improved. This is because the MOS breakdown voltage when a channel current flows is due to a parasitic bipolar operation composed of a source, a substrate, and a drain, and is lower than the MOS breakdown voltage due to surface breakdown when no channel current flows.
[0077]
When a word driver for forming a word line selection signal is formed by a CMOS circuit, the word line W1 may be used to control the switch of the switch MOSFET Q7. In this case, since the potential of the word line at the time of the write operation is increased to the high voltage Vpp, the switch MOSFET Q7 needs to have a higher breakdown voltage accordingly.
[0078]
In this embodiment, in order to shorten the writing time, the writing circuit WA having the latch circuit FF is connected to all the data lines D2 to D16... Like the data line D1 exemplarily shown as a representative. Is provided. The storage element Qm is composed of a non-volatile storage element having a single-layer gate structure as shown in FIG. 1D and FIG. Therefore, the size thereof is larger than that of the nonvolatile memory element having the two-layer gate structure. Therefore, the pitch between the data lines becomes relatively large, and the above-described write circuit WA can be provided for each data line without sacrificing the data line pitch of the memory mat.
[0079]
In the configuration in which the write circuit WA is provided for each data line, a write operation including two steps is performed. That is, the write operation of the first step is an operation of storing the write data in the latch circuit FF. At this time, the data input through the data input circuit DIB sequentially selects a data line via the column switch CW, and the data is transferred to the latch circuit FF provided therein. When the data transfer to all the data lines corresponding to one word line or to the latch circuits FF corresponding to a plurality of predetermined data lines is completed, the write operation in the second step is started. In the write operation of the second step, the potential of the selected word line is set to the high voltage for writing the word line, and the high voltage is supplied to the data line D1 in accordance with the data taken into the latch circuit FF of each write circuit WA. The switching of the switch MOSFET Q6 is performed, and charge is injected into the floating gate of the storage element Qm.
[0080]
In this case, since the write current flows simultaneously to a plurality of storage elements as described above, it is necessary to provide the above-described leakage current prevention circuit in order to prevent the write current from becoming enormous. It is necessary.
[0081]
In addition, when a write operation is performed simultaneously on a plurality of storage elements Qm as described above, a relatively large current flows through the storage element Qm in which charge is injected into the floating gate. In such a case, it is necessary to prevent disconnection of the wiring due to migration due to a large current. To prevent such disconnection due to migration, the width of the source line may be increased. However, for high integration, it is not advisable to increase the wiring width. Therefore, by providing a plurality of switch MOSFETs Q7 at regular intervals of the source line S1 and dispersing the write current, it is possible to prevent disconnection due to the above-described migration without forming the source line so thick.
[0082]
The above-mentioned writing operation is performed by, but not limited to, a probing process when a circuit is completed on a semiconductor wafer. That is, in the probing process, a read test of the mask ROM is performed, a defective bit is detected from the inspection result, and a rescue address is written and storage data corresponding to the rescue address is written. In the case of performing defect rescue, by performing writing in the probing process in this way, when the mask ROM is completed, a special control terminal is not required for writing the rescue address and data corresponding thereto. .
[0083]
When the user changes or corrects the data, it is necessary to perform writing after the semiconductor integrated circuit device is completed. Therefore, an appropriate external terminal is provided, or 3 A value input circuit may be provided to multiplex one terminal.
[0084]
Also, the write voltage applied to the data line is not switched from the power supply voltage Vcc to the high voltage Vpp, but the power supply voltage Vcc of about 5 V is raised to about 7 V to 8 V within the allowable range of the breakdown voltage of the MOSFET. The voltage (Vcc ') as shown in FIG. In this case, it is not necessary to increase the breakdown voltage of the write MOSFETs Q6 and Q5, so that the manufacturing process can be simplified. When the high voltage Vpp is used only as a selection level when writing a word line, no DC current flows from the high voltage terminal Vpp, so that the high voltage Vpp can be formed by a relatively simple internal booster circuit.
[0085]
When the write voltage applied to the data line at the time of writing is relatively low, such as about 7 to 8 V, the writing time is relatively long. However, when the non-volatile storage element having a single-layer gate structure is used for defect relief or function change as in this embodiment, the number of write data may be relatively small, so that the unit write time is slightly longer. It will not be a big problem.
[0086]
As described above, in the write operation of the nonvolatile memory element having the single-layer gate structure, the method of increasing the high voltage applied to the drain to the power supply voltage Vcc as Vcc ′ as in the embodiment of FIG. It goes without saying that the present invention can be used not only in the case of using the write circuit WA using the circuit FF but also in the case of inputting data from an external terminal shared with other terminals such as a pad, an external terminal or an address terminal.
[0087]
FIG. 5 shows a pattern diagram of an embodiment of the storage element having the above-described sub-word line. In this embodiment, a sub-word line SW made of the same aluminum layer as the source line SL is arranged in parallel with the source line SL. In the configuration in which the sub-word lines SW are arranged as described above, the size of the memory cell is correspondingly increased. Therefore, in order to prevent this, the source diffusion layer is formed small, and the source line wiring is formed to extend therethrough.
[0088]
17 to 23 show another embodiment of the present invention. In these embodiments, a part of the floating gate is exposed from the barrier layer covering the upper part of the floating gate. That is, the barrier layer does not cover the entire surface of the floating gate but covers a part thereof.
[0089]
As described above, it is desirable to form a barrier layer so as to cover the entire surface on the floating gate in order to improve data retention characteristics. However, if the entire surface of the floating gate is covered, the size of the nonvolatile memory element is increased accordingly. For this reason, when a large-capacity nonvolatile memory element having a single-layer gate structure is required as in the case of relief of a mask ROM, it is disadvantageous in terms of the degree of integration. Therefore, in order to reduce the size of the nonvolatile memory element, a configuration in which a part of the floating gate is exposed from the barrier layer is used. In other words, the barrier layer does not cover the entire surface of the floating gate but a word line. The shape of the data line or the source line is intentionally partially deformed to the extent possible and extends above the floating gate. By doing so, the floating gate is partially covered with the barrier layer, so that the data retention characteristics can be surely improved.
[0090]
In other words, it is presumed that the cause of impairing the data retention characteristic is that radical hydrogen from the final passivation film reacts and combines with the electrons accumulated in the floating gate, resulting in a decrease in the accumulated electrons. In this case, the rate at which the accumulated electrons decrease per unit time is considered to be proportional to the product of the electron density on the surface of the floating gate and the radical hydrogen density. Therefore, if the area ratio of the floating gate exposed from the barrier layer is reduced, the reaction between radical hydrogen and the electrons stored in the floating gate is reduced, so that the stored electron reduction rate is also reduced. As a result, the data retention characteristics are improved as described above.
[0091]
FIG. 17 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention, and FIG. 18 is a plan view thereof. 17 and 18, the aluminum layer 15 forming the word line WL is intended to be used as a barrier layer of the floating gate 8 by being intentionally extended to the right side (source line side) in FIG.
[0092]
FIG. 19 is a sectional view of the element structure of another embodiment of the nonvolatile memory element according to the present invention, and FIG. 20 is a plan view thereof. 19 and 20, a slit is provided in the aluminum layer 15 forming the word line WL, so that a part of the floating gate 8 is exposed. Although not particularly limited, the slit is formed in a rectangular shape so as to be parallel to a word line extending over two floating gates. When the word line is extended to cover the entire surface of the floating gate to form the barrier layer as described above, the word line becomes thicker. As described above, when the word line is thickened, cracks are formed in the aluminum layer 15 as the word line and the lower insulating film 13 of the aluminum layer 15 due to the stress of the final passivation film, which may impair the element characteristics. Therefore, in this embodiment, slits are provided in the aluminum layer acting as the barrier layer to reduce the substantial thickness, thereby preventing the above-mentioned cracks from occurring.
[0093]
In FIGS. 17 to 20, the aluminum layer 15 forming the word line WL is extended to cover a part of the floating gate. Instead, the data line DL or the source line SL is formed. The aluminum layer 15 may be extended to form a barrier layer that covers a part or the entire surface of the floating gate. Similar to the above, slits may be provided to prevent cracks.
[0094]
FIG. 21 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention, and FIG. 22 is a plan view thereof. 21 and 22, the aluminum layers 15 forming the word lines WL and the data lines DL are respectively extended so as to cover a part of the floating gate 8. In this case, although the ratio of the individual aluminum layers forming the word lines WL and the data lines DL to cover the upper part of the floating gate is small, by making both the word lines WL and the data lines DL function as barrier layers, , The ratio of covering the upper portion of the floating gate 8 can be substantially increased. When the barrier layer is divided into two layers as described above, the thickness of each aluminum layer can be reduced, so that the occurrence of cracks can be prevented without providing the slit as described above.
[0095]
In the above embodiments, the word line WL is constituted by the aluminum layer 15 and the data line DL is constituted by the conductor layer 8 such as polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile memory elements connected to the data line DL is smaller than the number of nonvolatile memory elements connected to the word line WL. That is, since the word line WL is formed of the aluminum layer 15 having a small resistance value, the delay time of the word line WL at the time of reading can be reduced.
[0096]
FIG. 23 is a plan view of another embodiment of the nonvolatile memory element according to the present invention. In the embodiment of FIG. 23A, the word line WL is constituted by a conductor layer 8 made of polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile memory elements connected to the word line WL is smaller than the number of nonvolatile memory elements connected to the data line DL. The data line DL is composed of an aluminum layer 15 as shown by a dotted line in FIG. Therefore, barrier layer is formed by forming aluminum layer 15 constituting data line DL so as to extend to a part of the upper portion of floating gate 8.
[0097]
In the embodiment shown in FIG. 23B, the word line WL is constituted by a conductor layer 8 made of polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile memory elements connected to the word line WL is smaller than the number of nonvolatile memory elements connected to the data line DL. The data line DL and the source line SL are composed of an aluminum layer 15 as shown by a dotted line in FIG. In this embodiment, the aluminum layer 15 forming the source line SL is extended to a part of the upper part of the two floating gates 8 forming the two nonvolatile memory elements sandwiching the source line SL. The barrier layer is constituted by being formed.
[0098]
As in the embodiment shown in FIGS. 21 and 22, the aluminum layers 15 of both the data line DL and the source line SL are extended so as to cover and partially cover the floating gate 8, respectively. Is also good.
[0099]
24A to 24D are cross-sectional views showing a manufacturing process for explaining another embodiment of the nonvolatile memory element according to the present invention, together with an N-channel MOSFET and a P-channel MOSFET formed simultaneously. Have been.
[0100]
In this embodiment, unlike the nonvolatile memory element shown in FIGS. 1A to 1D, the step of forming the N-type diffusion layer 6 is omitted. That is, the control gate of the nonvolatile memory element QE of this embodiment is connected to the N-type well region 102 (n ⁻ ). Further, in the nonvolatile memory element QE, similarly to the nonvolatile memory element QE shown in FIGS. 1A to 1D, an N-type diffusion layer 10 is formed so as to extend below the floating gate. . That is, the capacitive coupling between the floating gate and the control gate is determined by the capacitance between the N-type well region 102 and the floating gate and the capacitance between the N-type diffusion layer and the floating gate. Since the capacitance coupling can be increased as compared with the case where only the capacitance between the cells is used, the cell size can be reduced.
[0101]
FIG. 25 is a plan view of the nonvolatile memory element corresponding to FIGS. 24A to 24D. In this case, when a depletion-type N-channel MOSFET is formed on the same semiconductor substrate, the capacitance between the N-type well region 102 and the floating gate can be further increased by implanting an N-type impurity used for depletion type. It has the effect of increasing it. Of course, the control gate may be constituted only by the N-type well region 102. Alternatively, a diffusion layer extending below the floating gate, such as the N-type diffusion layer 10, may be used as the control gate without using the N-type well region 102.
[0102]
In this embodiment, the N-type well region formed on the P-type semiconductor substrate is used for the control gate. However, when the N-type semiconductor substrate is used, the nonvolatile memory having the PMOS structure using the P-type well region for the control gate is used. It may be an element, and various modifications are possible.
[0103]
According to the present embodiment, it is possible to obtain a nonvolatile memory element in which a control gate is formed of a diffusion layer without adding any manufacturing process, and therefore, it can be applied to any semiconductor integrated circuit device.
[0104]
Since the distance for separating the N-type well region from another diffusion layer such as the N-type diffusion layer 10 is long in the nonvolatile memory element of the present embodiment, the cell size is as shown in FIG. 4 or FIG. It will be larger than the example cell size. However, as will be described later, the number of nonvolatile storage elements required is small in the case of only address conversion, such as in the case of repairing a RAM, so that there is no problem even if the cell size is slightly large.
[0105]
26A to 26C are cross-sectional views showing a manufacturing process for explaining still another embodiment of the nonvolatile memory element according to the present invention. It is shown together with a storage MOSFET QM constituting a mask ROM having a two-layer gate structure.
[0106]
In this embodiment, adjacent word lines are constituted by different conductor layers 8 and 108 in order to improve the integration degree of the mask ROM. That is, of the plurality of storage MOSFETs arranged in series, the word line of the odd-numbered MOSFET is formed by the first polysilicon layer 8, and the even-numbered MOSFET is formed by the second polysilicon layer 108. Configure a word line. When such an adjacent word line has a two-layer gate structure, a substantial interval between word lines (pitch of storage MOSFET) is reduced, so that the degree of integration can be improved.
[0107]
Also in this case, the nonvolatile memory element QE used for defect relief has a one-layer gate structure in which the control gate is formed of a diffusion layer. The non-volatile memory element has a single-layer gate structure despite the fact that the polysilicon layer has a two-layer structure for the following reasons. In a nonvolatile memory element having a two-layer gate structure, a gate insulating film provided between the first and second polysilicon layers is essentially different from that of a mask ROM having a two-layer gate structure.
[0108]
That is, the two-layer gate structure in the mask ROM is different from the two-layer gate structure in that an insulating film may be formed merely for the purpose of simply electrically separating the first and second gates. The nonvolatile memory element needs to be a thin insulating film whose film quality and film pressure are controlled to satisfy desired write / read characteristics. Therefore, in a nonvolatile memory element having a two-layer gate structure, it is necessary to add a special manufacturing process for forming an insulating film to be formed between the floating gate and the control gate. Therefore, by using the nonvolatile memory element having the single-layer gate structure as described above, defect relief or the like can be performed without substantially increasing the number of manufacturing steps.
[0109]
In FIG. 26A, as in the embodiment shown in FIGS. 1A to 1D, an N-type diffusion layer 6 serving as a control gate, a mask including a first gate insulating film 7 and a first gate electrode 8 are provided. The first MOSFET of the ROM is formed. Insulating films 201 and 211 are formed on the upper and side surfaces of the first gate electrode 8 for insulation from the second MOSFET of the mask ROM.
[0110]
In FIG. 26B, a second MOSFET of a mask ROM including the second gate insulating film 107 and the second gate electrode 108 is formed. In the present embodiment, the floating gate of the nonvolatile memory element QE and the gate electrodes of the N-channel MOSFET QN and the P-channel MOSFET QP constituting the peripheral circuit of the mask ROM are formed by the second-layer conductor layer 108. Of course, these gate electrodes may be constituted by the first conductor layer 8.
[0111]
As shown in FIG. 26C, each of these circuit elements is completed in the same manner as in the above embodiment. However, the passivation film is omitted in FIG. In this embodiment, even if the original semiconductor integrated circuit device has a two-layer gate structure as described above, the manufacturing process is simplified by forming the nonvolatile memory element into a one-layer gate structure.
[0112]
FIGS. 27A and 27B are cross-sectional views of an element structure of an embodiment of a semiconductor integrated circuit device when a nonvolatile memory element having a single-layer gate structure is used for rescue of a dynamic RAM. .
[0113]
The dynamic memory cell in FIG. 27A has a so-called STC structure in which an information storage capacitor includes a conductor layer 203, a dielectric film 204, and a conductor layer 205. The dynamic memory cell in FIG. 27B has a so-called planar structure in which an information storage capacitor includes an N-type diffusion layer 6, a dielectric film 204, and a conductor layer 205. In the figure, the passivation film is omitted.
[0114]
In each of the embodiments shown in FIGS. 27A and 27B, similarly to the embodiment shown in FIGS. 24A to 24E, the nonvolatile memory element having a single-layer gate structure is an N-type. Since the control gate is constituted by the well region 102, there is no additional manufacturing process. Since the defect relief in the dynamic RAM is performed only by address conversion, the number of necessary nonvolatile storage elements may be small, so that there is no substantial problem even if the cell size is large.
[0115]
In the case where two wiring layers 15 and 17 are provided, as shown in the cross-sectional view of FIG. 27B and the plan view of FIG. Are covered by a combination of two layers of wiring layers 15 and 17. That is, in this embodiment, the word line WL is formed of the first aluminum layer 15, and the data line DL is formed of the second aluminum layer 17. Therefore, the two aluminum layers 15 and 17 overlap each other and cover the floating gate provided thereunder.
[0116]
FIG. 29 is a block diagram showing one embodiment of a dynamic RAM incorporating a defect relief circuit using a nonvolatile memory element according to the present invention. The memory section of the dynamic RAM includes a memory mat DR-MAT, a Y gate circuit DR-YGT, and a sense amplifier circuit DR-SAM. The memory mat DR-MAT is configured by arranging a memory cell including an information storage capacitor as shown in FIG. 27A or 27B and a transfer MOSFET for address selection in a matrix. In the case of a dynamic RAM, a non-volatile memory element for storing data later like a mask ROM is not necessary, and a spare memory arranged in a matrix of the same memory cells as the memory mat DR-MAT is used. It comprises a (redundant) memory mat dr-MAT, a Y gate circuit dr-MAT, and a sense amplifier circuit dr-SAM.
[0117]
Further, the dynamic RAM incorporates a substrate bias generation circuit VBBG. That is, as described above, the spare memory mat dr-MAT uses the same volatile memory cells as the memory mat DR-MAT, there is no circuit for writing to the spare memory mat dr-MAT, Except for the fact that a VBBG is mounted, the defect of the dynamic RAM can be remedied in the same manner as in the address conversion of the mask ROM.
[0118]
Although not particularly limited, at the time of writing to the nonvolatile memory element, the substrate bias generation circuit VBBG is inactivated, and the semiconductor substrate is set to the circuit ground potential (ground potential). This is because a high voltage is applied to the control gate formed of the diffusion layer formed on the semiconductor substrate when writing to the nonvolatile memory element, so that the voltage of the PN junction does not become too high. In other words, this makes it possible to write to a nonvolatile memory element having a single-layer gate structure using the diffusion layer as a control gate without particularly increasing the breakdown voltage of the PN junction. Needless to say, defect relief for a static RAM can also be realized by the same method as that for defect relief for a dynamic RAM as in this embodiment.
[0119]
FIG. 30 is a block diagram showing an embodiment in which a nonvolatile memory element having a one-layer gate structure according to the present invention is used for a microcomputer or the like. The microcomputer of the present embodiment includes a CPU (microprocessor), ROM, RAM, and I / O (input / output) ports configured on the same semiconductor substrate, and the respective circuit blocks are interconnected by a BUS (bus). Have been. The CPU is provided with a μROM (microprogram ROM).
[0120]
The rescue circuit is indicated by hatching in the μROM, ROM, ROM, and I / O port. These rescue circuits have a configuration similar to the circuits shown in FIGS. 6 to 15. The μROM and the ROM use nonvolatile storage elements to perform address conversion and data storage, and the RAMs use nonvolatile storage. Address conversion is performed using elements. Since these rescue methods are the same as those in the above-described embodiment, description thereof will be omitted. In the I / O port, for example, input / output at TTL level and input / output at CMOS level are changed. By using a nonvolatile memory element having a one-layer gate structure in which a control gate is formed of a diffusion layer as in this embodiment, it is easy to rescue each logic block mounted on a microprocessor or to change a logic such as an I / O port. It can be carried out. Further, it is also possible to prepare a spare BUS and convert the address of each logical block connected to the failed BUS.
[0121]
FIG. 31 is a sectional view of an element structure of an embodiment in which the nonvolatile memory element having a single-layer gate structure according to the present invention is mounted on a conventional EPROM having a two-layer gate structure. The control gate of the nonvolatile memory element QE having the single-layer gate structure according to the present invention is constituted by the N-type well region 102 which does not require any additional manufacturing steps as described above. The N-channel MOSFET QHN and the P-channel MOSFET QHP are high-breakdown-voltage MOSFETs used when writing a nonvolatile memory element (EPROM) QEP having a two-layer gate structure, and include a first gate insulating film 7 and a first gate electrode 8. ing. The N-channel MOSFET QN and the P-channel MOSFET QP are MOSFETs used at a normal operating voltage, and include a second gate insulating film 107 and a second gate electrode. The nonvolatile memory element QEP having a two-layer gate structure includes a floating gate formed of a first gate electrode 8 and a control gate formed of a second gate electrode 108 provided thereon with an insulating film 207 interposed therebetween.
[0122]
In the case where only the EPROM having the two-layer gate structure is relieved as described above, it is easy to use the EPROM having the two-layer gate structure also as the nonvolatile memory element for rescue. However, in the case of the microcomputer shown in FIG. 24, an EPROM whose data can be easily changed is used as a data ROM in the early stage of product development, but the function is the same after temporary data is determined. Even if inexpensive mask ROM is used. At this time, if the repair is performed by the EPROM having the two-layer gate structure, the EPROM having the two-layer gate structure must be changed to the nonvolatile memory element having the one-layer gate structure. ). Therefore, in such a case, as in the present embodiment, the part of the relief circuit is constituted by a circuit including a nonvolatile memory element having a single-layer gate structure from the beginning. Thus, for example, a microcomputer in which the data ROM is changed from an EPROM having a two-layer gate structure to a mask ROM can be easily obtained. Alternatively, this is convenient when the number of nonvolatile storage elements mounted on the microcomputer may be small.
[0123]
FIG. 32 is a sectional view showing an element structure of an embodiment in which the nonvolatile memory element according to the present invention is used for trimming of a semiconductor integrated circuit device including an analog circuit. FIG. An example circuit diagram is shown. As shown in FIG. 32, a semiconductor integrated circuit device including an analog circuit includes an N-channel MOSFET QN and a P-channel MOSFET QP constituting an operational amplifier AMP of a digital section and an analog section, a capacitive element QC, and a resistive element QR. You.
[0124]
The trimming circuit shown in FIG. 33 performs trimming of a reference voltage used in an analog circuit, and sets an internally generated voltage Vin to a desired voltage Vout using 3-bit data. A series resistor circuit R0 is provided between the voltage Vout and the ground potential, and each mutual terminal is connected to one terminal of an operational amplifier AMP via a decoder DEC. The decoder DEC is operated by data generated by the trimming circuits TRC1 and TRC3, and trimming is performed by changing the resistance ratio.
[0125]
First, the PC terminal is set to the ground potential, predetermined data is input to the PD terminal, and trimming data is determined. Next, the Vcc terminal is set to the ground potential, the write voltage Vpp is applied to the PC terminal, the predetermined data is input to the PD terminal, and the nonvolatile memory element QE is written.
[0126]
In the present embodiment, the data is directly input from the PD terminal via the resistor R, but may be as in the above embodiment. Alternatively, only one data input terminal may be provided, and serial data may be changed to parallel data by a shift register to perform writing.
[0127]
Further, a semiconductor integrated circuit device including an analog circuit is often operated with a battery of about 1 V. The threshold voltage of the nonvolatile memory element QE before writing is usually about 1 V, and it is impossible to judge before and after writing. In such a case, (1) the gate voltage of the nonvolatile memory element QE is boosted to a voltage that allows determination before and after writing, for example, about 3 to 5 V. (2) The state before writing is set to the depletion mode, and the mode is set to the enhancement mode after writing. Then, the gate voltage is set to the ground potential and read. (3) The state before writing is set to the enhancement mode by the method described later, and the mode is set to the depletion mode after writing. Then, the gate voltage is set to the ground potential and read.
[0128]
FIG. 34 is a circuit diagram of one embodiment of a memory array having a vertical (NAND) configuration using a nonvolatile memory element according to the present invention, and FIG. 35 is a partial plan view thereof. FIG. 36 shows a principle diagram of the writing method. In FIG. 34, in a memory array having a NAND configuration, nonvolatile storage elements are connected in series, a MOSFET constituting a column switch is provided on the data lines (or bit lines) D0 and D1, and the other end is connected to a circuit. A switch MOSFET is provided between the switch MOSFET and the ground potential point. This configuration is basically the same as the vertical mask ROM except that the storage MOSFET is a nonvolatile storage element and a switch MOSFET is provided.
[0129]
In FIG. 35, a word line WL made of an aluminum layer extending in the vertical direction is commonly contacted with a diffusion layer forming a control gate corresponding to two adjacent data lines DL, and a hatched line overlapping this diffusion layer is shown. The attached control gate is extended so as to straddle the data line DL constituting the source and drain extending in the lateral direction, thereby forming a nonvolatile memory element having a single-layer gate structure connected in series. By adopting such a layout, the occupied area can be reduced to about 42% as compared with a conventional horizontal (NOR) configuration memory array.
[0130]
In FIG. 36, writing is performed sequentially from the source side in the nonvolatile memory element in the serial form. At this time, the control signal SW is set to a low level such as the ground potential so that no DC current flows in the series circuit at the time of writing, and the switch MOSFET is turned off. In the initial state, the threshold voltage of the nonvolatile memory element has a positive voltage (enhancement mode).
[0131]
In this state, writing is performed from the nonvolatile memory element connected to the word line W7, the word line W7 is set to a low level such as the ground potential, and the other word lines W6 to W1 and the control voltages Y0 and Y1 of the column switches are changed to the low level. A relatively high voltage is applied. If the write data D0 is at a low level, no electric field acts between the control gate and the drain. Therefore, no tunnel current flows from the floating gate to the drain, and the threshold voltage (Vth> 0) is maintained. On the other hand, if the write data D0 is at a high level at a relatively high voltage, a high electric field acts between the control gate and the drain, causing a tunnel current to flow from the floating gate to the drain, and the threshold voltage (Vth <0).
[0132]
Hereinafter, similarly, writing is performed by setting the selected word line to the low level in the order of W6 to W0. In such a write operation, since only a tunnel current flows, the write current is small, and a current clamp or the like as in the case of the NOR type configuration is not required, thereby simplifying the circuit configuration.
[0133]
At the time of reading, the control signal SW is set to the high level to turn on the switch MOSFET. In this state, the conventional memory cells are read out in the same manner as the conventional vertical ROM because the depletion type is the enhancement type according to the stored information as described above.
[0134]
FIG. 37 is a circuit diagram of an embodiment in which the nonvolatile storage element according to the present invention is used to enable erasing electrically. In this embodiment, data is written using hot carriers as in a conventional EPROM, and data is erased using a tunnel current as shown in FIG. That is, data writing is performed in the same manner as shown in FIG. In the case of erasing data, the word line of the nonvolatile storage element to be erased is set to low level. As a result, the P-channel MOSFET Q2 is turned on, and a high level (Vpp) is supplied to the source line, and a high electric field is applied between the control gate and the source as shown in FIG. A tunnel current is caused to flow between the gate and the source. The MOSFET Q3 is turned off by the control signal RW at the time of writing and turned on by the control signal RW. MOSFET Q1 is turned on according to the selection / selection of the word line.
[0135]
At the time of reading, the source of the nonvolatile memory element connected to the non-selected word line is opened due to the off state of the MOSFET Q1, so that even if the nonvolatile memory element is overerased and becomes in the depletion state, a leak current flows through the memory element. There is no flow and no problem occurs in reading.
[0136]
FIGS. 38A and 38B are layout diagrams of an embodiment of the semiconductor integrated circuit device according to the present invention. The embodiment shown in the figure is directed to a case where a relief circuit using a nonvolatile memory element according to the present invention is mounted on a mask ROM.
[0137]
In FIG. 38A, a pad is provided at the center of the chip, and a relief circuit is provided as indicated by hatching between the pad and the memory mat MAT.
[0138]
In FIG. 38B, a relief circuit is provided as shaded between pads arranged in two rows in a zigzag pattern provided at the center of the chip.
[0139]
In the above configuration,
1) Since the stress at the center of the chip when it is sealed in the package is small, the characteristic fluctuation of the nonvolatile memory element is small and the reliability can be increased.
2) When the capacity of the mask ROM becomes large, the power supply line, the ground line, or the signal line becomes long. As a result, a malfunction due to signal delay or noise becomes a problem. As a countermeasure, it is necessary to arrange a pad at the center of the chip. In this case, the position where the relief circuit is arranged is desirably around the pad where space can be obtained most easily. This can prevent an increase in chip size.
[0140]
FIGS. 39A and 39B are layout diagrams of another embodiment of the semiconductor integrated circuit device according to the present invention. The embodiment shown in the figure is directed to a case where a relief circuit using the nonvolatile memory element according to the present invention is mounted on a microcomputer.
[0141]
In FIG. 39A, the relief circuits with diagonal lines are combined in one place of the chip. In this configuration, data lines can be easily input from the outside to the relief circuit.
[0142]
In FIG. 39B, the rescue circuits are dispersedly arranged for each functional block to be rescued, for example, μROM, ROM, RAM, or ADC (analog / digital conversion circuit). In this configuration, the relief circuit is provided close to the corresponding circuit, so that the delay time at the time of relief can be shortened.
[0143]
FIGS. 40A and 40B are circuit diagrams of an embodiment of a pad used for a write operation to a nonvolatile memory element. In FIG. 40A, a P-channel MOSFET having a high resistance value for pulling up a pad to a power supply voltage Vcc is provided. In FIG. 40B, an N-channel MOSFET having a high resistance value for pulling down the pad to the ground potential of the circuit is provided.
[0144]
In this way, a pull-up or pull-down resistor element is provided for a pad used for a write operation to a nonvolatile memory element having a one-layer gate structure at the time of repair or a function change, and these pads are directly connected to external terminals. do not do. With such a configuration, an increase in the number of external terminals can be prevented. Further, in the semiconductor integrated circuit device in which the defect relief or the function change has been performed as described above, the pad used therein is pulled up or pulled down to a fixed level, so that the pad has an undesired potential. Malfunction can be prevented. The resistance element to be pulled up or pulled down may use polysilicon or the like instead of the high resistance MOSFET as described above.
[0145]
FIG. The A flowchart for explaining an embodiment of the method is shown. In the embodiment of FIG. 41A, trimming data is determined after being sealed in a package by a terminal shared with an external terminal or another terminal.
[0146]
In the embodiment of FIG. 41 (B), of the plurality of bits of data used for trimming, the upper bits are removed in a probing step before a chip is completed on a semiconductor wafer before sealing in a package. After the determination, rough trimming is performed. After the chip is sealed in the package, the remaining lower bits are determined, and minute trimming is performed. By employing such a trimming method, it is possible to perform accurate trimming that can cope with minute fluctuations in element characteristics caused by heat treatment or the like when a chip is sealed in a package.
[0147]
FIG. 42 is a flowchart of an embodiment in which writing is performed on the nonvolatile memory element according to the present invention after the package is sealed. In the chip forming step, a desired semiconductor integrated circuit is formed on a semiconductor wafer as described above.
[0148]
In the test step, a test of the semiconductor integrated circuit including the nonvolatile memory element is performed. The test of the nonvolatile memory element is performed both in a state before writing data and in a state after writing data.
[0149]
In the erasing step, the nonvolatile memory element is returned to the initial state. That is, the state before writing data is set. The erasing operation is performed by irradiating ultraviolet rays when the nonvolatile memory element is an EPROM. In the nonvolatile memory element having the single-layer gate structure of this embodiment, a barrier layer made of aluminum or the like is provided on the floating gate. The aluminum layer itself does not transmit ultraviolet rays, but can be erased by diffracting or irregularly reflecting ultraviolet rays. In particular, when the barrier layer is provided only on a part of the floating gate as in the above embodiment or when the slit is provided, the erasing can be efficiently performed. Even if the entire surface of the floating gate is covered with aluminum to prevent radical hydrogen from the final passivation film from reaching the floating gate, the distance that the barrier layer extends from the floating gate is short, as described above. It can be sufficiently erased by diffraction and irregular reflection of ultraviolet rays.
[0150]
In a conventional EPROM having a two-layer gate structure, when the EPROM having a two-layer gate structure for relieving defects is used for address conversion, the address conversion section is also erased by the erasing operation of the memory array section. In order to prevent this, an aluminum layer covers the entire surface of the address conversion unit. In this case, a large aluminum shielding film is formed in consideration of diffraction and irregular reflection of erasing ultraviolet rays in the memory array section. Therefore, even in the same aluminum layer, in the nonvolatile memory element having the single-layer gate structure according to the present invention, an aluminum layer as a barrier layer for preventing radical hydrogen from entering the floating gate from the final passivation film is provided. Are fundamentally different in their technical ideas.
[0151]
In the encapsulation step, chips that have been determined to be non-defective among the chips individually separated from the semiconductor wafer are encapsulated in a package. In the data storage step, desired data is stored in the nonvolatile storage element. In the test step, a test of the nonvolatile memory element is performed, so that a good semiconductor integrated circuit device can be obtained regardless of what data is stored in the nonvolatile memory element in the data storage step. .
[0152]
The above-described test process is effective for any nonvolatile storage element. In particular, when the nonvolatile storage element is an EPROM and is sealed in a package such as a plastic that does not transmit ultraviolet rays, in other words, This is effective when the non-volatile storage element is used for one-time writing by disabling the erasing function by ultraviolet rays.
[0153]
The nonvolatile memory element having the single-layer gate structure according to the present invention may be used for changing or correcting data in the mask ROM in addition to repairing the defect in the mask ROM. Furthermore, the present invention may be applied to a PLD using a non-volatile memory element as a logic determining element and used to set / change a circuit function. When a nonvolatile memory element having a single-layer gate structure is used for setting or changing the functions of such a mask ROM or digital integrated circuit, it is only necessary to add a diffusion layer for forming a control gate. Since the well region can be used, it is unnecessary, and the manufacturing process can be simplified as compared with the case where a nonvolatile memory element having a two-layer gate structure is used.
[0154]
Since the barrier layer is provided in the nonvolatile memory element having the single-layer gate structure, high reliability can be obtained. The nonvolatile memory element having the single-layer gate structure of this embodiment may constitute one semiconductor memory device by itself. However, the cell size is significantly larger than that of a nonvolatile memory element having a two-layer gate structure. Therefore, the nonvolatile memory element having the single-layer gate structure of this embodiment is suitable for a small-capacity memory circuit for relieving defects of a memory circuit such as a mask ROM as described above and for setting / changing a function of a digital circuit. I have.
[0155]
The operational effects obtained from the above embodiment are as follows. That is,
(1) Forming a barrier layer so as to cover the entire upper surface of a floating gate formed of a conductor layer formed so that a part thereof overlaps a control gate formed of a diffusion layer with a thin insulating film interposed therebetween. As a result, it is possible to obtain an effect that data retention characteristics can be significantly improved.
[0156]
(2) When a final passivation film in a semiconductor integrated circuit device is constituted by a nitride film formed by a plasma CVD method, an inexpensive plastic package can be used. Therefore, the barrier layer improves data retention characteristics. In addition, there is an effect that an inexpensive semiconductor integrated circuit device can be obtained.
[0157]
(3) The barrier layer uses a conductor layer or an oxide film formed by a plasma-CVD method to improve the data retention characteristics of the nonvolatile memory element having a single-layer gate structure without adding a special manufacturing process. The effect that can be obtained is obtained.
[0158]
(4) By forming the barrier layer integrally with a word line made of an aluminum layer to which the control gate is connected, an effect that the barrier layer can be easily formed can be obtained.
[0159]
(5) By using a nonvolatile memory element having a single-layer gate structure provided with the barrier layer for relieving defects or setting / changing functions of a mask ROM or a digital circuit, high reliability can be prevented while preventing an increase in the number of manufacturing steps. Therefore, it is possible to obtain the effect that the defect can be remedied and the function can be set / changed.
[0160]
(6) In a semiconductor integrated circuit device including an analog circuit and a ROM or a RAM, the effect is obtained that the ROM or the RAM can be relieved before the package is sealed and the analog circuit can be trimmed after the package is sealed.
[0161]
(7) By using a non-volatile memory element having a single-layer gate structure provided with a barrier layer for defect repair and data correction change of a mask ROM, it is possible to achieve high reliability without increasing a manufacturing process and an occupied area. Thus, it is possible to obtain the effect that the defect can be repaired and the data can be corrected and changed.
[0162]
(8) The source of the nonvolatile memory element having a single-layer gate structure composed of a plurality of single layers corresponding to the word lines is connected to the common source line, and the ground potential of the circuit is changed by the switch element controlled by the selection signal of the corresponding word line. By providing such an effect, it is possible to prevent the occurrence of a leak current in the storage element of the unselected word line, and to obtain an effect that the withstand voltage can be improved accordingly.
[0163]
(9) The nonvolatile memory elements arranged in a matrix form a plurality of memory cells connected to one word line based on write data held in a latch circuit provided in a data line to which the nonvolatile memory elements are coupled. On the other hand, writing at the same time has an effect that the writing time can be reduced.
[0164]
(10) The word line selection signal can be simplified by using a drive circuit that forms an output level in accordance with the conductance ratio between the load MOSFET and the drive MOSFET, and the nonvolatile memory element can be shared. By transmitting a selection signal formed by a CMOS circuit through a sub-word line to a switch element that applies a ground potential to the source, an effect that leakage current can be reliably prevented can be obtained.
[0165]
(11) As in the case where the nonvolatile memory element is an EPROM, the voltage Vcc for performing a normal operation is set to a relatively small voltage such as 5 V in a normal state, and to a high voltage such as 7 V or 8 V in a write operation. . Thus, there is no need to use a high breakdown voltage MOSFET as a write-related circuit, and an advantage is obtained in that the manufacturing process of the semiconductor integrated circuit can be simplified.
[0166]
Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. Nor. For example, the barrier layer may be formed below the final passivation film and above the floating gate layer. Various embodiments can be adopted for the pattern of the nonvolatile memory element having the single-layer gate structure.
[0167]
In the nonvolatile memory element having a single-layer gate structure according to the present invention, writing is performed by hot carriers and erasing is performed by applying a high voltage to a source or a drain by a tunnel current, or writing and erasing are performed by a tunnel current. It can also be used as a nonvolatile storage element that can be written and erased.
[0168]
INDUSTRIAL APPLICABILITY The present invention can be widely used for a non-volatile memory element having a single-layer gate structure itself and a semiconductor integrated circuit device using the same for function setting or change, a redundant circuit, or the like.
[0169]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, for a memory circuit including a memory matrix including a plurality of read-only memory cells and a decoder for selecting a memory cell from the memory matrix, a redundant memory matrix including a plurality of electrically programmable memory cells; A redundant circuit comprising a redundant decoder for selecting an electrically programmable memory cell from the redundant memory matrix is provided. When a memory cell selected by an address signal has a defect, the data is stored in the selected memory cell. In place of the data, the data stored in the electrically programmable memory cell is output, and each of the electrically programmable memory cells is connected to a control gate formed by an impurity layer and a conductive layer. Included, and The use of those containing a floating gate having a portion, it is possible to defect remedy while preventing an increase in manufacturing steps.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of an embodiment for explaining a nonvolatile memory element according to the present invention.
FIG. 2 is an element structure sectional view showing another embodiment of the nonvolatile memory element according to the present invention.
FIG. 3 is a sectional view of an element structure showing still another embodiment of the nonvolatile memory element according to the present invention.
FIG. 4 is an element pattern diagram showing one embodiment of a nonvolatile memory element according to the present invention.
FIG. 5 is an element pattern diagram showing another embodiment of the nonvolatile memory element according to the present invention.
FIG. 6 is a block diagram showing an embodiment of a mask ROM to which the present invention is applied.
FIG. 7 is a circuit diagram showing one embodiment of a redundant word line selection circuit RAST in the mask ROM of FIG. 6;
8 is a circuit diagram showing one embodiment of a relief address selection circuit RAS in the mask ROM of FIG.
9 is a circuit diagram showing one embodiment of a relief address storage circuit PR-ADD in the mask ROM of FIG.
FIG. 10 is a circuit diagram showing one embodiment of a write data input circuit PR-PGC in the mask ROM of FIG. 6;
11 is a circuit diagram showing one embodiment of a redundant Y decoder circuit PR-YDC in the mask ROM of FIG. 6;
12 is a circuit diagram showing one embodiment of a redundant memory mat PR-MAT, a column switch gate PR-YGT, and a sense amplifier circuit PR-SAM in the mask ROM of FIG. 6;
FIG. 13 is a circuit diagram showing one embodiment of a multiplexer MPX in the mask ROM of FIG. 6;
FIG. 14 is a circuit diagram showing another embodiment of the mask ROM to which the present invention is applied.
FIG. 15 is a circuit diagram showing another embodiment of the redundant memory mat and its peripheral circuits according to the present invention.
FIG. 16 is a data retention characteristic diagram of a nonvolatile memory element for explaining the present invention.
FIG. 17 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.
18 is a plan view of the nonvolatile memory element in FIG.
FIG. 19 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.
20 is a plan view of the nonvolatile memory element in FIG.
FIG. 21 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.
FIG. 22 is a plan view of the nonvolatile memory element in FIG. 21;
FIG. 23 is a plan view showing another embodiment of the nonvolatile memory element according to the present invention.
FIG. 24 is a manufacturing process sectional view for explaining another embodiment of the nonvolatile memory element according to the present invention;
FIG. 25 is a plan view of the nonvolatile memory element in FIG. 24;
FIG. 26 is a manufacturing process sectional view for explaining still another embodiment of the nonvolatile memory element according to the present invention;
FIG. 27 is a sectional view of an element structure showing one embodiment of a semiconductor integrated circuit device in the case where a nonvolatile memory element having a single-layer gate structure according to the present invention is used for relief of a dynamic RAM.
FIG. 28 is a plan view corresponding to FIG. 27 (B).
FIG. 29 is a block diagram showing one embodiment of a dynamic RAM incorporating a defect rescue circuit using a nonvolatile memory element according to the present invention.
FIG. 30 is a block diagram showing one embodiment in which the nonvolatile memory element according to the present invention is used for rescue of a microcomputer or the like.
FIG. 31 is a sectional view of an element structure showing an embodiment in which a nonvolatile memory element having a one-layer gate structure according to the present invention is mounted on a conventional EPROM having a two-layer gate structure.
FIG. 32 is a sectional view of an element structure showing one embodiment in which the nonvolatile memory element according to the present invention is used for trimming of a semiconductor integrated circuit device including an analog circuit.
FIG. 33 is a circuit diagram showing one embodiment of the trimming circuit of FIG. 32;
FIG. 34 is a circuit diagram showing one embodiment of a memory array having a vertical configuration using a nonvolatile memory element according to the present invention.
FIG. 35 is a plan view showing one embodiment of the memory cell of FIG. 34;
FIG. 36 is a principle view showing one embodiment of a writing method of the nonvolatile memory element of FIG. 34;
FIG. 37 is a circuit diagram showing one embodiment in a case where the nonvolatile memory element according to the present invention can be electrically erased.
FIG. 38 is a layout diagram showing one embodiment of a semiconductor integrated circuit device (mask ROM) according to the present invention.
FIG. 39 is a layout diagram showing one embodiment of a semiconductor integrated circuit device (microcomputer) according to the present invention.
FIG. 40 is a circuit diagram showing one embodiment of a pad used for a write operation to a nonvolatile memory element.
FIG. 41 is a flowchart illustrating an embodiment of a trimming method.
FIG. 42 is a flowchart showing one embodiment in which writing is performed on the nonvolatile memory element according to the present invention after the package is sealed;
[Explanation of symbols]
QE..Non-volatile memory element, QN..N channel MOSFET, QP..P channel MOSFET, QHN..High voltage N channel MOSFET, QHP..High voltage P channel MOSFET, QD. Dynamic memory cell, QM.・ Mask type memory cell, QEP ... EPROM with two-layer gate structure, QR ... Resistor element, QC ... Capacitance element,
1. semiconductor substrate, 2,102 well region, 3. field insulating film, 4. channel stopper, 7,107 gate insulating film, 5, 11, 13, 16, 201, 211 insulating Film (interlayer insulating layer), 8, 108, 204, 205 conductive layer, 15, 17, wiring layer, 6, 9, 10, 109, 112 diffusion layer, 14, 114 contact hole, 18 ..Final passivation film, 204..Dielectric film,
ADB address buffer, MR-MAT mask ROM, OR-MAT redundancy memory circuit, XDC X decoder circuit, MR-YGT, PR-YGT column switch gate, YDC Y decoder Circuit, MR-SAM, PR-SAM sense amplifier circuit, DIB input buffer circuit, DOB output buffer circuit, MPX multiplexer, RAS relief address selection circuit, R-ADD relief address storage Circuit, RAST... Redundant word line selection circuit,
CONT control circuit, PR-PGC write data input circuit, WA write circuit, FF latch circuit, DEC decoder circuit, TRC1 to TRC3 trimming circuit, AMP operational amplifier, μROM Microprogram ROM, ROM read only memory, RAM random access memory, CPU microprocessor, ADC analog / digital conversion circuit, PORT input / output port.

Claims (7)

A trimming method for an integrated circuit having a trimming circuit for trimming the analog circuit includes an analog circuit and a nonvolatile memory element,
A first trimming step of storing first trimming data of the analog circuit of the integrated circuit formed on a semiconductor wafer in the nonvolatile storage element ;
A sealing step of sealing the integrated circuit in a package,
A second trimming step of storing, in the nonvolatile memory element, second trimming data for finer adjustment of the analog circuit than the first trimming data for the integrated circuit sealed in the package; Including
In the second trimming step, the storage of the second trimming data in the nonvolatile memory element is performed electrically . In the second trimming step, by applying a voltage from an external terminal of the integrated circuit sealed in the package to change a state of the nonvolatile memory element and storing the second trimming data, 2. The trimming method according to claim 1, wherein the storage of the second trimming data in the nonvolatile memory element is performed electrically. 2. The nonvolatile memory element according to claim 1, wherein the nonvolatile memory element includes a control gate formed in a semiconductor region of a semiconductor substrate, and a floating gate having a portion overlapping the control gate via an insulating layer. Trimming method. 2. The trimming method according to claim 1, wherein the first trimming data is upper bits of the trimming data, and the second trimming data is lower bits of the trimming data . A semiconductor integrated circuit device having a semiconductor integrated circuit and the external terminals including a trimming circuit for trimming the analog circuit and the analog circuit,
The trimming circuit includes first trimming information for trimming the analog circuit determined in the semiconductor integrated circuit, and trimming the analog circuit determined after the semiconductor integrated circuit is sealed in a package . A second trimming information for finer adjustment than the first trimming information can be stored;
The trimming circuit has a nonvolatile storage element for storing the first and second trimming information ,
A semiconductor integrated circuit device wherein the second trimming information is stored by applying a voltage to the nonvolatile storage element from the external terminal and changing the state of the nonvolatile storage element. Upper Symbol nonvolatile memory element, a control gate formed on the semiconductor region of the semiconductor substrate, according to claim 5, characterized in that it comprises a floating gate having the control gate and the overlapped portion through the insulating layer Semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein the first trimming information is upper bits of the trimming information, and the second trimming information is lower bits of the trimming information .

Images