JP2003317497A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor integrated circuit device, in which manufacturing efficiency is improved while maintaining high reliability of nonvolatile memory elements. <P>SOLUTION: Memory information and error correction code bits for detecting and correcting an error corresponding to the memory information are stored in a plurality of memory circuits including nonvolatile memory elements of single layer gate structure, also memory information is read utilizing an error correcting circuit, or memory information of each one bit in memory information of a plurality of bits is stored respectively in a plurality of nonvolatile memory elements of single gate structure, constitution in which a OR signal of the memory information is taken out is formed on a wafer, thus in the test process, of an electric test of the semiconductor integrated circuit device formed on the wafer, a high temperature test in which high temperature is applied to the semiconductor integrated circuit device for a fixed period in a constant temperature oven and a holding state of the memory information is tested can be omitted. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device having an electrically erasable and writable non-volatile memory element, for example, an existing CMOS process without adding a new process. The present invention relates to a technique effectively applied to a manufacturing method of a microcomputer or a memory LSI in which a nonvolatile memory element formed by applying a single-layer poly flash memory technique that can be applied is applied to defect relief or the like.

[0002]

2. Description of the Related Art A single-layer polyflash technique for forming a memory cell of a non-volatile memory with a single-layer polysilicon gate is disclosed in JP-A-6-334190, US Pat. No. 5,440,159, and US Pat. Publication No. 5,50
4,706, U.S. Pat. No. 5,457,335,
And "A single Ploy EEPROM Cell Stru by Osaki et al.
cture for Use in Standard CMOS Processes &# 34, IEEE
Journal of solid state circuits &# 34, VOL. 29, NO.
3, March, 1994, pp311-316. For example, in a non-volatile memory cell using a single-layer polyflash described in JP-A-6-334190, a first conductivity type MOS transistor is formed on a semiconductor substrate, and an insulating layer is interposed in a second conductivity type well. A plate electrode is formed, the gate electrode and the plate electrode of the MOS transistor are commonly connected to function as a floating gate, and the second conductivity type well functions as a control gate.

Japanese Patent Application Laid-Open No. 4-212471 discloses that electric
Discloses also utilized technology writable nonvolatile memory (EPROM) as a repair circuit of the read only memory (ROM). Further, in the same publication, in a nonvolatile memory element having a single-layer gate structure, writing is performed by hot carriers and erasing is performed by tunneling current by applying a high voltage to a source or drain, or writing and erasing is performed by tunneling current. It is described that it can also be used as a non-volatile memory element that can be electrically written and erased.

On the other hand, for the technique of differentially utilizing two nonvolatile memory elements from the viewpoint of preventing malfunction, as disclosed in Japanese Patent Laid-Open No. 6-268180 and US Pat.
No. 029,131 is available. In the differential memory cell structure, one of the nonvolatile memory elements is in a write state and the other nonvolatile memory element is in an erased state, and the read signals read in parallel from both nonvolatile memory elements are differentially amplified. Therefore, the logical value of the stored information is determined according to which of the non-volatile and non-inverted outputs of the nonvolatile memory element in the written or erased state is the input.

[0005]

Since the single-layer polysilicon gate flash memory (hereinafter simply referred to as ieFlash) can be manufactured by the CMOS process, it is used for defect relief and trimming of the memory circuit mounted on the system LSI. It can be replaced by fuse means. When used as a fuse means, the data retention failure is directly connected to the failure of the system LSI itself, and therefore higher reliability is required than when it is used for general data retention. In other words, in the case of data retention, if a defect occurs, another storage area is used, and it is possible to perform substantial relief. In the above ieFlash,
As described above, although the structure is simple so that it can be formed by the CMOS process, it is said that the data retention characteristic is inferior to the flash memory having the stacked gate structure. Therefore, it is considered necessary to evaluate the data retention life by leaving at high temperature (baking).

In general, the system LSI is often manufactured for a specific purpose, and accordingly, it is often a small mass-produced product. For that reason, the data retention life evaluation by leaving the high temperature for the purpose of ensuring the reliability of the ieFlash requires such an IEF.
This causes a decrease in manufacturing efficiency of a system LSI equipped with a lash, resulting in a high cost, which becomes a major cause of hindering the widespread use of a semiconductor integrated circuit device in which the IEFlash is used as a fuse. Therefore, the inventor of the present application has studied to improve the manufacturing efficiency while maintaining the high reliability while utilizing the features of the ieFlash that can be formed by the CMOS process as described above in the ieFlash.

An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device in which manufacturing efficiency is improved while maintaining high reliability of a nonvolatile memory element. Another object of the present invention is to manufacture a semiconductor integrated circuit device in which a flash memory cell whose gate electrode structure is composed of a single-layer gate electrode structure can be used as a relief circuit such as a memory circuit while improving the manufacturing efficiency. To provide a method. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it receives a plurality of storage circuits each including a non-volatile storage element having a single-layer gate structure, first storage information stored in the plurality of storage circuits, and error correction code information corresponding to the first storage information. A semiconductor wafer having a plurality of semiconductor integrated circuit devices including an error correction circuit is set. The above semiconductor wafer is later divided into a plurality of semiconductor chips by a so-called chip division technique, and is formed into a device as a finished product with a required mounting form. The semiconductor wafer does not need to be baked at a relatively high temperature exceeding the allowable operating temperature of the finished product.

1-bit stored information is stored in each of a plurality of non-volatile memory elements having a single-layer gate structure, and 1-bit stored information can be read out by logical synthesis that means a logical sum of the stored information. A semiconductor integrated circuit device including a plurality of such circuits is set. A semiconductor wafer on which the semiconductor integrated circuit device having such a structure is formed is set. Similarly to the above, the semiconductor wafer is later divided into a plurality of semiconductor chips by a so-called chip division technique, and is formed into a device as a finished product with a required mounting form. The application of the baking treatment at a relatively high temperature above the temperature is omitted. More preferably, the plurality of semiconductor integrated circuit devices are subjected to an electrical test in the wafer state, that is, a so-called wafer test. The semiconductor wafer for which the omission of the baking process is allowed is divided into chips and provided for assembling a finished product.

[0010]

FIG. 1 is a circuit diagram showing an embodiment of a memory cell as an information storage cell mounted in a semiconductor integrated circuit device to which the present invention is applied. The memory cell has two nonvolatile memory elements PM1 and PM2 and two read MOSFETs DM1 and DM2. Each of the nonvolatile memory elements PM1 and PM2 is composed of a flash memory element having a single-layer gate structure which can be understood in more detail with reference to FIGS.

In FIG. 1, the nonvolatile memory element PM1,
The floating gate of PM2 is read MOSFE
It is understood that it consists of an electrode coupled to the gate electrodes of TDM1 and DM2. The nonvolatile memory elements DM1 and DM2 are
The respective drains and sources are connected in parallel and are connected between the write data line PDL and the source line Vss.

As will be apparent from the following description, the relative potential difference between the write data line PDL and the source line Vss is
The write operation and the read operation are different. Therefore, the drain and source of the nonvolatile memory element are not fixed in a strict sense. However, here, in order to avoid complication of expression in which one object is expressed by different expressions, a connection point where the nonvolatile memory elements PM1 and PM2 are connected to the read data line is referred to as a drain electrode for convenience. For convenience, the connection point at which the memory elements PM1 and PM2 are connected to the source line Vss is referred to as a source electrode.

Two nonvolatile memory elements PM1 and PM2
Has its control gate coupled to the write word line. The read MOSFETs DM1 and DM2 are
The drain and source paths of the read switch MOSFETSM are connected in series between the read data line RDL and the source line Vss. Read MOSF
The ETSM is controlled by the read word line RWL with its gate coupled.

The nonvolatile memory elements PM1 and PM2 will be described later with reference to specific structural examples based on FIGS.
The outline is as follows. That is, the elements PM1 and P
M2 is a first gate that functions as a control gate electrode.
MOS capacitive elements PM1b and PM2 each composed of a semiconductor region and a capacitive electrode provided on the semiconductor region via an insulating layer.
b, a MOSFET having a first source electrode and a first drain electrode formed in the second semiconductor region, and a gate electrode
It is composed of PM1a and PM2a.

The MOS capacitance elements PM1b and PM2b
In other words, the same structure as that of the MOSFET, that is, the semiconductor region that functions as a back gate, the source electrode and the drain electrode formed therein are used as one electrode, and the semiconductor region is formed on the semiconductor region via a gate insulating film. MOS with one gate electrode as the other electrode (capacitance electrode)
It is composed of the gate capacitance of the FET structure. The capacitance electrodes of the MOS capacitance elements PM1b and PM2b are the same as those of the MOSF.
It is commonly connected to the gate electrodes of ETPM1a and PM2a and functions as a floating gate electrode Vf.

Nonvolatile memory element, read MOSF
The ET and read switch MOSFET has an n-channel type structure in which the first semiconductor region and the second semiconductor region are composed of p-type semiconductor regions. On the other hand, the MOS capacitance elements PM1b and PM2b have a p-channel type configuration. As a result, the MOS capacitance element PM
1b and PM2b are adapted to exhibit appropriate capacitance element characteristics even with respect to a voltage such as a write voltage applied to the semiconductor region (that is, the n-type semiconductor region) that functions as a back gate.

The nonvolatile memory elements PM1 and PM2 are
The configuration is such that hot electron writing and tunnel current erase are possible. That is, when data is written in the nonvolatile memory element, the write data line PDL is used.
Is set to a write potential level such as 5V, the write word line PWL is set to a write selection level such as 5V, and the source line Vss is set to a low potential level such as 0V. As a result, hot electrons generated at the drain electrode are injected into the floating gate electrode, and the nonvolatile memory element P
The threshold voltages of M1 and PM2 are increased.

When erasing the nonvolatile memory elements PM1 and PM2, the write data line PDL and the write word line PW are written.
L, read data line RDL, read word line RWL
Are set to 0V and the source line Vss is set to an erase level such as 6V. As a result, electrons are extracted from the floating gate to the source electrode by the tunnel current,
The threshold voltages of the nonvolatile memory elements PM1 and PM2 are lowered.

The read MOSFETs DM1 and DM2
Has a gate electrode potential of the nonvolatile memory elements PM1, P
It is modified by the write state and erase state of M2, and the switch state or transconductance thereof is made different. During the read operation of the stored information in the nonvolatile storage elements PM1 and PM2, a read potential such as 1.8 V is applied to the read data line RDL via a load (not shown), and the read word line RWL is read as 1.8 V. A selection level potential is applied and a reference potential such as 0V is applied to Vss.

The write word line PWL has a MOS capacitance PM.
The floating gate has a potential according to the stored information regardless of the coupling between the write word line PWL and the floating gate via 1b and PM2b.
It is set to a fixed potential such as 0V. Write data line PDL
Is also brought to a reference potential such as 0V. The gate electrode receives the potential of the selected level of the read word line RWL n
The channel type selection MOSFET SM has the read M
The OSFET DM1 is connected to the read data line RDL. Accordingly, the read data line RDL is electrically connected to the source line Vss via the read MOSFETs DM1 and DM2 if both read MOSFETs DM1 and DM2 are in the ON state.

Here, in the nonvolatile memory element, when a state in which a drain current flows or a state in which an electric field is applied occurs in the nonvolatile memory element, the current and the electric field bring about a clear written state and an erased state within a short time. Even a weak one has a risk of causing an undesired change in the charge of the floating gate after a long time. That is, depending on the unavoidable variations in semiconductor device manufacturing such as microscopic undesiredness of semiconductor crystal and impurity concentration distribution and microscopic changes in gate insulating film thickness, a relatively small drain current is used. However, there is a possibility that weak hot electrons will be generated, and there is a possibility that a tunnel current will be generated even under a weak electric field where a tunnel current should not be generated. Is.
They do not mean destruction or deterioration of the stored data of the non-volatile memory element in a relatively short time, but they mean destruction or deterioration in a remarkably long time.

On the other hand, as described above, when fixing the write data line PDL, the write word line PWL, and the source line Vss to a potential such as the circuit ground potential (0 V), the floating gate is weak. Hot electron injection and undesired electron injection due to tunnel current can be sufficiently reduced.

FIG. 2 shows the read MOSFET DM.
1, the voltage-current characteristic diagram of DM2 is shown. Initial threshold voltage (Vthn of read MOSFETs DM1 and DM2
dm) is higher than the potential (about −2 V) of the floating gate electrode Vf at the time of holding charges (writing state) where writing is performed in the nonvolatile memory elements PM1 and PM2, and writing to the nonvolatile memory elements PM1 and PM2 is performed. The voltage range is set to be lower than the potential (about 0 V) of the floating gate electrode Vf in the initial state of the erased state which is not performed. In other words, the read MOSFETs DM1 and DM2 are preferably depletion type transistors. The read MOSFETs DM1 and DM are not particularly limited.
The depletion type of 2 is such a MOSFET
Is carried out by introducing, for example, low-concentration phosphorus into the surface region of the semiconductor region forming

In the write state in which the floating gate is in the charge holding state, two read Ms connected in series are used.
OSFETs DM1 and DM2 are accordingly cut off. According to the embodiment, the nonvolatile memory element P
The charge held in one of M1 and PM2 leaks undesirably for some reason, such as due to a microscopic defect that occurs in the gate insulating film, and moves toward the initial state or the erased state. Even if it changes, such elements PM1 and PM2
The current path through the read selection MOSFET SM remains cut off in accordance with the charge held in the other element of the above, and no read failure occurs.

The reduction of defects will be described in more detail below. Here, the read failure rate by the memory cell of the 2-cell 1-bit format in which 1 bit is composed of the two nonvolatile memory elements PM1 and PM2 is calculated. now,
One non-volatile memory element constitutes one bit 1 cell 1
When the failure probability after 10 years in the memory cell having the bit structure is f, the probability Pa that both cells are non-defective is Pa = (1-f) ² (1). The probability Pb that one of the cells is defective is Pb = (1-f) f + f (1-f) = 2f (1-f) (2), and the probability Pc that both cells are defective is Pc = f ² (3)

Here, Pa + Pb + Pc = (1-f) ²
+ 2f (1-f) is a + f ² = 1. If the total number of bits of the chip is N, it means that there are no bits in the above state for a non-defective product, and at this time, N bits should be in the state of either equation (1) or equation (2). from good probability Y ^{_{is, Y = Σ N Ck Pa k}} Pb Nk ... (4) , and the chip defect rate F becomes F = 1-Y = 1- Σ N Ck Pa k Pb Nk ... (5).

[0027] The binomial theorem, because it is ^{_{Y = Σ N Ck Pa k Pb}} Nk = (Pa + Pb) N = [(1-f) 2 + 2f (1-f)] N = (1-f 2) N, F = 1− (1−f ² ) ^N (6)

In the case of the 1-cell 1-bit system, the good product probability Y'is a chip defect even if 1 bit out of N bits is defective. Therefore, the good product rate Y'is Y '= (1-f) ^N. (7) and the chip defect rate F'in the case of 1-cell 1-bit method
Becomes F '= 1- (1-f) ^N (8).

Therefore, according to the semiconductor integrated circuit device of the present invention, the improvement rate R of the chip defect rate is R = F / F '= 1- (1-f ² ) ^N / {1- (1-f) ^N } (9), and in the case of f << 1, R = F / F'≈f (10). That is, a remarkable improvement in the defective rate can be achieved.

According to the memory information cell structure shown in FIG. 1, the problems of weak hot electron injection and tunnel current do not occur due to the reasons described above, the long-term data retention performance is improved, and the read failure rate is improved. It becomes possible to realize the decrease.

Further, the configuration in which a plurality of non-volatile memory elements and a plurality of read transistor elements respectively corresponding to the nonvolatile memory elements are set can further reduce the defect rate. In other words, considering the possibility of defects that inevitably occur microscopically or locally as described above, there is a probability that the retained charges may leak from the nonvolatile memory element in the written state for some reason. Not 0.

However, the possibility or probability that a plurality of non-volatile elements may leak retained charges at the same time is extremely low from the viewpoint of microscopicity of defects such as semiconductor crystals and gate insulating films and their locality or randomness. It is good to be understood. From this point, even if the retained charge leaks from one of the nonvolatile memory elements, the series path of the plurality of read transistor elements is in a cutoff state in most cases depending on the retained charge in the other nonvolatile memory element. You can understand that there is a wait. As a result, the information storage cell for which the charge gain countermeasure is performed by the paired structure of the nonvolatile memory element and the read transistor element is also fully protected against the data retention, and the read failure rate can be further improved.

FIG. 3 is a device plan view of an embodiment of the nonvolatile memory device of FIG. In the nonvolatile memory element that can be manufactured by a manufacturing process such as the single-layer polysilicon process of this embodiment, the MOSFET whose gate electrode is a floating gate, and the floating gate of the MOSFET formed on the MOSFET have an insulating film. It is configured to have a control gate extended through it. The control gate has the same structure as a back gate in a normal MOSFET, that is, a semiconductor region into which impurities are introduced.

More specifically, as shown in the plane layout of FIG. 3, the control gate forming the nonvolatile memory element is a semiconductor region or a well region 1 of the first conductivity type such as an n-type, and the semiconductor region. A second p-type formed in the active region 4 set in the region 1
It is composed of a conductive type semiconductor region.

Although not particularly limited, the active region 4 has a rectangular pattern displayed with a dotted line in the drawing. On the active region 4, a floating gate 7, which is shaded in the drawing, is extendedly formed via a gate insulating film. In the portion of the active region 4 not covered with the floating gate 7, the second conductivity type semiconductor region is formed by an impurity introduction technique such as ion implantation of p-type impurities. The semiconductor regions in the semiconductor region 1 and the active region 4 form a control gate.

The MOSFET in which the gate electrode forming the nonvolatile memory elements PM1 and PM2 is the floating gate 7, that is, the write MOSFET is
It is formed in the active region 3 which is set in the semiconductor region 2 forming a well region of the first conductivity type. The floating gate 7 extends above the channel region of the write MOSFET through a gate insulating film, and is set on the active region 4 and in the semiconductor region 6 forming a well region of the first conductivity type. The active layer 5 is formed of a conductive layer extending over the channel region of the read MOSFET formed via the gate insulating film.

The read MOSFETs DM1 and DM2
Has its initial threshold voltage set such that the written state of the information charge on the corresponding floating gate can be read by itself.

In the case where the semiconductor integrated circuit device has a structure mainly composed of a logic circuit and a memory circuit as will be described later with reference to FIG. 6, a p-channel type MOS forming the same is formed.
Most of FETs and n-channel MOSFETs are composed of enhancement mode MOSFETs so that they can be clearly turned on and off with respect to signals in the operating power supply voltage range.

On the other hand, the read MOSFET
Is desired to be a depletion mode MOSFET, referring to the characteristic curve of FIG.
Therefore, in order to appropriately set the initial threshold voltage of the read MOSFET, a mask made of a photoresist mask having a pattern corresponding to the semiconductor region 6 is set. The impurity concentration of the channel region of the read MOSFET is adjusted by selectively introducing the second conductivity type impurity using such a mask as a mask for implanting impurity ions.

Two read MOSFETs and read switch MOSFETs or read select MOSFETs
Are formed in the active region 5 having an L-shaped pattern shown by a dotted line in FIG. The floating gates 7, 7
Extends over the active region 5 through the gate insulating film and serves as the gate electrode of the read MOSFET. The gate electrode of the read selection MOSFET is integrally formed with the read word line RWL extending in the horizontal direction in the drawing, and is composed of the conductive layer 8 made of the same layer as the floating gate.

Wiring according to the so-called multilayer metal wiring technique is applied to each of the illustrated structures. In the figure, a square pattern 9 marked with an X is a contact hole pattern provided in an insulating film such as an interlayer insulating film or an insulating layer, and 10 is a first metal wiring layer (M
1) and 11 are patterns of the second metal wiring layer (M2), and 12 is a pattern of the third metal wiring layer (M3). The write word line PWL connected to the control gate of the nonvolatile memory element and the source line Vs connected to the source regions of the write MIS transistor and the read MOSFET.
s is composed of the first metal wiring layer, and the write data line P
DL is formed of the second metal wiring layer, and the read data line R
DL is composed of a third metal wiring layer.

The description will be continued for a better understanding of the wiring configuration. A contact hole 9 is set in the semiconductor region in the active region 4, and a write word line PWL formed of a first metal wiring layer 10 extending in the lateral direction of the drawing through the contact hole 9. Are electrically contacted. The metal wiring layer 10 is electrically contacted with the semiconductor region 1 through a contact hole in a portion (not shown).

The common semiconductor region of the two write MOSFETs, that is, the portion of the active region 3 located between the two floating gates 7 and 7,
The source line Vss, which is the first-layer metal wiring 10, is electrically contacted through the contact hole 9. Although not particularly limited,
The metal wiring layer 10 forming the source line Vss has a pattern which extends on the read MOSFET mainly in the lateral direction of the drawing and has a branch portion which makes contact with the common semiconductor region of the write MOSFET. To be done. In the two semiconductor regions corresponding to the common semiconductor region of the write MOSFET, the second layer metal wiring layer 1 forming the write data line PDL extending in the vertical direction of the drawing is formed.
1 is electrically contacted through the contact hole 9.

FIG. 4 shows a cross section taken along the line AA 'in FIG. 3, and FIG. 5 shows a cross section taken along the line BB' in FIG. A semiconductor region 22 of the second conductivity type and a semiconductor region 23 of the first conductivity type, which function as a control gate of the nonvolatile memory element, are formed on the main surface portion of the semiconductor substrate 21 of the first conductivity type. An element isolation region 24 made of silicon oxide is formed in the first conductivity type semiconductor region 23. A portion of the semiconductor region 23 separated by the element isolation region 24 is a MOSFET region.
In the semiconductor region 23, a write MOSFET of a nonvolatile memory element having a gate insulating film 26 is formed, and a gate insulating film 26 and a second conductivity type impurity layer 25 for adjusting an initial threshold voltage are provided. Read MOSF
ET is formed.

A floating gate 27 is disposed above the second conductive type semiconductor region 22, the write MOSFET region, and the read MOSFET region via a gate insulating film 26, and the surface of the second conductive type semiconductor region 22. A second conductivity type semiconductor layer 31 and a first conductivity type semiconductor layer 32 are formed in the region. On the surfaces of the floating gate 27, the second conductive type semiconductor layer 31 and the first conductive type semiconductor layer 32, a metal that works effectively in improving the contact with the wiring layer and reducing the equivalent resistance. A silicide layer 29 is formed. Insulating side spacers 30 are set around the floating gate 27. On the semiconductor substrate 21, the first interlayer insulating film 33, the first metal wiring layer 34, and the second interlayer insulating film 3 are also provided.
5, the second metal wiring layer 36, the third interlayer insulating film 37, and the third metal wiring layer 38 are formed.

FIG. 6 shows a block diagram of an embodiment of a semiconductor integrated circuit device to which the present invention is applied. The semiconductor integrated circuit device of this embodiment is directed to a system LSI, although not particularly limited thereto. A plurality of external connection electrodes (not shown) such as a large number of bonding pads are arranged on the periphery of the semiconductor substrate on which the semiconductor integrated circuit device is formed,
An external input / output circuit IO is provided inside thereof. The external input / output circuit IO also includes an analog input / output circuit. Although not particularly limited, the semiconductor integrated circuit device uses an external power supply having a relatively high level such as 3.3 V as an operating power supply.
In the semiconductor integrated circuit device, an internal circuit as described later has a relatively small internal power supply voltage such as 1.8V so that it can operate at a relatively high speed with a relatively small power consumption. To work with.

A level shifter (not shown) is provided on the internal circuit side of the external input / output circuit IO. The level shifter converts an external input signal corresponding to 3.3V into a signal level corresponding to an internal power supply voltage such as 1.8V, or a signal such as 1.8V formed by an internal circuit. It is converted into a signal like 3.3V corresponding to the external output signal. Power supply circuit
Forms an internal power source such as 1.8 V by lowering the external power source such as 3.3 V.

As internal circuits, a dynamic random access memory (DRAM), a central processing unit (C
PU), static random access memory (SRAM) 32 used as cache memory, etc.
7. Read-only memory (ROM) for storing programs and fixed information, logic circuit (LOGIC), analog-digital conversion circuit (ADC), and digital memory
It includes an analog conversion circuit (DAC) or a user logic. In this example,
Although not particularly limited, an electrically erasable and writable non-volatile memory (ie Flash) is used as the relief program element of the SRAM.

As described above, the DRAM is operated using the internal power supply voltage such as 1.8V as the operating power supply. However, it also includes a circuit that is operated at a high voltage such as a boosted internal power supply voltage for word line selection. Non-volatile memory (ieFl
In the ash), the data read operation is performed using the internal power supply voltage, whereas the erase / write operation requires a high voltage. The high voltage applied to the non-volatile memory may be formed by providing an internal booster circuit, but since it is used only for defect relief, a predetermined voltage such as the EPROM writer mode of the system LSI described later is used. In the above operation mode, the power may be supplied from the outside through a predetermined external connection electrode.
In such a case, it is possible to avoid increasing the chip area for forming the booster circuit.

The non-volatile memory (ieFlash) may be used for storing relief information (control information for replacing defective memory cells with redundant memory cells) in the DRAM 325 in addition to the DRAM in addition to the SRAM. It may be used as an alternative to a power supply circuit or a fuse that stores resistance trimming information of A / D and D / A.

Although not particularly limited, the system LSI has a complementary MOSFET (insulated gate field effect transistor) formed on one semiconductor substrate such as single crystal silicon by a single layer polysilicon gate process. System LSI is designed for more suitable operation.
There are two types of gate insulating film thickness for the MOSFET. When the system LSI is configured by a fine processing technology such as a 0.2 μm process technology, external input / output circuits (including analog input / output circuits) IO, DRAM, nonvolatile memory (ieFlash), A / D, and D The MOSFET at / A has a gate length of 0.4 μm, and a gate insulating film made of silicon oxide, that is, a gate oxide film having a relatively large thickness of 8 nm is a MOSF.
Composed of ET.

This is desirable in order to improve the information retention performance of the flash memory by setting a relatively thick film thickness in the tunnel oxide film composed of the gate oxide film, and in addition to the operating voltage of the MOSFET. This is because it is necessary to secure a certain breakdown voltage (breakdown voltage against breakdown of the gate oxide film). 0.18 μm or 0.15
Under the minimum processing dimension of μm, the gate oxide film thickness of about 6.5 nm can be considered.

On the other hand, a circuit which uses a stepped-down relatively low internal voltage as an operating power supply, that is, a logic (LOGI
The circuit C, the SRAM, and the CPU are composed of MOSFETs having a gate length of 0.2 μm and a gate oxide film thickness of 4 nm, which is relatively single channel and has a thin gate insulating film thickness. The level shift circuit has MOSFETs having both gate oxide film thicknesses corresponding to the voltage level of the level shift. The gate electrodes of the MOSFETs having different gate oxide film thicknesses are composed of polysilicon layers having the same film thickness.

The above-mentioned gate oxide film is formed by using a gate oxide film forming technique using the same photomask for the same film thickness, and the polysilicon gate for the same film is formed by the same photomask. It can be produced using a molding technique that utilizes a mask. As described above, by making the gate oxide film thickness of the nonvolatile memory element having the single-layer gate structure common to the gate oxide film thickness of the MOSFETs of other circuits, priority is given not to complicate the system LSI manufacturing process. As a result, the nonvolatile memory element of the flash memory can have a certain amount of information retention performance.

FIG. 7 shows a circuit diagram of an embodiment of the unit information cell used in the relief program element of the present invention. The unit information cell of this embodiment includes a memory cell section 387 and a write / read control circuit 388. The memory cell unit 387 includes a nonvolatile storage element PM1 including a MOS capacitance element PM1b and a MOSFET PM1a, and a MOS capacitance element PM2, as in FIG.
It has a non-volatile memory element PM2 constituted by b and MOSFET PM2a.

In this embodiment, the read MOSFET D
M1 and DM2 are composed of enhancement types.
The control gate cg is provided to enable the enhancement mode of the MOSFETs DM1 and DM2.
Unlike the write word line PWL of the embodiment shown in FIG. 1, a potential or signal of a predetermined selection level is applied when reading data.

The MOSFETs DM1 and DM2 have different voltage-current characteristics with respect to the control gate cg depending on the writing state and the erasing state of the corresponding nonvolatile memory element. Therefore, the control gate cg prevents current from flowing through the read MOSFET when the stored information is “1”, in other words, in the written state, and when the stored information is “0”, that is, in the erased state, the MOS transistor is turned off.
The potential is set so that a current flows through the FET.

The potential of the floating gate in the non-volatile memory element depends on the storage state of information in the floating gate and the magnitude of capacitive coupling by the MOS capacitance elements PM1b and PM2b to the floating gate. Therefore, the control gate potential vs. drain current in the read MOSFET can be set also by setting the capacitance values of the MOS capacitance elements PM1b and PM2b.

The drain of the read MOSFET DM2 is coupled to the control node pu through the n-channel type MOSFETs TR3 and TR4, and the MOSFET TR3.
The potential of the coupling node of TR4 and TR4 is applied to the write / read control circuit 388 as the output rl. The MOSFET
PM1a and PM2a are n-channel MOSFETs, respectively
It is coupled to the control node wl via TR1 and TR2.
The gate electrodes of the MOSFETs TR1 to TR4 are biased by the power supply voltage. cg corresponds to the control gate, and sl corresponds to the source line.

In the data write operation, a voltage of a write level such as 5V is applied to the terminals sl and cg, and the terminal wl is set to a reference potential level such as 0V to make the nonvolatile memory element P.
M1a and PM2a are turned on, and hot electrons are injected from the terminal sl to the floating gate. In the erase operation, 5 V is applied only to the terminal sl, and electrons are emitted from the floating gate by tunnel emission.

In the read operation, a read potential such as 1.5 V is applied to the terminal pu, and a read selection level such as 1.5 V is applied to the terminal cg. This makes MO
The SFETs DM1 and DM2 operate in the switch state or mutual conductance state of the MOSFETs DM1 and DM2 depending on the accumulated charge in the floating gate. The potential of the terminal rl, which is determined accordingly,
That is, the read data is held in the latch circuit at the subsequent stage.

In the read operation, the nonvolatile memory elements PM1a and PM2a have their source electrode (sl) and drain electrode (wl) both fixed at 0V,
The source-to-source current is prevented. As a result, similar to the above-described embodiment, the MOSFET PM1 that undesirably changes the charge amount of the floating gate.
a, generation of weak hot electrons in PM2a is avoided. It may be feared that weak MOSFET hot electrons are generated according to the read current of the read MOSFETs DM1 and DM2, which adversely affects the charge of the floating gate.

However, it may be understood that the injection of such hot electrons into the floating gate is substantially negligible. That is, MOSFE
The TTR4, TR3, DM2, and DM1 may be vertically stacked or connected in series in that order, and the drain voltage of the read MOSFETs DM1 and DM2 is
This is because the voltage is a minute voltage equal to or lower than the voltage of the terminal pu (1.5 V), and the control voltage level of the terminal cg at the time of reading is as low as 1.5 V. Therefore, it is not necessary to consider deterioration of stored charges in the nonvolatile memory elements PM1 and PM2 due to the read operation, and high reliability can be realized.

FIG. 8 is a flow chart for explaining one embodiment of the method of manufacturing a semiconductor integrated circuit device according to the present invention. In this embodiment, a semiconductor integrated circuit device such as a system LSI is directed to a test operation after it is completed on a semiconductor wafer. FIG. 6
A plurality of semiconductor integrated circuit devices as shown in FIG. 1 are manufactured in a grid pattern on a semiconductor wafer by a known semiconductor integrated circuit manufacturing technique.

FIG. 8 shows two test methods. One is a test method for a semiconductor integrated circuit device product development or a first lot for mass production after product development is completed. In the probe test (1), function tests such as writing / erasing / reading, AC, DC
Perform a test and get information about good and bad products. At this time, at the end of the probe test, the ieFlash as the relief program element is set in a writing state in which charges are injected into the floating gate.

In the baking process, the semiconductor wafer is moved to a constant temperature bath for the baking process and left at a high temperature (baking process) so as to accelerate the failure occurrence time due to the retention.
This bake treatment is a high temperature exposure for revealing a potential defect that has not yet become a defect but progresses to a defect. In order to sufficiently achieve the purpose, the bake process is a finished product, that is, a semiconductor integrated circuit device as a plurality of semiconductor chips is formed from a semiconductor wafer by a semiconductor wafer dividing technique, and each semiconductor chip is called a lead or bump electrode. It is considered that a temperature and a time that are sufficiently higher than the allowable operating temperature of the product to be completed by setting an appropriate external terminal as described above and sealing with a sealing material made of resin are appropriate. It

The allowable operating temperature of the resin-sealed type completed semiconductor integrated circuit device is generally about 150 ° C., while an appropriate baking process is performed at a high temperature such as 250 ° C. The conditions are such that it is left for about 5 hours.
The upper limit of the temperature of the baking process is set to a value that does not cause essential damage such as melting, deformation, alteration, etc. in the components such as the wiring layer and the insulating layer of the semiconductor integrated circuit device which should be good in the state of the semiconductor wafer. It is what is done.

In the probe test (2), the semiconductor wafer is moved to a stage on a tester to test each semiconductor integrated circuit device. The probe test (2) includes a so-called retention test. As a result, the defective data retention product generated by the baking process is tested. The probe test (1) and the probe test (2)
The test information obtained in step 1 is used later as information for selectively obtaining non-defective semiconductor chips when the semiconductor wafer is made into semiconductor chips as individual semiconductor integrated circuit devices by a dividing technique such as a dicing technique. .

For the semiconductor integrated circuit device other than the above product development or the first lot, as described above, the highly reliable IEFlas is realized by making 1 bit into 2 cells.
Taking advantage of the feature of h, only the probe test (1) is performed, and the baking step and the subsequent probe test (2) are deleted.

FIG. 9 is a conceptual diagram for explaining a method of manufacturing the semiconductor integrated circuit device shown in FIG.
In the probe test (1) and (2), a tester and a wafer prober are used to supply the operating voltage to the electrodes of the semiconductor chip formed on the semiconductor wafer by the probe and to extract the signal input and the corresponding output signal. Various electrical tests including writing / reading / erasing as described above are performed. On the other hand, in the baking process, the semiconductor wafer is transferred from the wafer prober to a constant temperature bath and left at a high temperature for several hours as described above.

In FIG. 8, only the product development and the first lot are tested by the procedure as shown in FIG. 9, while the other mass-produced products are subjected to the above baking and the probe test ( 2) is omitted. Therefore, since the semiconductor device can be manufactured in the same manner as the test operation of a general semiconductor integrated circuit device, the reliability of the program element is ensured and the manufacturing efficiency is improved while taking advantage of the above-mentioned easy-to-use manufacturing and structure-friendly IEFlash. Can be realized.

FIG. 10 shows a flowchart of an embodiment of the probe test of the SRAM shown in FIG. This flowchart comprises steps (1) to (6). In the first step (1), the SRAM
A test is carried out, and in the case of a defect, it is judged in step (2) whether repair is possible, and the non-repairable product is removed. In step (3), writing, reading, and erasing tests of ieFlash are performed to remove defective margin products. In step (4), the relief address data is written in the ieFlash. In step (5), the relief data is read and defective products that are not written correctly are removed. In step (6), a SRAM test is performed to remove defective products that could not be repaired. In this way, ieFlas
The SRAM repaired by h is regarded as a good product.

FIG. 11 is a block diagram of another embodiment of the fuse circuit mounted on the semiconductor integrated circuit device to which the present invention is applied. In this embodiment, one ieFlash cell is used as the fuse. In order to ensure reliability when using one such cell,
An ECC circuit is used. For example, a circuit for storing a 7-bit rescue address with 7 fuses is used.
When providing a set, 35 bits of information are stored as a whole. A 7-bit parity bit for error detection and correction is added to this 35-bit storage information, and this is input to the ECC circuit for error correction.
Obtain a 5-bit data output. The 35-bit data is divided into 5 sets and used as a rescue address.

FIG. 12 is a block diagram showing still another embodiment of the fuse circuit mounted on the semiconductor integrated circuit device to which the present invention is applied. In this embodiment, as shown in FIG. 11, the fuse is made to have 2 cells of 1 bit as in the embodiment of FIG. 1 to enhance the reliability of the memory cell itself, and to secure higher reliability. ECC like
Circuit is used.

FIG. 13 is a block diagram of an embodiment of the fuse circuit shown in FIG. 11 or 12. The fuse module shown in the figure has five nonvolatile storage blocks (7bFile # 0) as a nonvolatile information storage cell group.
~ 7bFile # 4) non-volatile memory 380,
A Hamming code generator 381 that generates a Hamming code for the 35-bit data q0-34 output from the nonvolatile memory 380, and a nonvolatile storage block (7bFile # 5) that stores the Hamming code generated by the Hamming code generator 381. ) Is included. These non-volatile memory 38
0 and 382 may have a 1-bit 1-cell configuration as shown in FIG. 11 or a 1-bit 2-cell configuration as shown in FIG.

Receiving the Hamming code output from the non-volatile memory block 382 and the 35-bit data q0-34 output from the non-volatile memory 380,
An error correction circuit 383 and a control circuit 384 that can perform error correction on input data are provided. The write data for the non-volatile memory 380 is externally provided as d0-6. The output of error correction circuit 383 is shown as qc0-34. Controller 38
4 is a nonvolatile storage block 7bFile # 0 to 7bF.
Address signal a0-2 for selecting ile # 4, read operation instruction signal rd, write operation instruction signal pr
g is input.

As in the embodiment of FIG. 12, one bit is composed of two memory cells and the same data is written, so that even if there is a defect in the oxide film of one memory cell, the other one is normal. Data can be read out, so 2-3
The digit defect rate can be improved. Further, even if both cells become defective, the defective data can be corrected by the ECC circuit at the next stage. In the above-described embodiment, the ECC circuit for single-bit error correction is used in which the data word is 35 bits and the redundant word is 7 bits. This improves the defect rate by four digits. Therefore, the total combination is improved by 6 to 7 digits, and the baking process and the retention evaluation can be deleted (omitted) according to the flow of FIG. 8 by this high reliability. Even if one bit is composed of one memory cell, the defect rate can be improved by four digits by combining an ECC circuit. Therefore, the defect rate is improved more than when one bit is composed of two memory cells. Can be made.

Further, as described above, the Hamming code generator 381, the non-volatile memory 382, the error correction circuit 38.
3 implements an ECC circuit, it is assumed that the nonvolatile storage block 7bFile # 0-7b of the nonvolatile memory 380 is temporarily stored.
Even if a read failure occurs in the data read from File # 4, the error is automatically corrected, and thus the read failure rate can be ultimately reduced.

To guarantee the error correction function by such an ECC circuit, the nonvolatile memories 380 and 382 are required.
In the non-volatile storage block 7bFile # 0-7
The program circuit for writing to bFile # 4 and 7bFile # 5 has nonvolatile storage blocks 7bFile # 0 to 7bFile # 4, when the ECC circuit is enabled.
It has an operation mode in which writing to 7bFile # 5 is prohibited. For example, although not shown, a 1-bit non-volatile flag indicating completion / non-completion of writing is set in the non-volatile memory 380.
When the nonvolatile flag is set to the set state under the control of the controller 384, the operation mode for prohibiting the writing is specified to the program circuit. Since this 1-bit non-volatile flag is not applicable to the ECC circuit, it may be configured with 3 bits in order to improve the defective rate of the flag, and the same value may be set to the 3 bits.

FIG. 14 shows E shown in FIGS.
A flow chart diagram of an embodiment of an SRAM probe test when a relief program element is configured using a CC circuit is shown. This flowchart comprises steps (1) to (7). The process up to step (5) is the same as in FIG. 10, and in the first step (1), SR
An AM test is performed, and if defective, it is determined in step (2) whether or not repair is possible, and non-repairable products are removed.

In step (3), writing, reading and erasing tests of ieFlash are carried out to remove defective margin products. In step (4), relief address data is written in the ieFlash. In step (5), the relief data is read and defective products that are not written correctly are removed. In step (6), the ECC circuit is set to validate the operation of the ECC circuit. In step (7), an SRAM test is performed to remove defective products that could not be repaired. In this way, ieFlash
And the SRAM rescued by the ECC circuit is regarded as a good product.

In the electrically rewritable non-volatile memory having a single-layer gate structure as described above, the same data is stored in two or more memory cells, or defective data is corrected by an ECC circuit, or both are combined. By doing so, we aim to achieve high reliability. In a test process of a semiconductor integrated circuit device equipped with a nonvolatile memory circuit that realizes such high reliability, high temperature storage processing and data retention evaluation are deleted to reduce the number of steps. However, at the time of product development and in the first lot of products, high-temperature storage treatment and data retention evaluation are performed to confirm that process variations are within the manufacturing compensation range.

By constructing one bit by a plurality of cells of two or more cells as described above, even if any one of the cells becomes defective, if one is normal, it becomes a non-defective product and the defective rate is reduced, and the reliability is improved. it can. The ECC circuit is a circuit that detects and corrects the destroyed data when the stored data is destroyed, so that the reliability is improved. Furthermore, the reliability can be further improved by combining both types.

Due to this improvement in reliability, the retention evaluation which is carried out in the conventional process can be omitted, and the baking process for this purpose is not necessary, and a significant reduction in test man-hours can be realized. In the assembly process, both temperature and time are insufficient for retention evaluation as compared with the baking process, but a high temperature process such as burn-in test or aging in a normal semiconductor integrated circuit device is included. High-temperature treatment such as burn-in test or aging does not require the use of a constant temperature bath as described above, and therefore does not require transportation, which causes an extraordinary high cost like the baking process. is not.

Although the invention made by the present inventor has been concretely described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. Various embodiments can be adopted as a specific configuration of the non-volatile memory having a single-layer gate structure. One bit may be composed of three or more cells, and the write / read circuit for that purpose can adopt various embodiments. INDUSTRIAL APPLICABILITY The present invention can be applied to various semiconductor products equipped with an electrically rewritable non-volatile semiconductor memory having a single-layer gate structure, and can also be used for encryption codes, resistance value trimming, etc. in addition to the above-mentioned rescue address storage. Is.

[0086]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. A parity bit for performing error detection and correction generated corresponding to storage information stored in a plurality of first storage circuits including a non-volatile storage element having a single-layer gate structure has a configuration similar to that of the first storage circuit. A semiconductor integrated circuit device, which is stored in a plurality of two storage circuits and has an error detection / correction circuit that performs error correction of the storage information of the first storage circuit based on the storage information, is formed on the wafer, and is formed on the wafer. In a test step of conducting an electrical test of the formed semiconductor integrated circuit device, the semiconductor integrated circuit device is placed in a constant temperature bath with predetermined write information stored in the first memory circuit and the second memory circuit. By applying a high temperature for a certain period of time and then omitting the high temperature test of testing the holding state of the above stored information, the manufacturing efficiency is improved while maintaining the high reliability of the nonvolatile memory element. It can be.

1-bit storage information is stored in each of a plurality of non-volatile storage elements having a single-layer gate structure, and a signal transmission means for extracting a logical sum signal of the storage information is included.
In a test step of forming a semiconductor integrated circuit device having a plurality of memory circuits on a wafer and performing an electrical test of the semiconductor integrated circuit device formed on the wafer, a predetermined write operation is performed on the first memory circuit. With the information stored,
While maintaining the high reliability of the non-volatile memory element, the semiconductor integrated circuit device is subjected to a high temperature for a certain period of time in a constant temperature bath, and then the high temperature test of testing the holding state of the stored information is omitted. , The manufacturing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a memory cell as an information storage cell mounted in a semiconductor integrated circuit device to which the present invention is applied.

FIG. 2 is a voltage-current characteristic diagram of read MOSFETs DM1 and DM2 in FIG.

3 is a device plan view showing an embodiment of the nonvolatile memory device of FIG. 1. FIG.

FIG. 4 is a structural view of an A-A ′ cross-section device in FIG. 3;

FIG. 5 is a B-B ′ cross-section element structure view in FIG. 3;

FIG. 6 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied.

FIG. 7 is a circuit diagram showing an embodiment of a unit information cell using a relief program element used in the present invention.

FIG. 8 is a flow chart for explaining one embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

9 is a conceptual diagram for explaining a method of manufacturing the semiconductor integrated circuit device shown in FIG.

10 is a flow chart diagram of an embodiment of a probe test of the SRAM shown in FIG.

FIG. 11 is a block diagram showing another embodiment of a fuse circuit mounted on a semiconductor integrated circuit device to which the present invention is applied.

FIG. 12 is a block diagram showing still another embodiment of the fuse circuit mounted on the semiconductor integrated circuit device to which the present invention is applied.

13 is a block diagram of an embodiment of the fuse circuit of FIG. 11 or FIG.

FIG. 14 is a flow chart diagram showing an example of a probe test of an SRAM when a relief program element is configured by using the ECC circuit shown in FIGS.

[Explanation of symbols]

PM1, PM2 ... Non-volatile storage element, DM1, DM2 ...
Read MOSFET, SM ... Selection MOSFET, RD
L ... Read data line, PDL ... Write data line, RW
L ... Read word line, PWL ... Write word line, Vf
… Floating gate, Vss… Source line, 380…
Non-volatile memory, 7bFile # 0 to 7bFile # 5
... Nonvolatile storage block, 381 ... Hamming code generator, 382 ... Nonvolatile memory, 383 ... Error correction circuit, 384 ... Controller, PM1a, PM2a ...
Nonvolatile memory element configuration MOSFET, PM1b, PM
2b MOS capacitive element for non-volatile memory element configuration, cg ...
Control gate, sl ... Source line.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshio Yamada             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Tetsuya Muratani             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Koichi Toba             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 2G132 AA08 AA13 AB14 AK00 AK07                       AL12                 5F038 AV08 AV15 BG03 BG08 DF01                       DF03 DF04 DF05 DT08 DT10                       DT14 EZ20                 5L106 AA10 BB12 CC09 DD25 EE07                       FF04 FF05 GG05

Claims (16)

[Claims] 1. A step of preparing a semiconductor wafer, which is to be subsequently divided into individual chips and on which a plurality of semiconductor integrated circuit devices to be completed in a required mounting form are formed, the method comprising the steps of: The device has a plurality of nonvolatile memory elements each having a floating gate electrode to which information charges are applied, and having different threshold voltage characteristics according to the information charges of the floating gate electrodes, and the plurality of nonvolatile memory elements. And an error correction circuit for reading out a plurality of bits of stored information from the same and an error correction circuit for receiving a part of the plurality of bits of stored information as an information bit and another part as an error correction code bit The semiconductor wafer does not need to be baked at a relatively high temperature exceeding the allowable operating temperature of the finished product. The method of manufacturing a semiconductor integrated circuit device which is characterized in that what is. 2. The information read circuit according to claim 1, wherein the information read circuit is provided corresponding to the plurality of nonvolatile memory elements, and a gate electrode is coupled to the floating gate electrode of the corresponding nonvolatile memory element. A plurality of read MOSFETs and the read M
A plurality of storage circuits including a signal transmission means formed by an OSFET, wherein the error correction circuit receives a plurality of bits of storage information from the plurality of storage circuits and an error correction code bit and performs error correction. A method for manufacturing a semiconductor integrated circuit device, comprising: 3. The semiconductor integrated circuit device according to claim 2, wherein each of the semiconductor integrated circuit devices has a potential that suppresses a potential applied to the electrodes of the plurality of nonvolatile memory elements during a period other than a circuit operation that changes the charge amount of the floating gate electrode. A method of manufacturing a semiconductor integrated circuit device, comprising a suppressing circuit. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, further comprising a test step of performing an electrical test of the semiconductor integrated circuit device formed on the wafer. 5. The non-volatile memory element according to claim 2, wherein the non-volatile memory element is a non-volatile memory element having a single-layer gate structure, and the read MOSFET is a depletion type MOS.
A method for manufacturing a semiconductor integrated circuit device, which is an FET. 6. A step of preparing a semiconductor wafer on which a plurality of semiconductor integrated circuit devices, each of which is to be divided into individual chips and which is to be a finished product in a required mounting form, is prepared, and the plurality of semiconductor integrated circuits are provided. The device has a plurality of non-volatile memory elements each having a floating gate electrode to which information charges are applied and configured to have different threshold voltage characteristics according to the information charges of the floating gate electrodes,
An information read circuit for reading a plurality of bits of stored information from the plurality of nonvolatile storage elements, the information read circuit has a plurality of logic circuits, and each of the plurality of logic circuits has a plurality of logic circuits. , A logic synthesis output corresponding to a plurality of pieces of information from a plurality of nonvolatile storage elements is output as read information, and the semiconductor wafer is baked at a relatively high temperature exceeding the operation allowable temperature of the finished product. A method for manufacturing a semiconductor integrated circuit device, wherein application of processing is omitted. 7. The information read circuit according to claim 6, further comprising a plurality of storage circuits including means for transmitting signals generated by the plurality of logic circuits, wherein each of the logic circuits includes the plurality of nonvolatile storages. A plurality of read MOSFETs provided corresponding to the elements, the gate electrodes of which are coupled to the floating gate electrodes of the corresponding non-volatile memory elements, and which are coupled to each other to form the logic synthesis output. A method of manufacturing a semiconductor integrated circuit device, comprising: 8. The semiconductor integrated circuit device according to claim 6, wherein each of the semiconductor integrated circuit devices has a potential that suppresses a potential applied to the electrodes of the plurality of nonvolatile memory elements during a period other than a circuit operation that changes a charge amount of the floating gate electrode. A method of manufacturing a semiconductor integrated circuit device, comprising a suppressing circuit. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising a test step of performing an electrical test of the semiconductor integrated circuit device formed on the wafer. 10. The semiconductor integrated circuit device according to claim 7, wherein a part of the storage information of a plurality of bits from the plurality of storage circuits is used as an information bit, and the other part is received as an error correction code bit. A method of manufacturing a semiconductor integrated circuit device, further comprising an error correction circuit for performing error correction. 11. The non-volatile memory element according to claim 7, wherein the non-volatile memory element is a non-volatile memory element having a single-layer gate structure, and the read MOSFET is a depletion type MOS.
A method for manufacturing a semiconductor integrated circuit device, which is an FET. 12. The non-volatile memory element according to claim 10, wherein the non-volatile memory element has a single-layer gate structure, and the read MOSFET is a depletion type MOS.
A method for manufacturing a semiconductor integrated circuit device, which is an FET. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the memory circuit includes repair information for the circuit to be repaired as stored information thereof. 14. The repaired circuit according to claim 13, wherein the repaired circuit is an SRA mounted on a system LSI.
A method for manufacturing a semiconductor integrated circuit device, which is an M circuit. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device performs the bake treatment on all or part of a developed product. 16. The semiconductor integrated circuit device according to claim 7, wherein the high temperature test is performed on all or part of a first lot to be mass-produced. Manufacturing method.