WO2007072580A1

WO2007072580A1 - Memory-redundancy selecting device, memory device, information processing device, and method of selecting redundancy of memory cell

Info

Publication number: WO2007072580A1
Application number: PCT/JP2006/303153
Authority: WO
Inventors: Masato Susuki; Hiroshi Nakadai
Original assignee: Fujitsu Limited
Priority date: 2005-12-19
Filing date: 2006-02-22
Publication date: 2007-06-28
Also published as: JP2007172690A

Abstract

A memory-redundancy selecting device comprises redundant setting latches (51-5n) to hold beforehand redundancy-selecting signals corresponding to redundant sets indicative of replacing patterns of memory cell groups, a redundancy decode circuit (21) to derive the same redundant sets as those corresponding to the redundancy-selecting signals before the signals are reversed even when the redundancy selecting signals are input and a part of them is reversed, and a redundant switch circuit (22) to replace the memory cell groups based on derived redundancy sets.

Description

Specification

Memory redundancy selection device, storage device, information processing device, and memory cell redundancy selection method

Technical field

The present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell for performing redundancy selection in which a defective memory cell is replaced with a redundant memory cell in a semiconductor storage device such as a RAM built in an LSI such as a processor In particular, the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell redundancy selection method that can improve soft error tolerance in redundancy selection.

Background art

Conventionally, a processor incorporating a semiconductor memory device such as a RAM as a cache memory has a spare memory cell called a redundant memory cell in preparation for a manufacturing failure in an LSI such as a DSP (Digital Signal Processor) or SOC (System On Chip). Technology to relieve defective memory cells by replacing defective memory cells and redundant memory cells when defective memory cells are detected in tests prior to shipment. In the following, this is called redundancy selection).

[0003] As a method for replacing this defective memory cell, the address indicated by the defective memory cell is set by switching a memory cell by setting an address of the defective memory cell by cutting a fuse arranged on a semiconductor chip. A technique for switching a memory cell to a redundant memory cell has been devised (for example, see Patent Document 1) o

In this way, when a memory cell is replaced using a signal for replacing a defective memory cell with a redundant memory cell (hereinafter referred to as a redundant selection signal), this signal is sent from the fuse to the memory cell. Although it may be input directly to a circuit for replacement (hereinafter referred to as a redundancy selection circuit), it is input via a scan chain composed of scan latches arranged on the chip to avoid complicated wiring. Sometimes.

FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells. The RAM macro shown in the figure includes three memory cell groups 1 to 3 and one redundant memory cell group (reserved memory group). A memory cell is composed of a memory cell group) and a redundancy selection circuit. The memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit. Here, the redundancy selection circuit selects the memory cell group as a write destination of the write data and selects the read circuit of the memory cell group as the read destination of the read data. It consists of a redundant switch circuit that switches between redundant memory cell groups and a redundant decoding circuit that decodes redundant selection signals.

[0006] If a defective memory cell group including a defective memory cell is detected among the three memory cell groups by a test before shipment, the redundant switch circuit switches the defective memory cell group to the redundant memory cell group. Perform (redundant selection). At this time, the redundant switch circuit switches the memory cell groups in accordance with the redundant selection signal input via the redundant decoding circuit. The redundancy selection signal is held in the redundancy setting latch.

[0007] Here, in the RAM macro of the example shown in FIGS. 11 (a) and 11 (b), because there is a defective memory cell group, the! /, Shift between the three memory cell groups is replaced with a redundant memory cell group. There are four types of redundancy settings, including the case where the faulty memory cell group does not exist and the case where the replacement is not performed (redundancy is not selected).

[0008] Here, the redundancy setting is defined using a 2-bit redundancy selection signal so that four redundancy settings can be decoded by each redundancy selection signal. FIG. 12 is a diagram illustrating an example of a redundancy selection signal in the redundancy selection of a conventional memory cell. As shown in the figure, a 2-bit redundancy selection signal is set by a combination of “0” and “1”, and four redundancy settings are assigned to each.

In the example shown in FIG. 11 (a), since there is no memory cell group including a defective memory cell in memory cell groups 1 to 3, “00” is input as a redundancy selection signal. A redundancy selection signal “00” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “00”, but the redundancy switch circuit does not switch to the redundancy memory cell group.

[0010] Further, in the example shown in FIG. 11B, the memory cell group 2 is a defective memory cell. Then, “10” is input as the redundancy selection signal. A redundancy selection signal “1 0” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “10”, and the redundancy switch circuit switches to the redundancy memory cell group.

FIG. 13 is a diagram illustrating an example of a conventional redundancy selection circuit. FIG. 2A shows an example of a redundant switch circuit, and FIG. 2B shows an example of a redundant decode circuit. FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG.

[0012] As shown in FIG. 13 (b), the redundant decoding circuit includes two inverter circuits, three AND circuits, and two OR circuit forces. This redundant decode circuit outputs 3-bit redundant decode signals SEL0 to SEL2, which are select signals for the redundant switch circuit, as shown in FIG. 14, in response to 2-bit redundant selection signals RED0 to RED1.

In addition, as shown in FIG. 13 (a), the redundant switch circuit is configured by a combination of three sets of AND-OR equivalent circuits configured by a combination circuit of three NAND circuits. This redundant switch circuit includes memory cell groups ARRAY0 to ARRAY2 and redundant memory cell group ARRAYR as shown in FIG. Switches the connection with OUT0 to OUT2.

Patent Document 1: Japanese Patent Application Laid-Open No. 2005-149667

Disclosure of the invention

Problems to be solved by the invention

However, in the redundancy selection of the memory cell described above, a soft error occurred in the redundancy selection signal held in the latch due to the influence of a-line (helium (He) nucleus) falling from the universe to the earth. In this case, that is, when the setting value of the redundancy selection signal is inverted in bit units, there is a problem that the redundancy selection of the memory cell is not performed correctly.

[0016] The present invention has been made to solve the above-described problems caused by the prior art, and an object thereof is to provide a redundancy selection device and a redundancy selection method that can improve soft error resistance in redundancy selection. And

Means for solving the problem In order to solve the above-described problems and achieve the object, the redundancy selection device of the present invention is connected to a memory cell and a redundancy memory cell constituting a storage device, and the memory cell or the redundancy memory cell A redundancy selection device for performing redundancy selection for selecting any one of input and output, the redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell, and held in the redundancy selection information holding means A redundant decoding means for inputting the redundant selection signal and outputting the same redundant setting as a decoding result even when part of the redundant selection signal is inverted, based on the decoding result; And redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.

[0018] Further, the redundant selection signal holding means in the redundant selection device of the present invention is characterized by comprising a scan latch means.

[0019] Further, the redundancy decoding means in the redundancy selection device of the present invention associates at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result when decoding the redundancy selection signal. It is characterized by being configured.

[0020] Further, the redundancy selection signal in the redundancy selection device of the present invention is composed of n bits (n> 1), and the redundancy decoding means includes k bits (0 <k) of the n bits constituting the redundancy selection signal. Even when ≤n—1) is inverted, the same redundancy setting as before the inversion is output as a decoding result.

In addition, the memory device of the present invention is connected to the memory cell, the redundant memory cell, the memory cell and the redundant memory cell, and selects either the memory cell or the redundant memory cell. Redundancy selection means for performing redundancy selection, and the redundancy selection means is held in a redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell and in the redundancy selection information holding means. In addition, when the redundant selection signal is input and a part of the redundant selection signal is inverted, redundant decoding means for outputting the same redundancy setting as before decoding as a decoding result, and based on the decoding result And redundant switch means for selecting input / output of either the memory cell or the redundant memory cell. [0022] The information processing apparatus according to the present invention includes a memory cell, a redundant memory cell, an arithmetic processing unit connected to the storage device, the memory cell and the redundant memory cell, and the memory cell Or redundancy selection means for performing redundancy selection for selecting any input / output of the redundant memory cell, wherein the redundancy selection means holds a redundancy selection signal indicating selection information of the memory cell. When the redundancy selection signal held in the holding means and the redundancy selection information holding means is inputted, and the part of the redundancy selection signal is inverted! Redundant decoding means for outputting as a decoding result, and redundant switching means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result. The features.

[0023] Further, the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit. Latch means and fuse means connected to the scan latch means for setting a redundancy selection signal, outputting the redundancy selection signal set in the fuse means to the scan latch means, and performing the scan shift. Thus, the redundancy selection signal is held in the redundancy selection signal holding means.

[0024] Further, the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit. The redundancy selection signal holding means includes the latch means and a scan input connected to the scan latch means, and inputs the redundancy selection signal from the scan input and performs the scan shift, so that the redundancy selection signal is held in the redundancy selection signal holding means. It is characterized by holding a signal.

[0025] The redundancy selection method of the present invention is a memory cell redundancy selection method for selecting input / output of either a memory cell or a redundant memory cell constituting a storage device, wherein the selection of the memory cell is performed. A step of holding a redundant selection signal indicating information and a case where the held redundant selection signal is input and a part of the redundant selection signal is inverted! /! The step of outputting the same redundancy setting as the decoding result even before inversion, and the selection of the input / output of either the memory cell or the redundant memory cell based on the decoding result And a step of performing.

[0026] Further, in the redundancy selection method according to the present invention, even when the retained redundancy selection signal is input and a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is performed. In the step of outputting as a decoding result, at least two or more redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.

The invention's effect

[0027] According to the present invention, the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell is held in advance, and a part of the redundancy selection signal is changed by inputting the redundancy selection signal. Even in this case, the same redundancy setting as before the change was derived, and based on the derived redundancy setting! /, The memory cell was replaced, so the redundancy selection signal held by the influence of radiation from space, etc. Even if a soft error occurs, the redundancy selection can be performed correctly, so that the soft error tolerance in the redundant selection can be improved.

[0028] Further, according to the present invention, the redundancy selection signal is composed of n bits (n> 1), and k bits (0 <k≤n—1) of n bits constituting the redundancy selection signal. Even if is reversed, it is configured to derive the same redundancy setting as that associated with the redundancy selection signal before the inversion, so that a soft error has occurred in the retained redundancy selection signal However, if k bits (0 <k≤n—1) of n bits that make up the redundancy selection signal are inverted, the redundancy selection can be performed correctly, improving the soft error tolerance in the redundancy selection. If you can!

[0029] Further, according to the present invention, k bits (0 <k≤n-1) are inverted with respect to a predetermined bit among n bits (η> 1) constituting the redundancy selection signal, In this case, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived, so that the redundancy selection signal can be determined by limiting the bits from which the same redundancy setting can be derived even if it is inverted. Even when the number of bits that can be used for the selection is limited, the soft error tolerance in redundancy selection can be improved.

[0030] Further, according to the present invention, for a specific redundancy setting, there are n signals that constitute a redundancy selection signal. Inverting up to k bits (0 <k≤n—1) in a set (n> 1), the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. As a result, it is possible to improve the resistance to soft errors in the redundant selection with a focus on the redundant setting having a high probability of being actually set among a plurality of redundant settings.

In addition, according to the present invention, with respect to the redundant setting in which the memory cell is not replaced, up to k bits (0 <k≤n—1) out of n bits (n> 1) constituting the redundancy selection signal. Even if it is inverted, it is configured to derive the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion, so there is a high probability that it will actually be set, and redundancy that does not replace the memory cell It is possible to improve the tolerance of soft errors in redundant selection with emphasis on setting!

[0032] Further, according to the present invention, even when any one bit of n bits (η> 1) constituting the redundant selection signal is inverted, it is associated with the redundant selection signal before being inverted. Since the same redundancy setting as the redundancy setting is derived, even if a soft error has occurred in the retained redundancy selection signal, one of the n bits that make up the redundancy selection signal is inverted. In such a case, since the redundant selection can be performed correctly, the soft error resistance in the redundant selection can be improved.

[0033] Further, according to the present invention, for a specific redundancy setting, even if one of the n bits (n> 1) constituting the redundancy selection signal is inverted, it is inverted. Since the redundant setting that is the same as the redundant setting associated with the redundant selection signal before the configuration is derived, the redundant setting that has a high probability of being actually set is selected among the redundant settings. There is an effect that resistance to soft errors can be improved.

Further, according to the present invention, without replacing a memory cell, one bit out of n bits (n> 1) constituting the redundancy selection signal is inverted by redundancy setting. Even if it is, the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived, so there is a high probability that it will actually be set, and the redundancy that does not replace the memory cell If you can improve the tolerance of soft errors in the redundant selection with emphasis on the setting!

Brief Description of Drawings FIG. 1 is an explanatory diagram for explaining an outline of redundancy selection according to the present embodiment.

FIG. 2 is a block diagram showing a configuration of a RAM macro according to the present embodiment.

FIG. 3 is a diagram illustrating an example of redundancy setting according to the present embodiment.

FIG. 4 is a flowchart showing an algorithm for generating the redundant selection signal shown in FIG.

FIG. 5 is a diagram showing an example of assigning two redundancy selection signals to one redundancy setting.

[FIG. 6] FIG. 6 is a flowchart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a specific redundancy setting with priority.

[FIG. 7] FIG. 7 is a diagram showing an example in which a redundancy selection signal is assigned to a specific redundancy setting.

[FIG. 8] FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in a case where 2-digit inversion data is further assigned to a specific redundancy setting.

[FIG. 9] FIG. 9 is a diagram showing an example in the case of further assigning redundant selection signals remaining in a specific redundancy setting.

FIG. 10 is a diagram showing an example of a redundancy decoding circuit with redundancy setting shown in FIG.

FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.

FIG. 12 is a diagram showing an example of a redundancy selection signal in redundancy selection of a conventional memory cell.

FIG. 13 is a diagram showing an example of a conventional redundancy selection circuit.

FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG. 13.

Explanation of symbols

[0036] 1 LSI chip

2

1-2 fuse

Five

Three

1 to 3 latch rows

m

4-4 RAM macro 5 to 5 Redundancy setting latch

1 n

6 Processor core

7 TAP controller

10 ~: LO memory cell group

13

10 Redundant memory cell group

Four

20 Redundant selection circuit

21 Redundant decoding circuit

22 Redundant switch circuit

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of a redundancy selection device and a redundancy selection method according to the present invention will be described in detail with reference to the accompanying drawings.

Example

First, an overview of redundancy selection according to the present embodiment will be described. FIG. 1 is an explanatory diagram for explaining an outline of redundant selection according to the present embodiment. The LSI chip 1 shown in the figure includes a plurality of fuses 2 to 2, a plurality of latch trains 3 to 3, a plurality of RAM macros 4 to 4, and a plurality of fuses.

A processor core unit 6 that uses 1 5 1 m I n number of RAM macros as cache memory and a TAP (Test Access Port) controller 7 that controls scan of a plurality of latch rows are arranged.

[0039] Each of the latch trains 3 to 3 includes a plurality of scan latches.

1 m

H-rows 3 to 3 are connected in a daisy chain to form a scan chain with a scan latch

1 m

is doing. Latch row 3 has fuse 2 to 2 force Latch row 3 has RAM macro 4 to 4

1 1 5 n 1 n are connected to each other. Further, the scan chain has a scan-in terminal as an input from the outside in the LSI chip 1 and a scan-out terminal as an output to the outside. For example, the scan chain can be controlled by a TAP controller 7 that is compliant with the JTAG Origin Test Architecture Group (compliant with IEEE 1149.1).

[0040] Each of the RAM macros 4 to 4 includes a plurality of memory cell groups and a redundant memory.

1 n

It has a cell group (reserve memory cell group) and a redundancy selection circuit. The memory cell groups in each RAM macro 4-4 are inspected by pre-shipment testing of LSI chip 1.

1 n

Done. In this pre-shipment test, a memory cell group containing defective memory cells If it is detected, the setting to replace the defective memory cell group with the redundant memory cell group (redundancy setting) is performed for each RAM macro.

[0041] The redundant setting is performed using a redundant selection signal. The redundant selection signal here is a signal indicating which one of the plurality of memory cell groups is to be replaced with the redundant memory cell group, and is output from the fuse when the fuses 2 and 2 are cut.

1 5

It is generated by combining signals of “0” and “1” with a predetermined number of bits.

[0042] The redundancy selection signal generated in this way is stored bit by bit in the latch of latch column 3,

1

A scan clock input (not shown) from the TAP controller 7 is scan-shifted via the scan chain (latch column 3 to latch column 3) and finally the redundancy of the latch column 3

1 mm Hold for setting latch 5 ~ 5. Note that the redundancy setting latches 5 to 5 are respectively redundant.

1 n 1 n

The latching force is the same as the number of bits of the long selection signal.

Further, the redundancy selection circuit of each RAM macro is connected to a plurality of memory cell groups, a redundancy memory cell group, and redundancy setting latches 5 to 5 in the latch column 3. And m 1 n

The redundancy selection circuit inputs the redundancy selection signal held in the redundancy setting latches 5 to 5.

1 n

Then, the defective memory cell group and the redundant memory cell group are replaced according to the decoding result of the input redundancy selection signal by the redundancy decoding circuit.

[0044] Here, the signal output from the fuses 2 and 2 by cutting them is described here.

1 5

The redundant selection signal is generated using the

1 Without 5

The scan-in terminal force may also be generated by directly scanning and shifting the redundant selection signal.

Next, the configuration of the RAM macro according to the present embodiment will be described. FIG. 2 is a block diagram showing the configuration of the RAM macro according to the present embodiment. As shown in FIGS. 4A and 4B, the redundancy selection circuit 20 in this RAM macro includes three memory cell groups 10 to 10 and

13

One redundant memory cell group 10 is connected. Memory cell groups 1 to 3

Four

Each redundant memory cell group has a read circuit and a write circuit.

Further, the redundancy selection circuit 20 is a redundancy decoding circuit 21 that decodes a redundancy selection signal, and a selection of a write circuit of a memory cell group that is a write destination of write data and a read destination of the read data. By selecting the readout circuit for the memory cell group, The redundant switch circuit 22 is configured to switch between the recell group and the redundant memory cell group. The redundant switch circuit 22 includes the memory cell groups 10 to 10 and the redundant memory circuit.

13

Redundant decode circuit 21 connected to resell group 10 and redundant setting latches 5 to 5

4 1 n Connected.

The redundancy decode circuit 21 has a redundancy selection signal held in the redundancy setting latches 5 to 5.

1 n

Based on the inputted redundancy selection signal, the redundancy setting of the memory cell group is determined, and a redundancy decode signal for controlling the redundancy switch circuit is outputted. Here, the redundancy selection signal originally set in the redundancy setting latches 5 to 5 is one redundancy setting signal.

1 n

It should show that However, a soft error occurs in the redundancy setting latches 5-5.

1 n

In such a case, the value of the redundancy selection signal that should have been retained may change, so that decoding for redundancy setting that should be performed may not be output correctly.

[0048] Therefore, the redundancy decoding circuit 21 indicates that the original redundancy selection signal is indicated even if one of the bits constituting the redundancy selection signal is inverted, V, or one of the bits! / Configure so that redundant settings can be judged. The method for determining this redundancy setting is described below.

FIG. 3 is a diagram illustrating an example of the redundant selection setting according to the present embodiment. Originally, the number of bits required for redundant setting is 2 bits, but in order to improve soft error tolerance, it is possible to further increase the bit width of redundant setting and increase the decoding pattern. As shown in the figure, for example, if the number of bits of the redundancy setting signal is increased by 3 bits from the originally required 2 bits to 5 bits, each redundancy setting is first set in the redundancy setting latch. Assign one redundant selection signal to

In the example shown in FIG. 2, any one of the memory cell groups 10 to 10 is a redundant memory cell.

13

Four types of redundancy settings, when replacing with group 10 and when redundancy selection is not performed

Four

Can be considered. Therefore, among the four redundant selection signals, “00000” is assigned to the case where no redundant selection is performed, and “00111”, “10111” and “11110” are assigned to the case where redundant selection is performed.

[0051] Then, five values obtained by inverting any one bit of the already assigned redundancy selection signal are further assigned to each redundancy setting. For example, redundant selection If this is not done, assign the following five values: “00000”, “0000”, “00010”, “00100”, “01000”, and “10000”.

[0052] By decoding the redundancy setting based on the redundancy selection signal thus assigned and the 1-bit inverted data of the redundancy selection signal, the redundancy selection circuit 20 has the redundancy setting latches 5-5. If there is a soft error in the redundant selection signal held in

1 η

However, if one of the bits in the redundant selection signal is inverted! /, The redundant selection can be performed correctly, so that the soft error resistance in the redundant selection can be improved. Can do.

Further, the redundancy switch circuit 22 replaces the defective memory cell group and the redundancy memory cell group 10 based on the redundancy setting decoded by the redundancy decoding circuit 21 (redundancy selection).

Four

I do.

In the example shown in FIG. 2 (a), redundant selection is shown when a defective memory cell group is incapacitated. In the figure, since the redundancy selection signal “00000” is set in the redundancy setting latch, it is determined that the redundancy decoding circuit 21 does not select redundancy, but the redundancy selection signal power 00001 ”,“ 00010 ”, Even if it is changed to “00100”, “01000”, or “10000”, it is determined by the redundant decoding circuit 21 that redundant selection is not performed.

In the example shown in FIG. 2B, a case where a failure occurs in the memory cell group 2 is shown. Thus, when a failure occurs in memory cell group 2, it is necessary to replace the failed memory cell group 2 with a redundant cell group. In the figure, since the redundancy selection signal “11001” is set in the redundancy setting latch, the power redundancy selection signal is “11000”, “11” which is determined to replace the memory cell group 2 and the redundancy memory cell group. Even if it is changed to “011”, “11101”, “10001” or “01001”, it is determined that the memory cell group 2 and the redundant memory cell group are exchanged.

In this way, the redundant decode circuit 21 is redundantly held in the redundancy setting latches 5 to 5.

1 n

Even if a long selection signal is input and the input redundancy selection signal is originally set and has changed from the previous value, if only one bit is inverted, the redundancy selection signal that was originally set is The redundancy setting latch is determined by determining that the redundancy setting is the same as

1

Even if a soft error occurs in ~ 5 and 1 bit of the redundancy selection signal is inverted Since redundant selection can be performed, it is possible to improve soft error tolerance in redundant selection.

[0057] When the soft error rate per latch is ser (Soft ERror), for example, in the redundancy setting of the conventional memory cell in FIG. 12 described above, a 2-bit redundancy selection signal is used for one redundancy setting. Are assigned one by one, so the soft error rate SERO in the redundant selection is

1

SERO = l-{(l -ser) ² }

1

It becomes.

On the other hand, in the redundancy setting shown in FIG. 3, one 5-bit redundancy selection signal and five values obtained by inverting the 1-bit redundancy selection signal are assigned to one redundancy setting. So, the soft error rate SERN in redundant selection is

1

SERN = 1— {(1— ser) ⁵ + 5 X (1 -ser) 'X ser}

1

It becomes.

[0059] Therefore, when a ser = 0. 001, SERO = 0. 002, SERN = 9. 98 X 10- 6 next

1 1

Compared to the conventional redundant selection of memory cells, the soft error resistance is increased by about 200 times.

[0060] In this way, by increasing the number of bits of the redundancy selection signal held in the latch and assigning one redundancy selection signal and a plurality of 1-bit inverted data to one redundancy setting, Soft error resistance can be improved.

[0061] Although the case where 1-bit inversion data is assigned to each redundancy setting has been described here, when a larger number of bits can be used for the redundancy selection signal, data in which a plurality of bits are inverted is used. Further allocation is possible.

Next, a method for generating a redundant selection signal according to the present embodiment will be described. FIG. 4 is a flowchart showing an algorithm for generating the redundancy selection signal shown in FIG.

As shown in FIG. 4, in this redundancy selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value for all bits of this data variable (step S101). For example, if the redundant selection signal is 5 bits, set “00000”. [0064] Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S102). f, for example, when the redundant selection signal power S is “00000”, 5 bits of 1-bit inverted data of “00001”, “00010”, “00100”, “01000” and “10000” are created. .

[0065] Then, the data variable is assigned to the redundancy selection signal (step S103), and the data variable and the 1-bit inverted data of the data variable are all assigned to the redundancy selection signal. It is registered in the used list indicating that it cannot be used (step S104).

[0066] Thereafter, 1 is added to the data variable to make it a new data variable (step S105), and 1-bit inverted data of the new data variable is created (step S106).

[0067] Here, the new data variable and the 1-bit inverted data of the data variable are compared with the contents of the used list (step S107). If the used list already contains the data variable or data with the same value as the 1-bit inverted data of the data variable (step S108, Yes), return to step S105 to add a new data variable. Set and repeat the process from step S106.

[0068] On the other hand, when the used list does not include the data variable and the data having the same value as the 1-bit inverted data of the data variable (step S108, No), the data variable is set to the redundant selection signal. (Step S109), and the data variable and the 1-bit inverted data of the data variable are registered in the used list (step S110).

Here, when the necessary number of redundant selection signals are assigned to the data variable (step S111, Yes), the process is terminated. If the necessary number is not satisfied (step Sill, No), the process returns to step S105, a new data variable is set, and the processing after step S106 is repeated.

[0070] As shown in FIG. 3, the redundancy selection signal generated by the above algorithm and the 1-bit inverted data of each redundancy selection signal are allocated to the redundancy setting.

[0071] Here, for one redundancy setting, only one bit is inverted for one redundancy selection signal set in the latch and a plurality of bits constituting the redundancy selection signal. Explains how to assign all obtained 1-bit inverted data. [0072] In this case, for example, in the case of seven redundancy settings for replacing the memory cell groups 1 to 7 with the redundant memory cell group, 1 bit is used to replace the memory cell groups 1 to 7 with the redundant memory group. Since 1-bit inverted data obtained by inverting is associated with each memory cell group, a redundant selection signal of at least 7 bits is required. However, even if only 4 bits can be secured for the redundancy selection signal due to circuit area restrictions, etc., one 4-bit redundancy selection signal and 4 bits for the redundancy selection signal for each redundancy setting. Even if only one 1-bit inverted data with 1 bit inverted is assigned, the soft error tolerance is improved compared to decoding with only one redundant selection signal.

FIG. 5 is a diagram showing a case where two redundancy selection signals are assigned to one redundancy setting. In the example shown in the figure, there are 8 redundancy settings, and a 4-bit redundancy selection signal is used, and for each redundancy setting, there is one redundancy selection signal and one redundancy selection signal. Allocate 1-bit inverted data.

[0074] In this way, by limiting the 1-bit inverted data assigned to each redundancy setting, the number of bits that can be used for the redundancy selection signal is limited due to circuit area restrictions, etc. However, soft error tolerance in redundant selection can be improved.

[0075] Further, the case where the redundancy selection signal is equally assigned to each redundancy setting indicating the replacement pattern of the memory cell has been described so far, but by assigning more redundancy selection signals to a specific pattern, This can be achieved by improving the soft error tolerance with emphasis on patterns.

FIG. 6 is a flow chart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a redundancy setting when no redundancy selection is performed as a specific redundancy setting.

As shown in FIG. 6, in this redundancy selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S 201). For example, if it is a redundant selection variable force bit, set “0000”.

[0078] Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S202). For example, in the case of the redundant selection signal power bit, four types of inverted data “0001”, “0010”, “010 0”, and “1000” are created.

[0079] Then, the data variable is assigned to the redundancy selection signal (step S203), and all the data variable and 1-bit inverted data of the data variable are registered in the used list (step S204).

[0080] After that, 1 is added to the data variable to make this a new data variable (step S205).

Here, the data variable is compared with the used list (step S206). If the used list already contains data with the same value as the data variable (step S207, Yes), the process returns to step S205, sets a new data variable, and repeats the processing from step S206.

[0082] On the other hand, if the used list does not contain data having the same value as the data variable (step S207, No), the data variable is assigned to the redundant selection signal (step S208), and further The data variable is registered in the used list (step S209).

Here, when the necessary number of redundant selection signals are assigned to the data variable (step S210, Yes), the process is terminated. If the required number is not satisfied (step S210, No), the process returns to step S205 to set a new data variable, and the processes after step S206 are repeated.

[0084] FIG. 7 is a diagram illustrating an example in which a redundancy selection signal is assigned to a specific redundancy setting. In the example shown in the figure, a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit. ”,“ 0010 ”,“ 0100 ”and“ 1000 ”in total, allotting 5 redundant selection signals and replacing the redundant memory cell groups with other memory cell groups 1 to 7 Assign redundant selection signals one by one.

[0085] Replacing memory cell groups 1 to 7 and redundant memory cell groups In the case of seven redundancy settings, it is necessary to replace memory cell groups 1 to 7 and redundant memory groups. Since 1-bit inverted data corresponds to each memory cell group, the redundancy selection signal generated by the above algorithm and redundancy selection with all bits set to “0” A redundant setting that indicates the replacement pattern of the memory cell is assigned using 1-bit inverted data of the signal.

[0086] In this way, by allocating 1-bit inverted data focusing on a specific redundancy setting, a redundancy setting that has a high possibility of being actually set, for example, when no redundancy is selected among a plurality of redundancy settings. As a result, it is possible to improve soft error tolerance in redundant selection.

[0087] Further, in the redundancy selection signal generation method shown in Fig. 6, the case has been described in which the redundancy selection signal is assigned with priority to a specific redundancy setting. In this method, for a specific redundancy setting, the power of assigning 1-bit inverted data so that the redundancy setting can be determined even if only 1 bit is inverted in the redundancy selection signal assigned to that redundancy setting. Furthermore, by assigning 2-bit inverted data, the redundant setting may be determined even if the 2 bits are inverted.

FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in the case where 2-bit inverted data is further assigned to a specific redundancy setting.

As shown in FIG. 8, in this redundant selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S301). For example, if it is a redundant selection variable force bit, set “0000”.

[0090] Then, 1-bit inverted data obtained by inverting only 1 bit of the data variable and 2-bit inverted data obtained by inverting 2 bits are created (step S302). For example, when the redundancy selection signal is 4 bits, four types of 1-bit inverted data of “0001”, “0010”, “0100”, and “1000”, “0011”, “0101”, “ A total of 10 inverted data consisting of 6 2-bit inverted data of “0110”, “1001”, “1010” and “1100” is created.

[0091] Then, the data variable is assigned to the redundancy selection signal (step S303), and the data variable, the 1-bit inverted data and the 2-bit inverted data of the data variable are all registered in the used list (step S303). S304).

[0092] After that, 1 is added to the data variable to make this a new data variable (step S305). Here, the new data variable is compared with the used list (step S306). If the used list already contains data with the same value as the relevant data variable (step S307, Yes), the data variable will be the maximum value represented by the given number of bits (eg “1111”). It is determined whether or not there is (step S311).

[0094] If the data variable is equal to the maximum value represented by the given number of bits (eg, "1111") (step S311, Yes), until the required number is satisfied for the data variable, The 2-bit inverted data in the used list is assigned to the redundancy selection signal (step S312). On the other hand, if the data variable is weak at the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated. If the used list does not contain data with the same value as the data variable (Step S307, No), the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).

Here, when the necessary number of redundant selection signals are assigned to the data variable (step S310, Yes), the process is terminated. If the required number is not satisfied (step S310, No), it is determined whether or not the data variable is the maximum value represented by the given number of bits.

[0096] If the data variable has the maximum value (step S311, Yes), the 2-bit inverted data in the used list is assigned to the redundant selection signal until the required number is satisfied (step S312). On the other hand, when the data variable is weak at the maximum value (step S311, No), the process returns to step S305 to set a new data variable and repeats the processing after step S306.

Redundancy settings are assigned using the redundancy selection signal generated by the above algorithm and the 1-bit inverted data and 2-bit inverted data of the redundancy selection signal with all bits being “0”. FIG. 9 is a diagram showing an example in which redundant selection signals remaining for a specific redundant setting are further allocated. In the example shown in the figure, a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, a redundancy selection signal with all bits set to “0”, all 1-bit inverted data, and 2-bit inverted data. Memory cells that are assigned to the redundant selection signal. Redundant selection signals are assigned to each of the seven redundancy settings that replace redundant memory cell groups with groups 1-7.

[0098] Although the case where 1-bit inverted data and 2-bit inverted data are assigned to a specific redundancy setting has been described here, if a larger number of bits can be used for the redundancy selection signal, 3 Data in which bits or more are inverted may be further allocated.

[0099] As described above, by assigning data in which a plurality of bits are inverted as much as possible according to the number of bits that can be used for the redundancy selection signal, soft error resistance in redundancy selection is further improved for a specific redundancy setting. can do.

FIG. 10 is a diagram showing an example of a redundant decoding circuit based on the redundant setting shown in FIG. The redundant decoding circuit of the example shown in the figure also consists of four inverter circuits, seven AND circuits, and six OR circuit powers. This redundant decode circuit outputs 7-bit redundant decode signals SEL0 to SEL6 in response to 4-bit redundant select signals RED0 to RED3.

[0101] The redundant decode signals SEL0 to SEL6 output by decoding the 4-bit redundancy selection signals RED0 to RED3 are "0000000", "1111111", "1111110", "1111 100", "1111000", There are 8 types of “1110000”, “1100000” and “1000000”. Each of these redundant decode signals SEL0 to SEL6 is associated with eight redundancy settings. Then, based on these redundant decode signals SEL0 to SEL6, the redundant setting of the memory cell group is performed by the redundant switch circuit.

[0102] As described above, in this embodiment, the redundancy setting latch 5 to 5 force memory cell group

1 n

The redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the group is held in advance, and the redundancy selection circuit 21 inverts even when a part of the redundancy selection signal is inverted by inputting this redundancy selection signal. The redundancy setting same as the redundancy setting associated with the previous redundancy selection signal is derived, and the redundancy switch circuit 22 replaces the memory cell group based on the derived redundancy setting. The redundancy selection signal held in the redundancy setting latches 5 to 5 caused a soft error due to

1 n

Even in this case, since the redundancy selection can be performed correctly, the soft error resistance in the redundancy selection can be improved.

Industrial applicability As described above, the redundancy selection device and the redundancy selection method according to the present invention are useful for a semiconductor memory device that performs redundancy selection in which a defective memory cell is replaced with a redundancy memory cell, and in particular, controls redundancy selection such as a redundancy selection signal. Processors that contain semiconductor devices that hold data for a long time are suitable for LSI such as DSP (Digital Signal Processor) and SOC (System On Chip).

Claims

The scope of the claims

[1] A memory redundancy selection device that is connected to a memory cell and a redundancy memory cell constituting a storage device and performs redundancy selection for selecting an input / output of either the memory cell or the redundancy memory cell,

A redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell;

When the redundancy selection signal held in the redundancy selection information holding means is input, even if a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decode result. Redundant decoding means to perform,

Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;

A memory redundancy selection device comprising:

2. The memory redundancy selection device according to claim 1, wherein the redundancy selection signal holding means is constituted by a scan latch means.

3. The memory redundancy according to claim 1, wherein the redundancy decoding means is configured to associate at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result. Selection device.

[4] The redundancy selection signal is composed of n bits (n> 1),

The redundant decoding means outputs the same redundancy setting as the decoding result as the decoding result even when k bits (0 <k≤n-1) of n bits constituting the redundancy selection signal are inverted. The memory redundancy selection device according to claim 1, wherein the memory redundancy selection device is performed.

[5] Memory Senore and

Redundant memory cells;

Redundant selection means connected to the memory cell and the redundant memory cell, and performing redundant selection for selecting input / output of either the memory cell or the redundant memory cell; and

A redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell; When the redundancy selection signal held in the redundancy selection information holding means is input, even if a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decode result. Redundant decoding means to perform,

A storage device comprising:

[6] Memory Senore,

Redundant memory cells;

An arithmetic processing unit connected to the storage device;

An information processing apparatus comprising:

[7] The information processing apparatus further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and includes a redundancy selection signal holding unit;

A fuse means connected to the scan latch means for setting a redundancy selection signal;

7. The redundancy selection signal set in the fuse means is output to the scan latch means, and the redundancy selection signal is held in the redundancy selection signal holding means by performing the scan shift. The information processing apparatus described.

[8] The information processing apparatus further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and includes a redundancy selection signal holding unit;

A scan input connected to the scan latch means;

7. The information processing apparatus according to claim 6, wherein the redundancy selection signal is held in the redundancy selection signal holding unit by inputting the redundancy selection signal from the scan input and performing the scan shift.

[9] A memory cell redundancy selection method for selecting input / output of a memory cell or a redundant memory cell constituting a storage device,

A step of holding a redundancy selection signal indicating selection information of the memory cell, and inputting the held redundancy selection signal, and even when a part of the redundancy selection signal is inverted, the same as before the inversion A step of outputting the redundant setting as a decoding result; and

Based on the decoding result !, selecting the input / output of either the memory cell or the redundant memory cell;

A method for redundant selection of memory cells, comprising:

[10] The retained redundancy selection signal is input, and even when a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decoding result.

10. The method for redundant selection of memory cells according to claim 9, wherein at least two redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.

[11] A memory redundancy selection device for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor memory device,

Redundancy selection signal holding means for holding in advance a redundancy selection signal associated with a redundancy setting indicating a replacement pattern of a memory cell;

Redundant decoding means for deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal; Redundant switch means for replacing a memory cell based on the redundancy setting derived by the redundant decoding means;

A memory redundancy selection device comprising:

[12] The redundancy selection signal is composed of n bits (n> 1),

The redundant decoding means is associated with the redundant selection signal before inversion even when n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 12. The memory redundancy selection device according to claim 11, wherein a redundancy setting that is the same as the redundancy setting is derived.

[13] The redundant decoding means may perform redundancy before inversion even if n-k bits (0 <k≤n-1) are inverted for a predetermined bit among n bits constituting the redundancy selection signal. 13. The memory redundancy selection device according to claim 12, wherein the redundancy setting that is the same as the redundancy setting associated with the selection signal is derived.

[14] The redundancy decoding means inverts n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal for a specific redundancy setting. 13. The memory redundancy selection device according to claim 12, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.

[15] The redundancy decoding means inverts up to n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal for redundancy setting in which memory cells are not replaced. 15. The memory redundancy selection device according to claim 14, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.

[16] The redundant decoding means is any one of n bits constituting the redundant selection signal.

13. The memory redundancy selection device according to claim 12, wherein even if one bit is inverted, a redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before being inverted is derived.

[17] The redundant decoding means is associated with the redundant selection signal before inversion even if one of the n bits constituting the redundancy selection signal is inverted for a specific redundancy setting. 15. The memory redundancy selection device according to claim 14, wherein the same redundancy setting as the redundancy setting is derived.

[18] For the redundancy setting in which the memory cell is not replaced, the redundancy decoding means selects the redundancy before inversion even if any one of the n bits constituting the redundancy selection signal is inverted. 18. The memory redundancy selection device according to claim 17, wherein the redundancy setting same as the redundancy setting associated with the signal is derived.

[19] The memory redundancy selection according to any one of [11] to [18], wherein the redundancy selection signal holding means holds the redundancy selection signal in a latch mounted on the semiconductor memory device. apparatus.

20. The memory redundancy selection device according to claim 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by a signal generated by cutting a fuse. .

21. The memory redundancy selection device according to claim 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by an externally input signal.

[22] A memory redundancy selection method for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor memory device,

A redundancy selection signal holding step for holding in advance a redundancy selection signal associated with a redundancy setting indicating a memory cell replacement pattern;

A redundancy decoding step of deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal;

A redundant switch step for replacing a memory cell based on the redundancy setting derived by the redundant decoding step;

A method for redundant selection of memory cells, comprising:

[23] The redundancy selection signal is composed of n bits (n> 1),

The redundant decoding step is associated with the redundant selection signal before inversion even when n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 23. The method for redundant selection of memory cells according to claim 22, wherein a redundancy setting that is the same as the redundancy setting is derived.

[24] The redundant decoding step includes a predetermined bit of n bits constituting the redundant selection signal. A request characterized by deriving the same redundancy setting as that associated with the redundancy selection signal before inversion even if n−k bits (0 <k≤n—1) are inverted. 24. A method of redundant selection of memory cells according to item 23.

[25] In the redundancy decoding step, n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal are inverted for a specific redundancy setting. 24. The method of redundant selection of memory cells according to claim 23, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived even in the case.

[26] In the redundancy decoding step, n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal were inverted for the redundancy setting in which the memory cell is not replaced. 26. The method of redundant selection of a memory cell according to claim 25, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.

[27] In the redundancy decoding step, even if any one of the n bits constituting the redundancy selection signal is inverted, the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion is performed. 24. The method for redundantly selecting memory cells according to claim 23, wherein:

[28] The redundant decoding process is for a specific redundant setting! In other words, even if any one of the n bits constituting the redundancy selection signal is inverted, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. 26. The method for redundant selection of memory cells according to claim 25.

[29] In the redundancy decoding step, the redundancy selection before the inversion is performed even if one of the n bits constituting the redundancy selection signal is inverted for the redundancy setting in which the memory cell is not replaced. 30. The method for redundant selection of memory cells according to claim 28, wherein the same redundancy setting as that for the signal is derived.

30. The memory cell according to claim 22, wherein the redundancy selection signal holding step holds the redundancy selection signal in a latch mounted on the semiconductor memory device. Redundant selection method.