WO2007072580A1 - Memory-redundancy selecting device, memory device, information processing device, and method of selecting redundancy of memory cell - Google Patents
Memory-redundancy selecting device, memory device, information processing device, and method of selecting redundancy of memory cell Download PDFInfo
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- WO2007072580A1 WO2007072580A1 PCT/JP2006/303153 JP2006303153W WO2007072580A1 WO 2007072580 A1 WO2007072580 A1 WO 2007072580A1 JP 2006303153 W JP2006303153 W JP 2006303153W WO 2007072580 A1 WO2007072580 A1 WO 2007072580A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
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- Memory redundancy selection device storage device, information processing device, and memory cell redundancy selection method
- the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell for performing redundancy selection in which a defective memory cell is replaced with a redundant memory cell in a semiconductor storage device such as a RAM built in an LSI such as a processor
- the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell redundancy selection method that can improve soft error tolerance in redundancy selection.
- a processor incorporating a semiconductor memory device such as a RAM as a cache memory has a spare memory cell called a redundant memory cell in preparation for a manufacturing failure in an LSI such as a DSP (Digital Signal Processor) or SOC (System On Chip).
- LSI Digital Signal Processor
- SOC System On Chip
- the address indicated by the defective memory cell is set by switching a memory cell by setting an address of the defective memory cell by cutting a fuse arranged on a semiconductor chip.
- a technique for switching a memory cell to a redundant memory cell has been devised (for example, see Patent Document 1) o
- a redundant selection signal when a memory cell is replaced using a signal for replacing a defective memory cell with a redundant memory cell (hereinafter referred to as a redundant selection signal), this signal is sent from the fuse to the memory cell. Although it may be input directly to a circuit for replacement (hereinafter referred to as a redundancy selection circuit), it is input via a scan chain composed of scan latches arranged on the chip to avoid complicated wiring. Sometimes.
- FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.
- the RAM macro shown in the figure includes three memory cell groups 1 to 3 and one redundant memory cell group (reserved memory group).
- a memory cell is composed of a memory cell group) and a redundancy selection circuit.
- the memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit.
- the redundancy selection circuit selects the memory cell group as a write destination of the write data and selects the read circuit of the memory cell group as the read destination of the read data. It consists of a redundant switch circuit that switches between redundant memory cell groups and a redundant decoding circuit that decodes redundant selection signals.
- the redundant switch circuit switches the defective memory cell group to the redundant memory cell group. Perform (redundant selection). At this time, the redundant switch circuit switches the memory cell groups in accordance with the redundant selection signal input via the redundant decoding circuit. The redundancy selection signal is held in the redundancy setting latch.
- the redundancy setting is defined using a 2-bit redundancy selection signal so that four redundancy settings can be decoded by each redundancy selection signal.
- FIG. 12 is a diagram illustrating an example of a redundancy selection signal in the redundancy selection of a conventional memory cell. As shown in the figure, a 2-bit redundancy selection signal is set by a combination of “0” and “1”, and four redundancy settings are assigned to each.
- redundancy selection signal “00” is input as a redundancy selection signal.
- a redundancy selection signal “00” is held in the redundancy setting latch.
- the redundancy selection circuit decodes the redundancy selection signal “00”, but the redundancy switch circuit does not switch to the redundancy memory cell group.
- the memory cell group 2 is a defective memory cell. Then, “10” is input as the redundancy selection signal. A redundancy selection signal “1 0” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “10”, and the redundancy switch circuit switches to the redundancy memory cell group.
- FIG. 13 is a diagram illustrating an example of a conventional redundancy selection circuit.
- FIG. 2A shows an example of a redundant switch circuit
- FIG. 2B shows an example of a redundant decode circuit.
- FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG.
- the redundant decoding circuit includes two inverter circuits, three AND circuits, and two OR circuit forces.
- This redundant decode circuit outputs 3-bit redundant decode signals SEL0 to SEL2, which are select signals for the redundant switch circuit, as shown in FIG. 14, in response to 2-bit redundant selection signals RED0 to RED1.
- the redundant switch circuit is configured by a combination of three sets of AND-OR equivalent circuits configured by a combination circuit of three NAND circuits.
- This redundant switch circuit includes memory cell groups ARRAY0 to ARRAY2 and redundant memory cell group ARRAYR as shown in FIG. Switches the connection with OUT0 to OUT2.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2005-149667
- the present invention has been made to solve the above-described problems caused by the prior art, and an object thereof is to provide a redundancy selection device and a redundancy selection method that can improve soft error resistance in redundancy selection.
- the redundancy selection device of the present invention is connected to a memory cell and a redundancy memory cell constituting a storage device, and the memory cell or the redundancy memory cell
- redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.
- the redundant selection signal holding means in the redundant selection device of the present invention is characterized by comprising a scan latch means.
- the redundancy decoding means in the redundancy selection device of the present invention associates at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result when decoding the redundancy selection signal. It is characterized by being configured.
- the redundancy selection signal in the redundancy selection device of the present invention is composed of n bits (n> 1), and the redundancy decoding means includes k bits (0 ⁇ k) of the n bits constituting the redundancy selection signal. Even when ⁇ n—1) is inverted, the same redundancy setting as before the inversion is output as a decoding result.
- the memory device of the present invention is connected to the memory cell, the redundant memory cell, the memory cell and the redundant memory cell, and selects either the memory cell or the redundant memory cell.
- Redundancy selection means for performing redundancy selection, and the redundancy selection means is held in a redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell and in the redundancy selection information holding means.
- redundant decoding means for outputting the same redundancy setting as before decoding as a decoding result, and based on the decoding result
- redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.
- the information processing apparatus includes a memory cell, a redundant memory cell, an arithmetic processing unit connected to the storage device, the memory cell and the redundant memory cell, and the memory cell Or redundancy selection means for performing redundancy selection for selecting any input / output of the redundant memory cell, wherein the redundancy selection means holds a redundancy selection signal indicating selection information of the memory cell.
- the redundancy selection signal held in the holding means and the redundancy selection information holding means is inputted, and the part of the redundancy selection signal is inverted! Redundant decoding means for outputting as a decoding result, and redundant switching means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result.
- the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit.
- Latch means and fuse means connected to the scan latch means for setting a redundancy selection signal, outputting the redundancy selection signal set in the fuse means to the scan latch means, and performing the scan shift.
- the redundancy selection signal is held in the redundancy selection signal holding means.
- the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit.
- the redundancy selection signal holding means includes the latch means and a scan input connected to the scan latch means, and inputs the redundancy selection signal from the scan input and performs the scan shift, so that the redundancy selection signal is held in the redundancy selection signal holding means. It is characterized by holding a signal.
- the redundancy selection method of the present invention is a memory cell redundancy selection method for selecting input / output of either a memory cell or a redundant memory cell constituting a storage device, wherein the selection of the memory cell is performed.
- a step of holding a redundant selection signal indicating information and a case where the held redundant selection signal is input and a part of the redundant selection signal is inverted! /! The step of outputting the same redundancy setting as the decoding result even before inversion, and the selection of the input / output of either the memory cell or the redundant memory cell based on the decoding result And a step of performing.
- the redundancy selection method even when the retained redundancy selection signal is input and a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is performed.
- the step of outputting as a decoding result at least two or more redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.
- the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell is held in advance, and a part of the redundancy selection signal is changed by inputting the redundancy selection signal. Even in this case, the same redundancy setting as before the change was derived, and based on the derived redundancy setting! /, The memory cell was replaced, so the redundancy selection signal held by the influence of radiation from space, etc. Even if a soft error occurs, the redundancy selection can be performed correctly, so that the soft error tolerance in the redundant selection can be improved.
- the redundancy selection signal is composed of n bits (n> 1), and k bits (0 ⁇ k ⁇ n—1) of n bits constituting the redundancy selection signal. Even if is reversed, it is configured to derive the same redundancy setting as that associated with the redundancy selection signal before the inversion, so that a soft error has occurred in the retained redundancy selection signal. However, if k bits (0 ⁇ k ⁇ n—1) of n bits that make up the redundancy selection signal are inverted, the redundancy selection can be performed correctly, improving the soft error tolerance in the redundancy selection. If you can!
- k bits (0 ⁇ k ⁇ n-1) are inverted with respect to a predetermined bit among n bits ( ⁇ > 1) constituting the redundancy selection signal,
- n bits ( ⁇ > 1) constituting the redundancy selection signal
- the same redundancy setting as that associated with the redundancy selection signal before inversion is derived, so that the redundancy selection signal can be determined by limiting the bits from which the same redundancy setting can be derived even if it is inverted. Even when the number of bits that can be used for the selection is limited, the soft error tolerance in redundancy selection can be improved.
- n signals that constitute a redundancy selection signal. Inverting up to k bits (0 ⁇ k ⁇ n—1) in a set (n> 1), the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. As a result, it is possible to improve the resistance to soft errors in the redundant selection with a focus on the redundant setting having a high probability of being actually set among a plurality of redundant settings.
- the redundant setting in which the memory cell is not replaced up to k bits (0 ⁇ k ⁇ n—1) out of n bits (n> 1) constituting the redundancy selection signal. Even if it is inverted, it is configured to derive the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion, so there is a high probability that it will actually be set, and redundancy that does not replace the memory cell It is possible to improve the tolerance of soft errors in redundant selection with emphasis on setting!
- any one bit of n bits ( ⁇ > 1) constituting the redundant selection signal is inverted, it is associated with the redundant selection signal before being inverted. Since the same redundancy setting as the redundancy setting is derived, even if a soft error has occurred in the retained redundancy selection signal, one of the n bits that make up the redundancy selection signal is inverted. In such a case, since the redundant selection can be performed correctly, the soft error resistance in the redundant selection can be improved.
- the redundant setting that is the same as the redundant setting associated with the redundant selection signal before the configuration is derived, the redundant setting that has a high probability of being actually set is selected among the redundant settings. There is an effect that resistance to soft errors can be improved.
- one bit out of n bits (n> 1) constituting the redundancy selection signal is inverted by redundancy setting. Even if it is, the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived, so there is a high probability that it will actually be set, and the redundancy that does not replace the memory cell If you can improve the tolerance of soft errors in the redundant selection with emphasis on the setting!
- FIG. 1 is an explanatory diagram for explaining an outline of redundancy selection according to the present embodiment.
- FIG. 2 is a block diagram showing a configuration of a RAM macro according to the present embodiment.
- FIG. 3 is a diagram illustrating an example of redundancy setting according to the present embodiment.
- FIG. 4 is a flowchart showing an algorithm for generating the redundant selection signal shown in FIG.
- FIG. 5 is a diagram showing an example of assigning two redundancy selection signals to one redundancy setting.
- FIG. 6 is a flowchart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a specific redundancy setting with priority.
- FIG. 7 is a diagram showing an example in which a redundancy selection signal is assigned to a specific redundancy setting.
- FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in a case where 2-digit inversion data is further assigned to a specific redundancy setting.
- FIG. 9 is a diagram showing an example in the case of further assigning redundant selection signals remaining in a specific redundancy setting.
- FIG. 10 is a diagram showing an example of a redundancy decoding circuit with redundancy setting shown in FIG.
- FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.
- FIG. 12 is a diagram showing an example of a redundancy selection signal in redundancy selection of a conventional memory cell.
- FIG. 13 is a diagram showing an example of a conventional redundancy selection circuit.
- FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG. 13.
- FIG. 1 is an explanatory diagram for explaining an outline of redundant selection according to the present embodiment.
- the LSI chip 1 shown in the figure includes a plurality of fuses 2 to 2, a plurality of latch trains 3 to 3, a plurality of RAM macros 4 to 4, and a plurality of fuses.
- a processor core unit 6 that uses 1 5 1 m I n number of RAM macros as cache memory and a TAP (Test Access Port) controller 7 that controls scan of a plurality of latch rows are arranged.
- Each of the latch trains 3 to 3 includes a plurality of scan latches.
- H-rows 3 to 3 are connected in a daisy chain to form a scan chain with a scan latch
- Latch row 3 has fuse 2 to 2 force Latch row 3 has RAM macro 4 to 4
- the scan chain has a scan-in terminal as an input from the outside in the LSI chip 1 and a scan-out terminal as an output to the outside.
- the scan chain can be controlled by a TAP controller 7 that is compliant with the JTAG Origin Test Architecture Group (compliant with IEEE 1149.1).
- Each of the RAM macros 4 to 4 includes a plurality of memory cell groups and a redundant memory.
- each RAM macro 4-4 has a cell group (reserve memory cell group) and a redundancy selection circuit.
- the memory cell groups in each RAM macro 4-4 are inspected by pre-shipment testing of LSI chip 1.
- the redundant setting is performed using a redundant selection signal.
- the redundant selection signal here is a signal indicating which one of the plurality of memory cell groups is to be replaced with the redundant memory cell group, and is output from the fuse when the fuses 2 and 2 are cut.
- the redundancy selection signal generated in this way is stored bit by bit in the latch of latch column 3,
- a scan clock input (not shown) from the TAP controller 7 is scan-shifted via the scan chain (latch column 3 to latch column 3) and finally the redundancy of the latch column 3
- the latching force is the same as the number of bits of the long selection signal.
- each RAM macro is connected to a plurality of memory cell groups, a redundancy memory cell group, and redundancy setting latches 5 to 5 in the latch column 3.
- the redundancy selection circuit inputs the redundancy selection signal held in the redundancy setting latches 5 to 5.
- the defective memory cell group and the redundant memory cell group are replaced according to the decoding result of the input redundancy selection signal by the redundancy decoding circuit.
- the redundant selection signal is generated using the
- the scan-in terminal force may also be generated by directly scanning and shifting the redundant selection signal.
- FIG. 2 is a block diagram showing the configuration of the RAM macro according to the present embodiment.
- the redundancy selection circuit 20 in this RAM macro includes three memory cell groups 10 to 10 and
- Memory cell groups 1 to 3 are connected.
- Each redundant memory cell group has a read circuit and a write circuit.
- the redundancy selection circuit 20 is a redundancy decoding circuit 21 that decodes a redundancy selection signal, and a selection of a write circuit of a memory cell group that is a write destination of write data and a read destination of the read data.
- the redundant switch circuit 22 is configured to switch between the recell group and the redundant memory cell group.
- the redundant switch circuit 22 includes the memory cell groups 10 to 10 and the redundant memory circuit.
- Redundant decode circuit 21 connected to resell group 10 and redundant setting latches 5 to 5
- the redundancy decode circuit 21 has a redundancy selection signal held in the redundancy setting latches 5 to 5.
- the redundancy setting of the memory cell group is determined, and a redundancy decode signal for controlling the redundancy switch circuit is outputted.
- the redundancy selection signal originally set in the redundancy setting latches 5 to 5 is one redundancy setting signal.
- the value of the redundancy selection signal that should have been retained may change, so that decoding for redundancy setting that should be performed may not be output correctly.
- the redundancy decoding circuit 21 indicates that the original redundancy selection signal is indicated even if one of the bits constituting the redundancy selection signal is inverted, V, or one of the bits! / Configure so that redundant settings can be judged.
- the method for determining this redundancy setting is described below.
- FIG. 3 is a diagram illustrating an example of the redundant selection setting according to the present embodiment.
- the number of bits required for redundant setting is 2 bits, but in order to improve soft error tolerance, it is possible to further increase the bit width of redundant setting and increase the decoding pattern.
- the number of bits of the redundancy setting signal is increased by 3 bits from the originally required 2 bits to 5 bits, each redundancy setting is first set in the redundancy setting latch. Assign one redundant selection signal to
- any one of the memory cell groups 10 to 10 is a redundant memory cell.
- the redundancy selection circuit 20 By decoding the redundancy setting based on the redundancy selection signal thus assigned and the 1-bit inverted data of the redundancy selection signal, the redundancy selection circuit 20 has the redundancy setting latches 5-5. If there is a soft error in the redundant selection signal held in
- the redundancy switch circuit 22 replaces the defective memory cell group and the redundancy memory cell group 10 based on the redundancy setting decoded by the redundancy decoding circuit 21 (redundancy selection).
- redundant selection is shown when a defective memory cell group is incapacitated.
- the redundancy selection signal “00000” is set in the redundancy setting latch, it is determined that the redundancy decoding circuit 21 does not select redundancy, but the redundancy selection signal power 00001 ”,“ 00010 ”, Even if it is changed to “00100”, “01000”, or “10000”, it is determined by the redundant decoding circuit 21 that redundant selection is not performed.
- FIG. 2B a case where a failure occurs in the memory cell group 2 is shown.
- the redundancy selection signal “11001” is set in the redundancy setting latch
- the power redundancy selection signal is “11000”, “11” which is determined to replace the memory cell group 2 and the redundancy memory cell group. Even if it is changed to “011”, “11101”, “10001” or “01001”, it is determined that the memory cell group 2 and the redundant memory cell group are exchanged.
- the redundant decode circuit 21 is redundantly held in the redundancy setting latches 5 to 5.
- the redundancy setting latch is determined by determining that the redundancy setting is the same as
- the soft error rate per latch is ser (Soft ERror), for example, in the redundancy setting of the conventional memory cell in FIG. 12 described above, a 2-bit redundancy selection signal is used for one redundancy setting. Are assigned one by one, so the soft error rate SERO in the redundant selection is
- the soft error resistance is increased by about 200 times.
- FIG. 4 is a flowchart showing an algorithm for generating the redundancy selection signal shown in FIG.
- a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined.
- This data variable is set to a binary number.
- “0” is set as an initial value for all bits of this data variable (step S101). For example, if the redundant selection signal is 5 bits, set “00000”.
- 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S102). f, for example, when the redundant selection signal power S is “00000”, 5 bits of 1-bit inverted data of “00001”, “00010”, “00100”, “01000” and “10000” are created. .
- the data variable is assigned to the redundancy selection signal (step S103), and the data variable and the 1-bit inverted data of the data variable are all assigned to the redundancy selection signal. It is registered in the used list indicating that it cannot be used (step S104).
- step S105 1 is added to the data variable to make it a new data variable (step S105), and 1-bit inverted data of the new data variable is created (step S106).
- step S107 the new data variable and the 1-bit inverted data of the data variable are compared with the contents of the used list. If the used list already contains the data variable or data with the same value as the 1-bit inverted data of the data variable (step S108, Yes), return to step S105 to add a new data variable. Set and repeat the process from step S106.
- step S108 when the used list does not include the data variable and the data having the same value as the 1-bit inverted data of the data variable (step S108, No), the data variable is set to the redundant selection signal. (Step S109), and the data variable and the 1-bit inverted data of the data variable are registered in the used list (step S110).
- step S111 when the necessary number of redundant selection signals are assigned to the data variable (step S111, Yes), the process is terminated. If the necessary number is not satisfied (step Sill, No), the process returns to step S105, a new data variable is set, and the processing after step S106 is repeated.
- the redundancy selection signal generated by the above algorithm and the 1-bit inverted data of each redundancy selection signal are allocated to the redundancy setting.
- FIG. 5 is a diagram showing a case where two redundancy selection signals are assigned to one redundancy setting.
- there are 8 redundancy settings and a 4-bit redundancy selection signal is used, and for each redundancy setting, there is one redundancy selection signal and one redundancy selection signal. Allocate 1-bit inverted data.
- redundancy selection signal is equally assigned to each redundancy setting indicating the replacement pattern of the memory cell so far, but by assigning more redundancy selection signals to a specific pattern, This can be achieved by improving the soft error tolerance with emphasis on patterns.
- FIG. 6 is a flow chart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a redundancy setting when no redundancy selection is performed as a specific redundancy setting.
- a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined.
- This data variable is set to a binary number.
- “0” is set as an initial value in all bits of the data variable (step S 201). For example, if it is a redundant selection variable force bit, set “0000”.
- 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S202). For example, in the case of the redundant selection signal power bit, four types of inverted data “0001”, “0010”, “010 0”, and “1000” are created.
- the data variable is assigned to the redundancy selection signal (step S203), and all the data variable and 1-bit inverted data of the data variable are registered in the used list (step S204).
- step S206 the data variable is compared with the used list (step S206). If the used list already contains data with the same value as the data variable (step S207, Yes), the process returns to step S205, sets a new data variable, and repeats the processing from step S206.
- step S207, No if the used list does not contain data having the same value as the data variable (step S207, No), the data variable is assigned to the redundant selection signal (step S208), and further The data variable is registered in the used list (step S209).
- step S210 when the necessary number of redundant selection signals are assigned to the data variable (step S210, Yes), the process is terminated. If the required number is not satisfied (step S210, No), the process returns to step S205 to set a new data variable, and the processes after step S206 are repeated.
- FIG. 7 is a diagram illustrating an example in which a redundancy selection signal is assigned to a specific redundancy setting.
- a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit.
- redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit.
- ”,“ 0010 ”,“ 0100 ”and“ 1000 ”in total allotting 5 redundant selection signals and replacing the redundant memory cell groups with other memory cell groups 1 to 7 Assign redundant selection signals one by one.
- the redundancy selection signal generation method shown in Fig. 6 the case has been described in which the redundancy selection signal is assigned with priority to a specific redundancy setting.
- the power of assigning 1-bit inverted data so that the redundancy setting can be determined even if only 1 bit is inverted in the redundancy selection signal assigned to that redundancy setting.
- the redundant setting may be determined even if the 2 bits are inverted.
- FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in the case where 2-bit inverted data is further assigned to a specific redundancy setting.
- this redundant selection signal generation algorithm first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S301). For example, if it is a redundant selection variable force bit, set “0000”.
- 1-bit inverted data obtained by inverting only 1 bit of the data variable and 2-bit inverted data obtained by inverting 2 bits are created (step S302).
- the redundancy selection signal is 4 bits
- four types of 1-bit inverted data of “0001”, “0010”, “0100”, and “1000”, “0011”, “0101”, “ A total of 10 inverted data consisting of 6 2-bit inverted data of “0110”, “1001”, “1010” and “1100” is created.
- the data variable is assigned to the redundancy selection signal (step S303), and the data variable, the 1-bit inverted data and the 2-bit inverted data of the data variable are all registered in the used list (step S303). S304).
- step S305 1 is added to the data variable to make this a new data variable.
- step S305 the new data variable is compared with the used list (step S306). If the used list already contains data with the same value as the relevant data variable (step S307, Yes), the data variable will be the maximum value represented by the given number of bits (eg “1111”). It is determined whether or not there is (step S311).
- step S311, Yes If the data variable is equal to the maximum value represented by the given number of bits (eg, "1111") (step S311, Yes), until the required number is satisfied for the data variable, The 2-bit inverted data in the used list is assigned to the redundancy selection signal (step S312). On the other hand, if the data variable is weak at the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated. If the used list does not contain data with the same value as the data variable (Step S307, No), the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).
- the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).
- step S310, Yes when the necessary number of redundant selection signals are assigned to the data variable (step S310, Yes), the process is terminated. If the required number is not satisfied (step S310, No), it is determined whether or not the data variable is the maximum value represented by the given number of bits.
- step S311, Yes If the data variable has the maximum value (step S311, Yes), the 2-bit inverted data in the used list is assigned to the redundant selection signal until the required number is satisfied (step S312). On the other hand, when the data variable is weak at the maximum value (step S311, No), the process returns to step S305 to set a new data variable and repeats the processing after step S306.
- Redundancy settings are assigned using the redundancy selection signal generated by the above algorithm and the 1-bit inverted data and 2-bit inverted data of the redundancy selection signal with all bits being “0”.
- FIG. 9 is a diagram showing an example in which redundant selection signals remaining for a specific redundant setting are further allocated.
- a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, a redundancy selection signal with all bits set to “0”, all 1-bit inverted data, and 2-bit inverted data.
- Memory cells that are assigned to the redundant selection signal. Redundant selection signals are assigned to each of the seven redundancy settings that replace redundant memory cell groups with groups 1-7.
- FIG. 10 is a diagram showing an example of a redundant decoding circuit based on the redundant setting shown in FIG.
- the redundant decoding circuit of the example shown in the figure also consists of four inverter circuits, seven AND circuits, and six OR circuit powers.
- This redundant decode circuit outputs 7-bit redundant decode signals SEL0 to SEL6 in response to 4-bit redundant select signals RED0 to RED3.
- the redundant decode signals SEL0 to SEL6 output by decoding the 4-bit redundancy selection signals RED0 to RED3 are "0000000", “1111111”, “1111110”, “1111 100", “1111000”, There are 8 types of “1110000”, “1100000” and “1000000”. Each of these redundant decode signals SEL0 to SEL6 is associated with eight redundancy settings. Then, based on these redundant decode signals SEL0 to SEL6, the redundant setting of the memory cell group is performed by the redundant switch circuit.
- the redundancy setting latch 5 to 5 force memory cell group
- the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the group is held in advance, and the redundancy selection circuit 21 inverts even when a part of the redundancy selection signal is inverted by inputting this redundancy selection signal.
- the redundancy setting same as the redundancy setting associated with the previous redundancy selection signal is derived, and the redundancy switch circuit 22 replaces the memory cell group based on the derived redundancy setting.
- the redundancy selection signal held in the redundancy setting latches 5 to 5 caused a soft error due to
- the redundancy selection device and the redundancy selection method according to the present invention are useful for a semiconductor memory device that performs redundancy selection in which a defective memory cell is replaced with a redundancy memory cell, and in particular, controls redundancy selection such as a redundancy selection signal.
- LSI such as DSP (Digital Signal Processor) and SOC (System On Chip).
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- Static Random-Access Memory (AREA)
Abstract
A memory-redundancy selecting device comprises redundant setting latches (51-5n) to hold beforehand redundancy-selecting signals corresponding to redundant sets indicative of replacing patterns of memory cell groups, a redundancy decode circuit (21) to derive the same redundant sets as those corresponding to the redundancy-selecting signals before the signals are reversed even when the redundancy selecting signals are input and a part of them is reversed, and a redundant switch circuit (22) to replace the memory cell groups based on derived redundancy sets.
Description
明 細 書 Specification
メモリ冗長選択装置、記憶装置、情報処理装置およびメモリセルの冗長 選択の方法 Memory redundancy selection device, storage device, information processing device, and memory cell redundancy selection method
技術分野 Technical field
[0001] 本発明は、プロセサ等の LSIに内蔵される RAMなどの半導体記憶装置において 不良メモリセルを冗長メモリセルで置き換える冗長選択を行うメモリ冗長選択装置、記 憶装置、情報処理装置およびメモリセルの冗長選択の方法に関し、特に、冗長選択 におけるソフトエラー耐性を向上することができるメモリ冗長選択装置、記憶装置、情 報処理装置およびメモリセルの冗長選択の方法に関するものである。 The present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell for performing redundancy selection in which a defective memory cell is replaced with a redundant memory cell in a semiconductor storage device such as a RAM built in an LSI such as a processor In particular, the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell redundancy selection method that can improve soft error tolerance in redundancy selection.
背景技術 Background art
[0002] 従来、キャッシュメモリとして RAMなどの半導体記憶装置を内蔵するプロセサゃ D SP(Digital Signal Processor), SOC(System On Chip)等の LSIにおいては、製造 不良に備え、冗長メモリセルと呼ばれる予備のメモリセルを半導体チップ上に搭載し ておき、出荷前の試験などで不良なメモリセルが検知された場合は、不良メモリセル と冗長メモリセルを置き換えることによって、不良メモリセルを救済する技術 (以降、冗 長選択と呼ぶ。)が用いられている。 Conventionally, a processor incorporating a semiconductor memory device such as a RAM as a cache memory has a spare memory cell called a redundant memory cell in preparation for a manufacturing failure in an LSI such as a DSP (Digital Signal Processor) or SOC (System On Chip). Technology to relieve defective memory cells by replacing defective memory cells and redundant memory cells when defective memory cells are detected in tests prior to shipment. In the following, this is called redundancy selection).
[0003] この不良メモリセルを置き換える方法として、半導体チップ上に配置されたヒューズ を切断することにより不良メモリセルのアドレスを設定し、メモリセルを切り替えるため の回路を用いて当該アドレスによって示される不良メモリセルを冗長メモリセルに切り 替える技術が考案されている (例えば、特許文献 1参照。 ) o [0003] As a method for replacing this defective memory cell, the address indicated by the defective memory cell is set by switching a memory cell by setting an address of the defective memory cell by cutting a fuse arranged on a semiconductor chip. A technique for switching a memory cell to a redundant memory cell has been devised (for example, see Patent Document 1) o
[0004] このように、不良メモリセルを冗長メモリセルに置き換えるための信号 (以降、冗長選 択信号と呼ぶ。)を用いてメモリセルの置き換えを行う場合、この信号は、ヒューズから メモリセルの置き換えを行うための回路 (以降、冗長選択回路と呼ぶ。)に直接入力さ れることもあるが、複雑な配線を避けるため、チップ上に配置したスキャンラッチにより 構成されるスキャンチェーンを経て入力されることもある。 In this way, when a memory cell is replaced using a signal for replacing a defective memory cell with a redundant memory cell (hereinafter referred to as a redundant selection signal), this signal is sent from the fuse to the memory cell. Although it may be input directly to a circuit for replacement (hereinafter referred to as a redundancy selection circuit), it is input via a scan chain composed of scan latches arranged on the chip to avoid complicated wiring. Sometimes.
[0005] 図 11は、従来のメモリセルの冗長選択の一例を示す図である。同図に示す RAM マクロは、 3つのメモリセルグループ 1〜3と、 1つの冗長メモリセルグループ(予備のメ
モリセルグループ)と、冗長選択回路とから構成されることによりメモリセルを構成して いる。また、メモリセルグループ 1〜3と冗長メモリセルグループは、それぞれ読出回 路と書込回路とを有する。ここで、冗長選択回路は、書込データの書込み先であるメ モリセルグループの書込回路の選択及び読出データの読出し先であるメモリセルグ ループの読出回路の選択を行うことにより、メモリセルグループと冗長メモリセルグル ープとの切り替えを行う冗長スィッチ回路と、冗長選択信号のデコードを行う冗長デ コード回路とから構成されている。 FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells. The RAM macro shown in the figure includes three memory cell groups 1 to 3 and one redundant memory cell group (reserved memory group). A memory cell is composed of a memory cell group) and a redundancy selection circuit. The memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit. Here, the redundancy selection circuit selects the memory cell group as a write destination of the write data and selects the read circuit of the memory cell group as the read destination of the read data. It consists of a redundant switch circuit that switches between redundant memory cell groups and a redundant decoding circuit that decodes redundant selection signals.
[0006] 出荷前の試験などにより、 3つのメモリセルグループのうち、不良メモリセルを含む 不良メモリセルグループを検知した場合は、冗長スィッチ回路が、当該不良メモリセ ルグループを冗長メモリセルグループに切り替え (冗長選択)を行う。この際、冗長ス イッチ回路は、冗長デコード回路を介して入力される冗長選択信号に応じて、メモリ セルグループの切り替えを行う。また、冗長選択信号は、冗長設定用ラッチに保持さ れている。 [0006] If a defective memory cell group including a defective memory cell is detected among the three memory cell groups by a test before shipment, the redundant switch circuit switches the defective memory cell group to the redundant memory cell group. Perform (redundant selection). At this time, the redundant switch circuit switches the memory cell groups in accordance with the redundant selection signal input via the redundant decoding circuit. The redundancy selection signal is held in the redundancy setting latch.
[0007] ここで、図 11 (a)および(b)に示す例の RAMマクロでは、不良メモリセルグループ が存在するために 3つのメモリセルグループの!/、ずれかを冗長メモリセルグループと 交換する場合と、不良メモリセルグループが存在しな 、ために交換を行わな ヽ (冗長 選択しない)場合を含み、 4通りの冗長設定が考えられる。 [0007] Here, in the RAM macro of the example shown in FIGS. 11 (a) and 11 (b), because there is a defective memory cell group, the! /, Shift between the three memory cell groups is replaced with a redundant memory cell group. There are four types of redundancy settings, including the case where the faulty memory cell group does not exist and the case where the replacement is not performed (redundancy is not selected).
[0008] また、ここでは、それぞれの冗長選択信号によって 4通りの冗長設定がデコードでき るように、 2ビットの冗長選択信号を用いて冗長設定を定義する。図 12は、従来のメ モリセルの冗長選択における冗長選択信号の一例を示す図である。同図に示すよう に、 2ビットの冗長選択信号に「0」と「1」の組み合わせによって値を設定し、 4通りの 冗長設定をそれぞれ割り当てる。 [0008] Here, the redundancy setting is defined using a 2-bit redundancy selection signal so that four redundancy settings can be decoded by each redundancy selection signal. FIG. 12 is a diagram illustrating an example of a redundancy selection signal in the redundancy selection of a conventional memory cell. As shown in the figure, a 2-bit redundancy selection signal is set by a combination of “0” and “1”, and four redundancy settings are assigned to each.
[0009] 図 11 (a)に示す例では、メモリセルグループ 1〜3に不良なメモリセルを含むメモリ セルグループが無いため、冗長選択信号として「00」が入力される。冗長設定用ラッ チには、冗長選択信号「00」が保持されている。冗長デコード回路により、当該冗長 選択信号「00」がデコードされるが、冗長スィッチ回路は冗長メモリセルグループへ の切り替えは行わない。 In the example shown in FIG. 11 (a), since there is no memory cell group including a defective memory cell in memory cell groups 1 to 3, “00” is input as a redundancy selection signal. A redundancy selection signal “00” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “00”, but the redundancy switch circuit does not switch to the redundancy memory cell group.
[0010] また、図 11 (b)に示す例では、メモリセルグループ 2が不良なメモリセルであるため
、冗長選択信号として「10」が入力される。冗長設定用ラッチには、冗長選択信号「1 0」が保持されている。冗長デコード回路により、当該冗長選択信号「10」がデコード され、冗長スィッチ回路により冗長メモリセルグループへの切り替えが行われる。 [0010] Further, in the example shown in FIG. 11B, the memory cell group 2 is a defective memory cell. Then, “10” is input as the redundancy selection signal. A redundancy selection signal “1 0” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “10”, and the redundancy switch circuit switches to the redundancy memory cell group.
[0011] 図 13は、従来の冗長選択回路の一例を示す図である。同図(a)は、冗長スィッチ 回路の一例を示しており、同図 (b)は、冗長デコード回路の一例を示している。また、 図 14は、図 13に示した冗長スィッチ回路および冗長デコード回路が生成する信号 の一覧を示す図である。 FIG. 13 is a diagram illustrating an example of a conventional redundancy selection circuit. FIG. 2A shows an example of a redundant switch circuit, and FIG. 2B shows an example of a redundant decode circuit. FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG.
[0012] 図 13 (b)〖こ示すように、冗長デコード回路は、 2つのインバータ回路と、 3つの AND 回路と、 2つの OR回路力も構成されている。この冗長デコード回路は、 2ビットの冗長 選択信号 RED0〜RED1に応じて、図 14に示すように冗長スィッチ回路に対するセ レクト信号となる 3ビットの冗長デコード信号 SEL0〜SEL2を出力する。 [0012] As shown in FIG. 13 (b), the redundant decoding circuit includes two inverter circuits, three AND circuits, and two OR circuit forces. This redundant decode circuit outputs 3-bit redundant decode signals SEL0 to SEL2, which are select signals for the redundant switch circuit, as shown in FIG. 14, in response to 2-bit redundant selection signals RED0 to RED1.
[0013] また、図 13 (a)に示すように、冗長スィッチ回路は、 3つの NAND回路の組み合わ せ回路により構成される 3組の AND— OR等価回路の組み合わせで構成されている 。この冗長スィッチ回路は、冗長デコード回路が出力したセレクト信号である冗長デコ ード信号 SEL0〜SEL2に応じて、図 14に示すようにメモリセルグループ ARRAY0 〜ARRAY2および冗長メモリセルグループ ARRAYRと、出力端子 OUT0〜OUT 2との接続を切り替える。 In addition, as shown in FIG. 13 (a), the redundant switch circuit is configured by a combination of three sets of AND-OR equivalent circuits configured by a combination circuit of three NAND circuits. This redundant switch circuit includes memory cell groups ARRAY0 to ARRAY2 and redundant memory cell group ARRAYR as shown in FIG. Switches the connection with OUT0 to OUT2.
[0014] 特許文献 1 :特開 2005— 149667号公報 Patent Document 1: Japanese Patent Application Laid-Open No. 2005-149667
発明の開示 Disclosure of the invention
発明が解決しょうとする課題 Problems to be solved by the invention
[0015] し力しながら、上述したメモリセルの冗長選択において、宇宙から地球に降り注ぐ a 線 (ヘリウム (He)原子核)などの影響によって、ラッチに保持された冗長選択信号に ソフトエラーが発生した場合、すなわち、冗長選択信号の設定値がビット単位で反転 してしまった場合は、メモリセルの冗長選択が正しく行われないという問題がある。 However, in the redundancy selection of the memory cell described above, a soft error occurred in the redundancy selection signal held in the latch due to the influence of a-line (helium (He) nucleus) falling from the universe to the earth. In this case, that is, when the setting value of the redundancy selection signal is inverted in bit units, there is a problem that the redundancy selection of the memory cell is not performed correctly.
[0016] 本発明は、上述した従来技術による問題点を解消するためになされたものであり、 冗長選択におけるソフトエラー耐性を向上することができる冗長選択装置および冗長 選択方法を提供することを目的とする。 [0016] The present invention has been made to solve the above-described problems caused by the prior art, and an object thereof is to provide a redundancy selection device and a redundancy selection method that can improve soft error resistance in redundancy selection. And
課題を解決するための手段
[0017] 上述した課題を解決し、目的を達成するため、本発明の冗長選択装置は、記憶装 置を構成するメモリセルと冗長メモリセルとに接続され、前記メモリセル又は前記冗長 メモリセルの何れかの入出力を選択する冗長選択を行う冗長選択装置であって、前 記メモリセルの選択情報を示す冗長選択信号を保持する冗長選択信号保持手段と、 前記冗長選択情報保持手段に保持された前記冗長選択信号を入力して、前記冗長 選択信号の一部が反転していた場合においても反転する前と同じ冗長設定をデコー ド結果として出力を行う冗長デコード手段と、前記デコード結果に基づいて、前記メ モリセル又は前記冗長メモリセルの何れかの入出力の選択を行う冗長スィッチ手段と 、を備えたことを特徴とする。 Means for solving the problem In order to solve the above-described problems and achieve the object, the redundancy selection device of the present invention is connected to a memory cell and a redundancy memory cell constituting a storage device, and the memory cell or the redundancy memory cell A redundancy selection device for performing redundancy selection for selecting any one of input and output, the redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell, and held in the redundancy selection information holding means A redundant decoding means for inputting the redundant selection signal and outputting the same redundant setting as a decoding result even when part of the redundant selection signal is inverted, based on the decoding result; And redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.
[0018] また、本発明の冗長選択装置における前記冗長選択信号保持手段は、スキャンラ ツチ手段により構成されることを特徴とする。 [0018] Further, the redundant selection signal holding means in the redundant selection device of the present invention is characterized by comprising a scan latch means.
[0019] また、本発明の冗長選択装置における冗長デコード手段は、前記冗長選択信号を デコードする場合において、デコード結果として出力する同一の冗長設定について、 少なくとも二以上の冗長選択信号が入力として対応付けられるように構成されることを 特徴とする。 [0019] Further, the redundancy decoding means in the redundancy selection device of the present invention associates at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result when decoding the redundancy selection signal. It is characterized by being configured.
[0020] また、本発明の冗長選択装置における冗長選択信号は nビット (n> 1)で構成され 、前記冗長デコード手段は、前記冗長選択信号を構成する nビットのうち kビット (0< k≤n— 1)までが反転していた場合においても反転する前と同じ冗長設定をデコード 結果として出力を行うことを特徴とする。 [0020] Further, the redundancy selection signal in the redundancy selection device of the present invention is composed of n bits (n> 1), and the redundancy decoding means includes k bits (0 <k) of the n bits constituting the redundancy selection signal. Even when ≤n—1) is inverted, the same redundancy setting as before the inversion is output as a decoding result.
[0021] また、本発明の記憶装置は、メモリセルと、冗長メモリセルと、前記メモリセルと前記 冗長メモリセルとに接続され、前記メモリセル又は前記冗長メモリセルの何れかの入 出力を選択する冗長選択を行う冗長選択手段とを有し、前記冗長選択手段は、前記 メモリセルの選択情報を示す冗長選択信号を保持する冗長選択信号保持手段と、前 記冗長選択情報保持手段に保持された前記冗長選択信号を入力して、前記冗長選 択信号の一部が反転していた場合においても反転する前と同じ冗長設定をデコード 結果として出力を行う冗長デコード手段と、前記デコード結果に基づいて、前記メモリ セル又は前記冗長メモリセルの何れかの入出力の選択を行う冗長スィッチ手段と、を 備えたことを特徴とする。
[0022] また、本発明の情報処理装置は、メモリセルと、冗長メモリセルと、前記記憶装置に 接続される演算処理装置と、前記メモリセルと前記冗長メモリセルとに接続され、前記 メモリセル又は前記冗長メモリセルの何れかの入出力を選択する冗長選択を行う冗 長選択手段とを有し、前記冗長選択手段は、前記メモリセルの選択情報を示す冗長 選択信号を保持する冗長選択信号保持手段と、前記冗長選択情報保持手段に保 持された前記冗長選択信号を入力して、前記冗長選択信号の一部が反転して!/ヽた 場合においても反転する前と同じ冗長設定をデコード結果として出力を行う冗長デコ ード手段と、前記デコード結果に基づいて、前記メモリセル又は前記冗長メモリセル の何れかの入出力の選択を行う冗長スィッチ手段と、を備えたことを特徴とする。 In addition, the memory device of the present invention is connected to the memory cell, the redundant memory cell, the memory cell and the redundant memory cell, and selects either the memory cell or the redundant memory cell. Redundancy selection means for performing redundancy selection, and the redundancy selection means is held in a redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell and in the redundancy selection information holding means. In addition, when the redundant selection signal is input and a part of the redundant selection signal is inverted, redundant decoding means for outputting the same redundancy setting as before decoding as a decoding result, and based on the decoding result And redundant switch means for selecting input / output of either the memory cell or the redundant memory cell. [0022] The information processing apparatus according to the present invention includes a memory cell, a redundant memory cell, an arithmetic processing unit connected to the storage device, the memory cell and the redundant memory cell, and the memory cell Or redundancy selection means for performing redundancy selection for selecting any input / output of the redundant memory cell, wherein the redundancy selection means holds a redundancy selection signal indicating selection information of the memory cell. When the redundancy selection signal held in the holding means and the redundancy selection information holding means is inputted, and the part of the redundancy selection signal is inverted! Redundant decoding means for outputting as a decoding result, and redundant switching means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result. The features.
[0023] また、本発明の情報処理装置はさらに、スキャンシフト制御を行う TAPコントローラ 手段と、前記 TAPコントローラ手段から出力されるスキャンクロックによりスキャンシフ トを行い、前記冗長選択信号保持手段を含むスキャンラッチ手段と、前記スキャンラ ツチ手段に接続され、冗長選択信号を設定するヒューズ手段とを有し、前記ヒューズ 手段に設定された冗長選択信号を前記スキャンラッチ手段に出力し、前記スキャンシ フトを行うことにより、前記冗長選択信号保持手段に前記冗長選択信号を保持するこ とを特徴とする。 [0023] Further, the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit. Latch means and fuse means connected to the scan latch means for setting a redundancy selection signal, outputting the redundancy selection signal set in the fuse means to the scan latch means, and performing the scan shift. Thus, the redundancy selection signal is held in the redundancy selection signal holding means.
[0024] また、本発明の情報処理装置はさらに、スキャンシフト制御を行う TAPコントローラ 手段と、前記 TAPコントローラ手段から出力されるスキャンクロックによりスキャンシフ トを行い、前記冗長選択信号保持手段を含むスキャンラッチ手段と、前記スキャンラ ツチ手段に接続されるスキャン入力とを有し、前記スキャン入力から前記冗長選択信 号を入力し、前記スキャンシフトを行うことにより、前記冗長選択信号保持手段に前記 冗長選択信号を保持することを特徴とする。 [0024] Further, the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit. The redundancy selection signal holding means includes the latch means and a scan input connected to the scan latch means, and inputs the redundancy selection signal from the scan input and performs the scan shift, so that the redundancy selection signal is held in the redundancy selection signal holding means. It is characterized by holding a signal.
[0025] また、本発明の冗長選択の方法は、記憶装置を構成するメモリセル又は冗長メモリ セルの何れかの入出力を選択するメモリセルの冗長選択の方法であって、前記メモリ セルの選択情報を示す冗長選択信号を保持するステップと、前記保持された前記冗 長選択信号を入力して、前記冗長選択信号の一部が反転して!/、た場合にお!ヽても 反転する前と同じ冗長設定をデコード結果として出力を行うステップと、前記デコード 結果に基づいて、前記メモリセル又は前記冗長メモリセルの何れかの入出力の選択
を行うステップと、を備えたことを特徴とする。 [0025] The redundancy selection method of the present invention is a memory cell redundancy selection method for selecting input / output of either a memory cell or a redundant memory cell constituting a storage device, wherein the selection of the memory cell is performed. A step of holding a redundant selection signal indicating information and a case where the held redundant selection signal is input and a part of the redundant selection signal is inverted! /! The step of outputting the same redundancy setting as the decoding result even before inversion, and the selection of the input / output of either the memory cell or the redundant memory cell based on the decoding result And a step of performing.
[0026] また、本発明の冗長選択の方法は、前記保持された前記冗長選択信号を入力して 、前記冗長選択信号の一部が反転していた場合においても反転する前と同じ冗長設 定をデコード結果として出力を行う前記ステップにおいて、デコード結果として出力す る同一の冗長設定について、少なくとも二以上の冗長選択信号が入力として対応付 けられることを特徴とする。 [0026] Further, in the redundancy selection method according to the present invention, even when the retained redundancy selection signal is input and a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is performed. In the step of outputting as a decoding result, at least two or more redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.
発明の効果 The invention's effect
[0027] 本発明によれば、メモリセルの置き換えパターンを示す冗長設定に対応付けられた 冗長選択信号をあらかじめ保持し、この冗長選択信号を入力して冗長選択信号の一 部が変化していた場合でも変化する前と同じ冗長設定を導出し、導出した冗長設定 に基づ!/、てメモリセルの置き換えを行うよう構成したので、宇宙からの放射線などの 影響で保持している冗長選択信号にソフトエラーが発生していた場合でも、正しく冗 長選択を行うことができるため、冗長選択におけるソフトエラー耐性を向上することが できるという効果を奏する。 [0027] According to the present invention, the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell is held in advance, and a part of the redundancy selection signal is changed by inputting the redundancy selection signal. Even in this case, the same redundancy setting as before the change was derived, and based on the derived redundancy setting! /, The memory cell was replaced, so the redundancy selection signal held by the influence of radiation from space, etc. Even if a soft error occurs, the redundancy selection can be performed correctly, so that the soft error tolerance in the redundant selection can be improved.
[0028] また、本発明によれば、冗長選択信号を nビット (n> 1)で構成し、この冗長選択信 号を構成する nビットのうち kビット (0<k≤n— 1)までが反転していた場合でも反転 する前の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導出するよう構 成したので、保持している冗長選択信号にソフトエラーが発生していた場合でも、冗 長選択信号を構成する nビットのうち kビット (0<k≤n— 1)までが反転していた場合 は正しく冗長選択を行うことができるため、冗長選択におけるソフトエラー耐性を向上 することができると!/、う効果を奏する。 [0028] Further, according to the present invention, the redundancy selection signal is composed of n bits (n> 1), and k bits (0 <k≤n—1) of n bits constituting the redundancy selection signal. Even if is reversed, it is configured to derive the same redundancy setting as that associated with the redundancy selection signal before the inversion, so that a soft error has occurred in the retained redundancy selection signal However, if k bits (0 <k≤n—1) of n bits that make up the redundancy selection signal are inverted, the redundancy selection can be performed correctly, improving the soft error tolerance in the redundancy selection. If you can!
[0029] また、本発明によれば、冗長選択信号を構成する nビット (η> 1)のうち所定のビット につ 、て kビット(0< k≤n— 1)までが反転して 、た場合でも反転する前の冗長選択 信号に対応付けられた冗長設定と同じ冗長設定を導出するよう構成したので、反転 していても同じ冗長設定が導出できるビットを限定することによって、冗長選択信号に 用いることができるビット数が制限されている場合でも、冗長選択におけるソフトエラ 一耐性を向上することができるという効果を奏する。 [0029] Further, according to the present invention, k bits (0 <k≤n-1) are inverted with respect to a predetermined bit among n bits (η> 1) constituting the redundancy selection signal, In this case, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived, so that the redundancy selection signal can be determined by limiting the bits from which the same redundancy setting can be derived even if it is inverted. Even when the number of bits that can be used for the selection is limited, the soft error tolerance in redundancy selection can be improved.
[0030] また、本発明によれば、特定の冗長設定につ!ヽては冗長選択信号を構成する nビ
ット (n> 1)のうち kビット (0<k≤n— 1)までが反転して 、た場合でも反転する前の冗 長選択信号に対応付けられた冗長設定と同じ冗長設定を導出するよう構成したので 、複数の冗長設定の中で、実際に設定される確率が高い冗長設定について重点的 に冗長選択におけるソフトエラーの耐性を向上することができるという効果を奏する。 [0030] Further, according to the present invention, for a specific redundancy setting, there are n signals that constitute a redundancy selection signal. Inverting up to k bits (0 <k≤n—1) in a set (n> 1), the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. As a result, it is possible to improve the resistance to soft errors in the redundant selection with a focus on the redundant setting having a high probability of being actually set among a plurality of redundant settings.
[0031] また、本発明によれば、メモリセルの置き換えを行わない冗長設定については冗長 選択信号を構成する nビット (n> 1)のうち kビット(0<k≤n— 1)までが反転して 、た 場合でも反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を 導出するよう構成したので、実際に設定される確率が高い、メモリセルの置き換えを 行わない冗長設定について重点的に冗長選択におけるソフトエラーの耐性を向上す ることができると!/、う効果を奏する。 In addition, according to the present invention, with respect to the redundant setting in which the memory cell is not replaced, up to k bits (0 <k≤n—1) out of n bits (n> 1) constituting the redundancy selection signal. Even if it is inverted, it is configured to derive the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion, so there is a high probability that it will actually be set, and redundancy that does not replace the memory cell It is possible to improve the tolerance of soft errors in redundant selection with emphasis on setting!
[0032] また、本発明によれば、冗長選択信号を構成する nビット (η> 1)のうちいずれかの 1ビットが反転していた場合でも反転する前の冗長選択信号に対応付けられた冗長 設定と同じ冗長設定を導出するよう構成したので、保持している冗長選択信号にソフ トエラーが発生していた場合でも、冗長選択信号を構成する nビットのうちいずれか 1 ビットが反転していた場合は、正しく冗長選択を行うことができるため、冗長選択にお けるソフトエラー耐性を向上することができるという効果を奏する。 [0032] Further, according to the present invention, even when any one bit of n bits (η> 1) constituting the redundant selection signal is inverted, it is associated with the redundant selection signal before being inverted. Since the same redundancy setting as the redundancy setting is derived, even if a soft error has occurred in the retained redundancy selection signal, one of the n bits that make up the redundancy selection signal is inverted. In such a case, since the redundant selection can be performed correctly, the soft error resistance in the redundant selection can be improved.
[0033] また、本発明によれば、特定の冗長設定につ!ヽては前記冗長選択信号を構成する nビット (n> 1)のうちいずれかの 1ビットが反転していた場合でも反転する前の冗長 選択信号に対応付けられた冗長設定と同じ冗長設定を導出するよう構成したので、 複数の冗長設定の中で、実際に設定される確率が高い冗長設定について重点的に 冗長選択におけるソフトエラーの耐性を向上することができるという効果を奏する。 [0033] Further, according to the present invention, for a specific redundancy setting, even if one of the n bits (n> 1) constituting the redundancy selection signal is inverted, it is inverted. Since the redundant setting that is the same as the redundant setting associated with the redundant selection signal before the configuration is derived, the redundant setting that has a high probability of being actually set is selected among the redundant settings. There is an effect that resistance to soft errors can be improved.
[0034] また、本発明によれば、メモリセルの置き換えを行わな 、冗長設定にっ 、ては前記 冗長選択信号を構成する nビット (n> 1)のうちいずれかの 1ビットが反転していた場 合でも反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導 出するよう構成したので、実際に設定される確率が高い、メモリセルの置き換えを行 わない冗長設定について重点的に冗長選択におけるソフトエラーの耐性を向上する ことができると!/、う効果を奏する。 Further, according to the present invention, without replacing a memory cell, one bit out of n bits (n> 1) constituting the redundancy selection signal is inverted by redundancy setting. Even if it is, the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived, so there is a high probability that it will actually be set, and the redundancy that does not replace the memory cell If you can improve the tolerance of soft errors in the redundant selection with emphasis on the setting!
図面の簡単な説明
[0035] [図 1]図 1は、本実施例に係る冗長選択の概要を説明するための説明図である。 Brief Description of Drawings FIG. 1 is an explanatory diagram for explaining an outline of redundancy selection according to the present embodiment.
[図 2]図 2は、本実施例に係る RAMマクロの構成を示すブロック図である。 FIG. 2 is a block diagram showing a configuration of a RAM macro according to the present embodiment.
[図 3]図 3は、本実施例に係る冗長設定の一例を示す図である。 FIG. 3 is a diagram illustrating an example of redundancy setting according to the present embodiment.
[図 4]図 4は、図 3に示した冗長選択信号を生成するアルゴリズムを示すフローチヤ一 トである。 FIG. 4 is a flowchart showing an algorithm for generating the redundant selection signal shown in FIG.
[図 5]図 5は、 1つの冗長設定に 2つの冗長選択信号を割り当てる場合の一例を示す 図である。 FIG. 5 is a diagram showing an example of assigning two redundancy selection signals to one redundancy setting.
[図 6]図 6は、特定の冗長設定に重点的に冗長選択信号を割り当てる場合の冗長選 択信号生成アルゴリズムを示すフローチャートである。 [FIG. 6] FIG. 6 is a flowchart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a specific redundancy setting with priority.
[図 7]図 7は、特定の冗長設定に重点的に冗長選択信号を割り当てる場合の一例を 示す図である。 [FIG. 7] FIG. 7 is a diagram showing an example in which a redundancy selection signal is assigned to a specific redundancy setting.
[図 8]図 8は、特定の冗長設定に 2桁反転データをさらに割り当てる場合の冗長選択 信号生成アルゴリズムを示すフローチャートである。 [FIG. 8] FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in a case where 2-digit inversion data is further assigned to a specific redundancy setting.
[図 9]図 9は、特定の冗長設定に余った冗長選択信号をさらに割り当てる場合の一例 を示す図である。 [FIG. 9] FIG. 9 is a diagram showing an example in the case of further assigning redundant selection signals remaining in a specific redundancy setting.
[図 10]図 10は、図 9に示した冗長設定による冗長デコード回路の一例を示す図であ る。 FIG. 10 is a diagram showing an example of a redundancy decoding circuit with redundancy setting shown in FIG.
[図 11]図 11は、従来のメモリセルの冗長選択の一例を示す図である。 FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.
[図 12]図 12は、従来のメモリセルの冗長選択における冗長選択信号の一例を示す 図である。 FIG. 12 is a diagram showing an example of a redundancy selection signal in redundancy selection of a conventional memory cell.
[図 13]図 13は、従来の冗長選択回路の一例を示す図である。 FIG. 13 is a diagram showing an example of a conventional redundancy selection circuit.
[図 14]図 14は、図 13に示した冗長スィッチ回路および冗長デコード回路が生成する 信号の一覧を示す図である。 FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG. 13.
符号の説明 Explanation of symbols
[0036] 1 LSIチップ [0036] 1 LSI chip
2 2
1〜2 ヒューズ 1-2 fuse
5 Five
3 Three
1〜3 ラッチ列 1 to 3 latch rows
m m
4〜4 RAMマクロ
5〜5 冗長設定用ラッチ 4-4 RAM macro 5 to 5 Redundancy setting latch
1 n 1 n
6 プロセサコア部 6 Processor core
7 TAPコントローラ 7 TAP controller
10〜: LO メモリセルグループ 10 ~: LO memory cell group
1 3 13
10 冗長メモリセルグループ 10 Redundant memory cell group
4 Four
20 冗長選択回路 20 Redundant selection circuit
21 冗長デコード回路 21 Redundant decoding circuit
22 冗長スィッチ回路 22 Redundant switch circuit
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0037] 以下に添付図面を参照して、本発明に係る冗長選択装置および冗長選択方法の 好適な実施例を詳細に説明する。 Hereinafter, preferred embodiments of a redundancy selection device and a redundancy selection method according to the present invention will be described in detail with reference to the accompanying drawings.
実施例 Example
[0038] まず、本実施例に係る冗長選択の概要について説明する。図 1は、本実施例に係 る冗長選択の概要を説明するための説明図である。同図に示す LSIチップ 1には、 複数のヒューズ 2〜2と、複数のラッチ列 3〜3と、複数の RAMマクロ 4〜4と、複 First, an overview of redundancy selection according to the present embodiment will be described. FIG. 1 is an explanatory diagram for explaining an outline of redundant selection according to the present embodiment. The LSI chip 1 shown in the figure includes a plurality of fuses 2 to 2, a plurality of latch trains 3 to 3, a plurality of RAM macros 4 to 4, and a plurality of fuses.
1 5 1 m I n 数の RAMマクロをキャッシュメモリとして使用するプロセサコア部 6と、複数のラッチ 列のスキャン制御を行う TAP(Test Access Port)コントローラ 7が配置されている。 A processor core unit 6 that uses 1 5 1 m I n number of RAM macros as cache memory and a TAP (Test Access Port) controller 7 that controls scan of a plurality of latch rows are arranged.
[0039] ラッチ列 3〜3 は、それぞれ複数のスキャンラッチから構成されており、全てのラッ [0039] Each of the latch trains 3 to 3 includes a plurality of scan latches.
1 m 1 m
チ列 3〜3が数珠つなぎに接続され、スキャンラッチによるスキャンチェーンを構成 H-rows 3 to 3 are connected in a daisy chain to form a scan chain with a scan latch
1 m 1 m
している。また、ラッチ列 3にはヒューズ 2〜2力 ラッチ列 3には RAMマクロ 4〜4 is doing. Latch row 3 has fuse 2 to 2 force Latch row 3 has RAM macro 4 to 4
1 1 5 n 1 n がそれぞれ接続されている。さらに、当該スキャンチェーンは LSIチップ 1における外 部からの入力としてスキャン ·イン端子及び外部への出力としてスキャン ·アウト端子を 有する。例えば、当該スキャンチェーンの制御は IEEE1149. 1準拠による JTAGOoi nt Test Architecture Group)準拠の TAPコントローラ 7により行うことができる。 1 1 5 n 1 n are connected to each other. Further, the scan chain has a scan-in terminal as an input from the outside in the LSI chip 1 and a scan-out terminal as an output to the outside. For example, the scan chain can be controlled by a TAP controller 7 that is compliant with the JTAG Origin Test Architecture Group (compliant with IEEE 1149.1).
[0040] また、各 RAMマクロ 4〜4は、それぞれ、複数のメモリセルグループと、冗長メモリ [0040] Each of the RAM macros 4 to 4 includes a plurality of memory cell groups and a redundant memory.
1 n 1 n
セルグループ (予備のメモリセルグループ)と、冗長選択回路とを有している。各 RA Mマクロ 4〜4のメモリセルグループは、 LSIチップ 1の出荷前試験によって検査が It has a cell group (reserve memory cell group) and a redundancy selection circuit. The memory cell groups in each RAM macro 4-4 are inspected by pre-shipment testing of LSI chip 1.
1 n 1 n
行われる。この出荷前試験において、不良なメモリセルを含むメモリセルグループが
検出された場合は、不良メモリセルグループを冗長メモリセルグループで置き換える 設定 (冗長設定)が RAMマクロごとに行われる。 Done. In this pre-shipment test, a memory cell group containing defective memory cells If it is detected, the setting to replace the defective memory cell group with the redundant memory cell group (redundancy setting) is performed for each RAM macro.
[0041] カゝかる冗長設定は、冗長選択信号を用いて行われる。ここでいう冗長選択信号とは 、複数のメモリセルグループのうち、いずれを冗長メモリセルグループで置き換えるか を示す信号であり、ヒューズ 2〜2を切断することにより当該ヒューズから出力される「 [0041] The redundant setting is performed using a redundant selection signal. The redundant selection signal here is a signal indicating which one of the plurality of memory cell groups is to be replaced with the redundant memory cell group, and is output from the fuse when the fuses 2 and 2 are cut.
1 5 1 5
0」および「1」の信号を所定のビット数で組み合わせることによって生成される。 It is generated by combining signals of “0” and “1” with a predetermined number of bits.
[0042] このように生成された冗長選択信号は、ラッチ列 3のラッチに 1ビットずつ格納され、 [0042] The redundancy selection signal generated in this way is stored bit by bit in the latch of latch column 3,
1 1
TAPコントローラ 7からのスキャンクロック入力(図示せず)によって、スキャンチェーン (ラッチ列 3〜ラッチ列 3 )を経由してスキャンシフトされ、最終的にラッチ列 3 の冗長 A scan clock input (not shown) from the TAP controller 7 is scan-shifted via the scan chain (latch column 3 to latch column 3) and finally the redundancy of the latch column 3
1 m m 設定用ラッチ 5〜5に保持される。なお、冗長設定用ラッチ 5〜5は、それぞれ、冗 1 mm Hold for setting latch 5 ~ 5. Note that the redundancy setting latches 5 to 5 are respectively redundant.
1 n 1 n 1 n 1 n
長選択信号のビット数と同数のラッチ力 構成されている。 The latching force is the same as the number of bits of the long selection signal.
[0043] また、各 RAMマクロの冗長選択回路は、複数のメモリセルグループと、冗長メモリ セルグループと、ラッチ列 3の冗長設定用ラッチ 5〜5とに接続されている。そして、 m 1 n Further, the redundancy selection circuit of each RAM macro is connected to a plurality of memory cell groups, a redundancy memory cell group, and redundancy setting latches 5 to 5 in the latch column 3. And m 1 n
冗長選択回路は、冗長設定用ラッチ 5〜5に保持されている冗長選択信号を入力し The redundancy selection circuit inputs the redundancy selection signal held in the redundancy setting latches 5 to 5.
1 n 1 n
、入力した冗長選択信号の冗長デコード回路によるデコード結果に応じて不良なメ モリセルグループと冗長メモリセルグループとの置き換えを行う。 Then, the defective memory cell group and the redundant memory cell group are replaced according to the decoding result of the input redundancy selection signal by the redundancy decoding circuit.
[0044] なお、ここでは、ヒューズ 2〜2を切断することにより当該ヒューズから出力される信 [0044] Here, the signal output from the fuses 2 and 2 by cutting them is described here.
1 5 1 5
号を用いて冗長選択信号を生成する場合を説明したが、ヒューズ 2〜2 The redundant selection signal is generated using the
1 5を用いずに 1 Without 5
、スキャン 'イン端子力も直接冗長選択信号をスキャンシフトさせることによって生成し てもよい。 The scan-in terminal force may also be generated by directly scanning and shifting the redundant selection signal.
[0045] 次に、本実施例に係る RAMマクロの構成について説明する。図 2は、本実施例に 係る RAMマクロの構成を示すブロック図である。同図(a)および (b)に示すように、こ の RAMマクロにおける冗長選択回路 20は、 3つのメモリセルグループ 10〜10と、 Next, the configuration of the RAM macro according to the present embodiment will be described. FIG. 2 is a block diagram showing the configuration of the RAM macro according to the present embodiment. As shown in FIGS. 4A and 4B, the redundancy selection circuit 20 in this RAM macro includes three memory cell groups 10 to 10 and
1 3 13
1つの冗長メモリセルグループ 10に接続されている。また、メモリセルグループ 1〜3 One redundant memory cell group 10 is connected. Memory cell groups 1 to 3
4 Four
と冗長メモリセルグループは、それぞれ読出回路と書込回路とを有する。 Each redundant memory cell group has a read circuit and a write circuit.
[0046] また、冗長選択回路 20は、冗長選択信号のデコードを行う冗長デコード回路 21お よび、書込データの書込み先であるメモリセルグループの書込回路の選択及び読出 データの読出し先であるメモリセルグループの読出回路の選択を行うことにより、メモ
リセルグループと冗長メモリセルグループとの切り替えを行う冗長スィッチ回路 22から 構成されており、冗長スィッチ回路 22がメモリセルグループ 10〜10および冗長メモ Further, the redundancy selection circuit 20 is a redundancy decoding circuit 21 that decodes a redundancy selection signal, and a selection of a write circuit of a memory cell group that is a write destination of write data and a read destination of the read data. By selecting the readout circuit for the memory cell group, The redundant switch circuit 22 is configured to switch between the recell group and the redundant memory cell group. The redundant switch circuit 22 includes the memory cell groups 10 to 10 and the redundant memory circuit.
1 3 13
リセルグループ 10に接続され、冗長デコード回路 21が冗長設定用ラッチ 5〜5に Redundant decode circuit 21 connected to resell group 10 and redundant setting latches 5 to 5
4 1 n 接続されている。 4 1 n Connected.
[0047] 冗長デコード回路 21には、冗長設定用ラッチ 5〜5に保持されている冗長選択信 The redundancy decode circuit 21 has a redundancy selection signal held in the redundancy setting latches 5 to 5.
1 n 1 n
号が入力され、入力された冗長選択信号に基づ!、てメモリセルグループの冗長設定 を判定し、冗長スィッチ回路を制御するための冗長デコード信号を出力する。ここで 、本来、冗長設定用ラッチ 5〜5に設定されている冗長選択信号は、 1つの冗長設 Based on the inputted redundancy selection signal, the redundancy setting of the memory cell group is determined, and a redundancy decode signal for controlling the redundancy switch circuit is outputted. Here, the redundancy selection signal originally set in the redundancy setting latches 5 to 5 is one redundancy setting signal.
1 n 1 n
定を示しているはずである。しかし、冗長設定用ラッチ 5〜5にソフトエラーが発生し It should show that However, a soft error occurs in the redundancy setting latches 5-5.
1 n 1 n
た場合、本来保持していたはずの冗長選択信号の値が変化してしまい、そのため本 来行うべき冗長設定のためのデコードが正しく出力されなくなってしまうことがある。 In such a case, the value of the redundancy selection signal that should have been retained may change, so that decoding for redundancy setting that should be performed may not be output correctly.
[0048] そこで、冗長デコード回路 21は、冗長選択信号を構成している複数のビットのうち、 V、ずれか 1つのビットが反転してしまった場合でも、本来の冗長選択信号が示して!/ヽ た冗長設定を判定できるように構成する。以下に、この冗長設定の判定方法を説明 する。 [0048] Therefore, the redundancy decoding circuit 21 indicates that the original redundancy selection signal is indicated even if one of the bits constituting the redundancy selection signal is inverted, V, or one of the bits! / Configure so that redundant settings can be judged. The method for determining this redundancy setting is described below.
[0049] 図 3は、本実施例に係る冗長選択設定の一例を示す図である。本来、冗長設定に 必要なビット数が 2ビットであるところ、ソフトエラー耐性を向上させる目的のため、冗 長設定のビット幅をさらに増やしてデコードパターンを増やすことが考えられる。同図 に示すように、例えば、冗長設定信号のビット数を本来必要な 2ビットに対し 3ビット増 やして 5ビットとした場合は、各冗長設定に対して、まずは冗長設定用ラッチに設定 するための 1つの冗長選択信号を割り当てる。 FIG. 3 is a diagram illustrating an example of the redundant selection setting according to the present embodiment. Originally, the number of bits required for redundant setting is 2 bits, but in order to improve soft error tolerance, it is possible to further increase the bit width of redundant setting and increase the decoding pattern. As shown in the figure, for example, if the number of bits of the redundancy setting signal is increased by 3 bits from the originally required 2 bits to 5 bits, each redundancy setting is first set in the redundancy setting latch. Assign one redundant selection signal to
[0050] 図 2に示す例では、メモリセルグループ 10〜10のいずれか一つを冗長メモリセル In the example shown in FIG. 2, any one of the memory cell groups 10 to 10 is a redundant memory cell.
1 3 13
グループ 10で置き換える場合と、冗長選択を行わない場合とで、 4通りの冗長設定 Four types of redundancy settings, when replacing with group 10 and when redundancy selection is not performed
4 Four
が考えられる。そこで、 4つの冗長選択信号について、「00000」は冗長選択を行わ ない場合に対して割当て、「00111」、「10111」および「11110」は冗長選択を行う 場合に対して割り当てる。 Can be considered. Therefore, among the four redundant selection signals, “00000” is assigned to the case where no redundant selection is performed, and “00111”, “10111” and “11110” are assigned to the case where redundant selection is performed.
[0051] そして、各冗長設定に対して、既に割り当てられている冗長選択信号のいずれか 1 ビットを反転することによって得られる 5つの値をさらに割り当てる。例えば、冗長選択
を行わな ヽ場合【こ対応する「00000」【こつ!ヽて ίま、「00001」、 「00010」、 「00100」 、「01000」及び「10000」の 5つの値を割り当てる。 [0051] Then, five values obtained by inverting any one bit of the already assigned redundancy selection signal are further assigned to each redundancy setting. For example, redundant selection If this is not done, assign the following five values: “00000”, “0000”, “00010”, “00100”, “01000”, and “10000”.
[0052] このようにして割り当てられた冗長選択信号と当該冗長選択信号の 1ビット反転デ ータに基づいて冗長設定をデコードすることによって、冗長選択回路 20は、冗長設 定用ラッチ 5〜5に保持している冗長選択信号にソフトエラーが発生していた場合で [0052] By decoding the redundancy setting based on the redundancy selection signal thus assigned and the 1-bit inverted data of the redundancy selection signal, the redundancy selection circuit 20 has the redundancy setting latches 5-5. If there is a soft error in the redundant selection signal held in
1 η 1 η
も、冗長選択信号を構成して 、るビットのうち 、ずれか 1ビットが反転して!/、た場合は 、正しく冗長選択を行うことができるため、冗長選択におけるソフトエラー耐性を向上 することができる。 However, if one of the bits in the redundant selection signal is inverted! /, The redundant selection can be performed correctly, so that the soft error resistance in the redundant selection can be improved. Can do.
[0053] また、冗長スィッチ回路 22は、冗長デコード回路 21がデコードした冗長設定に基 づ 、て不良メモリセルグループと冗長メモリセルグループ 10の置き換え(冗長選択) Further, the redundancy switch circuit 22 replaces the defective memory cell group and the redundancy memory cell group 10 based on the redundancy setting decoded by the redundancy decoding circuit 21 (redundancy selection).
4 Four
を行う。 I do.
[0054] 図 2 (a)に示す例では、不良なメモリセルグループが無力つた場合の冗長選択を示 している。同図においては、冗長設定用ラッチには冗長選択信号「00000」が設定さ れているため、冗長デコード回路 21により冗長選択しないと判定されるが、冗長選択 信号力 00001」、 「00010」、 「00100」、 「01000」または「10000」に変ィ匕していた 場合でも、同じく冗長デコード回路 21により冗長選択しないと判定される。 In the example shown in FIG. 2 (a), redundant selection is shown when a defective memory cell group is incapacitated. In the figure, since the redundancy selection signal “00000” is set in the redundancy setting latch, it is determined that the redundancy decoding circuit 21 does not select redundancy, but the redundancy selection signal power 00001 ”,“ 00010 ”, Even if it is changed to “00100”, “01000”, or “10000”, it is determined by the redundant decoding circuit 21 that redundant selection is not performed.
[0055] また、図 2 (b)に示す例では、メモリセルグループ 2に故障が発生した場合を示して いる。このようにメモリセルグループ 2に故障が発生した場合には、故障したメモリセ ルグループ 2を冗長セルグループに交換する必要がある。同図においては、冗長設 定用ラッチには冗長選択信号「11001」が設定されているため、メモリセルグループ 2 と冗長メモリセルグループを交換すると判定する力 冗長選択信号が「11000」、 「11 011」、 「11101」、 「10001」または「01001」に変化していた場合でも、メモリセルグ ループ 2と冗長メモリセルグループを交換すると判定される。 In the example shown in FIG. 2B, a case where a failure occurs in the memory cell group 2 is shown. Thus, when a failure occurs in memory cell group 2, it is necessary to replace the failed memory cell group 2 with a redundant cell group. In the figure, since the redundancy selection signal “11001” is set in the redundancy setting latch, the power redundancy selection signal is “11000”, “11” which is determined to replace the memory cell group 2 and the redundancy memory cell group. Even if it is changed to “011”, “11101”, “10001” or “01001”, it is determined that the memory cell group 2 and the redundant memory cell group are exchanged.
[0056] このように、冗長デコード回路 21が、冗長設定用ラッチ 5〜5に保持されている冗 In this way, the redundant decode circuit 21 is redundantly held in the redundancy setting latches 5 to 5.
1 n 1 n
長選択信号を入力し、入力した冗長選択信号が本来設定されて!ヽた値から変わって いた場合でも、 1ビットのみが反転した値であった場合は、本来設定されていた冗長 選択信号が示す冗長設定と同じであると判定することによって、冗長設定用ラッチ 5 Even if a long selection signal is input and the input redundancy selection signal is originally set and has changed from the previous value, if only one bit is inverted, the redundancy selection signal that was originally set is The redundancy setting latch is determined by determining that the redundancy setting is the same as
1 1
〜5にソフトエラーが発生して冗長選択信号の 1ビットが反転していた場合でも正しく
冗長選択を行うことができるため、冗長選択におけるソフトエラー耐性を向上すること ができる。 Even if a soft error occurs in ~ 5 and 1 bit of the redundancy selection signal is inverted Since redundant selection can be performed, it is possible to improve soft error tolerance in redundant selection.
[0057] ラッチ 1つ当たりのソフトエラー率を ser (Soft ERror)とすると、例えば、前述した 図 12の従来のメモリセルの冗長設定では、 1つの冗長設定に対して、 2ビットの冗長 選択信号を 1つずつ割り当てたので、冗長選択におけるソフトエラー率 SEROは、 [0057] When the soft error rate per latch is ser (Soft ERror), for example, in the redundancy setting of the conventional memory cell in FIG. 12 described above, a 2-bit redundancy selection signal is used for one redundancy setting. Are assigned one by one, so the soft error rate SERO in the redundant selection is
1 1
SERO = l - { (l -ser) 2} SERO = l-{(l -ser) 2 }
1 1
となる。 It becomes.
[0058] 一方、図 3で示した冗長設定では、 1つの冗長設定に対して、 5ビットの冗長選択信 号を 1つと、冗長選択信号の 1ビットを反転させた 5つの値とを割り当てたので、冗長 選択におけるソフトエラー率 SERNは、 On the other hand, in the redundancy setting shown in FIG. 3, one 5-bit redundancy selection signal and five values obtained by inverting the 1-bit redundancy selection signal are assigned to one redundancy setting. So, the soft error rate SERN in redundant selection is
1 1
SERN = 1— { (1— ser) 5 + 5 X (1 -ser) ' X ser} SERN = 1— {(1— ser) 5 + 5 X (1 -ser) 'X ser}
1 1
となる。 It becomes.
[0059] よって、 ser=0. 001とした場合、 SERO =0. 002、 SERN = 9. 98 X 10— 6となり [0059] Therefore, when a ser = 0. 001, SERO = 0. 002, SERN = 9. 98 X 10- 6 next
1 1 1 1
、従来のメモリセルの冗長選択に比べ、ソフトエラー耐性が約 200倍に増加する結果 となる。 Compared to the conventional redundant selection of memory cells, the soft error resistance is increased by about 200 times.
[0060] このように、ラッチに保持される冗長選択信号のビット数を増やし、 1つの冗長設定 に対して、 1つの冗長選択信号と、複数の 1ビット反転データを割り当てることによって 、冗長選択におけるソフトエラー耐性を向上することができる。 [0060] In this way, by increasing the number of bits of the redundancy selection signal held in the latch and assigning one redundancy selection signal and a plurality of 1-bit inverted data to one redundancy setting, Soft error resistance can be improved.
[0061] なお、ここでは各冗長設定に 1ビット反転データを割り当てる場合を説明したが、より 多くのビット数を冗長選択信号に用いることができる場合には、複数のビットが反転し たデータをさらに割り当てることが可能である。 [0061] Although the case where 1-bit inversion data is assigned to each redundancy setting has been described here, when a larger number of bits can be used for the redundancy selection signal, data in which a plurality of bits are inverted is used. Further allocation is possible.
[0062] 次に、本実施例に係る冗長選択信号の生成方法について説明する。図 4は、図 3 に示した冗長選択信号を生成するアルゴリズムを示すフローチャートである。 Next, a method for generating a redundant selection signal according to the present embodiment will be described. FIG. 4 is a flowchart showing an algorithm for generating the redundancy selection signal shown in FIG.
[0063] 図 4に示すように、この冗長選択信号生成アルゴリズムでは、まず、生成する冗長信 号のビット数と同じビット数のデータ変数を定義する。このデータ変数には、 2進数の 数値が設定される。そして、このデータ変数の全てのビットに初期値として「0」を設定 する (ステップ S101)。例えば、冗長選択信号が 5ビットである場合は、「00000」を設 定する。
[0064] そして、データ変数の 1ビットのみを反転した 1ビット反転データを作成する (ステツ プ S102)。 f列えば、、冗長選択信号力 S「00000」である場合に ίま、「00001」、 「00010 」、 「00100」、 「01000」及び「10000」の 5通りの 1ビット反転データを作成する。 As shown in FIG. 4, in this redundancy selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value for all bits of this data variable (step S101). For example, if the redundant selection signal is 5 bits, set “00000”. [0064] Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S102). f, for example, when the redundant selection signal power S is “00000”, 5 bits of 1-bit inverted data of “00001”, “00010”, “00100”, “01000” and “10000” are created. .
[0065] そして、データ変数を冗長選択信号に割り当てるとともに (ステップ S103)、当該デ ータ変数および当該データ変数の 1ビット反転データを全て、そのデータ変数が冗長 選択信号に割当てられていることにより使用できないことを示す使用済みリストに登録 する(ステップ S 104)。 [0065] Then, the data variable is assigned to the redundancy selection signal (step S103), and the data variable and the 1-bit inverted data of the data variable are all assigned to the redundancy selection signal. It is registered in the used list indicating that it cannot be used (step S104).
[0066] その後、データ変数に 1を加算し、これを新たなデータ変数とするとともに (ステップ S105)、新たなデータ変数の 1ビット反転データを作成する(ステップ S 106)。 [0066] Thereafter, 1 is added to the data variable to make it a new data variable (step S105), and 1-bit inverted data of the new data variable is created (step S106).
[0067] ここで、新たなデータ変数およびデータ変数の 1ビット反転データを使用済みリスト の内容と比較する (ステップ S107)。使用済みリストに当該データ変数または当該デ ータ変数の 1ビット反転データと同じ値のデータが既に含まれて 、た場合は (ステップ S108, Yes)、ステップ S 105に戻って新たなデータ変数を設定し、ステップ S106以 降の処理を繰り返す。 [0067] Here, the new data variable and the 1-bit inverted data of the data variable are compared with the contents of the used list (step S107). If the used list already contains the data variable or data with the same value as the 1-bit inverted data of the data variable (step S108, Yes), return to step S105 to add a new data variable. Set and repeat the process from step S106.
[0068] 一方、使用済みリストに当該データ変数および当該データ変数の 1ビット反転デー タと同じ値のデータが含まれていなかった場合は (ステップ S 108, No)、当該データ 変数を冗長選択信号に割り当て (ステップ S109)、さらに、当該データ変数および当 該データ変数の 1ビット反転データを使用済みリストに登録する (ステップ S110)。 [0068] On the other hand, when the used list does not include the data variable and the data having the same value as the 1-bit inverted data of the data variable (step S108, No), the data variable is set to the redundant selection signal. (Step S109), and the data variable and the 1-bit inverted data of the data variable are registered in the used list (step S110).
[0069] ここで、データ変数に対して必要な数だけ冗長選択信号が割り当てられた場合は( ステップ S111, Yes)、処理を終了する。必要な数を満たしていない場合は (ステップ Si l l, No)、ステップ S 105に戻って新たなデータ変数を設定し、ステップ S106以 降の処理を繰り返す。 Here, when the necessary number of redundant selection signals are assigned to the data variable (step S111, Yes), the process is terminated. If the necessary number is not satisfied (step Sill, No), the process returns to step S105, a new data variable is set, and the processing after step S106 is repeated.
[0070] 上記のアルゴリズムで生成した冗長選択信号と、各冗長選択信号の 1ビット反転デ ータを、図 3に示したように、冗長設定に対して割り当てる。 [0070] As shown in FIG. 3, the redundancy selection signal generated by the above algorithm and the 1-bit inverted data of each redundancy selection signal are allocated to the redundancy setting.
[0071] なお、ここでは、 1つの冗長設定に対して、ラッチに設定される 1つの冗長選択信号 と、その冗長選択信号を構成する複数のビットについて、 1つのビットのみを反転させ ることによって得られる全ての 1ビット反転データとを割り当てる場合について説明し
[0072] この場合、例えば、メモリセルグループ 1〜7と冗長メモリセルグループを置き換える 7通りの冗長設定の場合には、メモリセルグループ 1〜7と冗長メモリグループとを置 き換えるため、 1ビットを反転した 1ビット反転データがそれぞれのメモリセルグループ と対応するため、少なくとも 7ビットの冗長選択信号が必要となる。しかし、回路面積の 制約等で、冗長選択信号に用いるビットが 4ビットしか確保できない場合でも、それぞ れの冗長設定に対して、 4ビットの冗長選択信号 1つと、その冗長選択信号について 4ビット中 1ビットを反転した 1つの 1ビット反転データを割り当てただけでも、 1つの冗 長選択信号のみでデコードする場合に比べれば、ソフトエラー耐性は向上する。 [0071] Here, for one redundancy setting, only one bit is inverted for one redundancy selection signal set in the latch and a plurality of bits constituting the redundancy selection signal. Explains how to assign all obtained 1-bit inverted data. [0072] In this case, for example, in the case of seven redundancy settings for replacing the memory cell groups 1 to 7 with the redundant memory cell group, 1 bit is used to replace the memory cell groups 1 to 7 with the redundant memory group. Since 1-bit inverted data obtained by inverting is associated with each memory cell group, a redundant selection signal of at least 7 bits is required. However, even if only 4 bits can be secured for the redundancy selection signal due to circuit area restrictions, etc., one 4-bit redundancy selection signal and 4 bits for the redundancy selection signal for each redundancy setting. Even if only one 1-bit inverted data with 1 bit inverted is assigned, the soft error tolerance is improved compared to decoding with only one redundant selection signal.
[0073] 図 5は、 1つの冗長設定に 2通りの冗長選択信号を割り当てる場合を示す図である 。同図に示す例では、冗長設定が 8通りであり、 4ビットの冗長選択信号を用いて、そ れぞれの冗長設定に対して、 1つの冗長選択信号と、その冗長選択信号の 1つの 1 ビット反転データを割り当てて 、る。 FIG. 5 is a diagram showing a case where two redundancy selection signals are assigned to one redundancy setting. In the example shown in the figure, there are 8 redundancy settings, and a 4-bit redundancy selection signal is used, and for each redundancy setting, there is one redundancy selection signal and one redundancy selection signal. Allocate 1-bit inverted data.
[0074] このように、各冗長設定に対して割り当てる 1ビット反転データを限定することによつ て、回路面積の制約等で、冗長選択信号に用いることができるビット数が制限されて いる場合でも、冗長選択におけるソフトエラー耐性を向上することができる。 [0074] In this way, by limiting the 1-bit inverted data assigned to each redundancy setting, the number of bits that can be used for the redundancy selection signal is limited due to circuit area restrictions, etc. However, soft error tolerance in redundant selection can be improved.
[0075] また、これまで、メモリセルの置き換えパターンを示す各冗長設定に対して冗長選 択信号を均等に割り当てる場合を説明したが、特定のパターンにより多くの冗長選択 信号を割り当てることによって、当該パターンについて重点的にソフトエラー耐性を向 上させることちでさる。 [0075] Further, the case where the redundancy selection signal is equally assigned to each redundancy setting indicating the replacement pattern of the memory cell has been described so far, but by assigning more redundancy selection signals to a specific pattern, This can be achieved by improving the soft error tolerance with emphasis on patterns.
[0076] 図 6は、特定の冗長設定として、冗長選択をしない場合の冗長設定に重点的に冗 長選択信号を割り当てる場合の冗長選択信号生成アルゴリズムを示すフローチヤ一 トである。 FIG. 6 is a flow chart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a redundancy setting when no redundancy selection is performed as a specific redundancy setting.
[0077] 図 6に示すように、この冗長選択信号生成アルゴリズムでは、まず、生成する冗長信 号のビット数と同じビット数のデータ変数を定義する。このデータ変数には、 2進数の 数値が設定される。そして、このデータ変数の全てのビットに初期値として「0」を設定 する (ステップ S 201)。例えば、冗長選択変数力 ビットである場合は、「0000」を設 定する。 As shown in FIG. 6, in this redundancy selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S 201). For example, if it is a redundant selection variable force bit, set “0000”.
[0078] そして、データ変数の 1ビットのみを反転した 1ビット反転データを作成する (ステツ
プ S202)。例えば、冗長選択信号力 ビットである場合は、「0001」、「0010」、「010 0」、「1000」の 4通りの反転データを作成する。 [0078] Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S202). For example, in the case of the redundant selection signal power bit, four types of inverted data “0001”, “0010”, “010 0”, and “1000” are created.
[0079] そして、データ変数を冗長選択信号に割り当てるとともに (ステップ S203)、当該デ ータ変数および当該データ変数の 1ビット反転データを全て使用済みリストに登録す る(ステップ S 204)。 [0079] Then, the data variable is assigned to the redundancy selection signal (step S203), and all the data variable and 1-bit inverted data of the data variable are registered in the used list (step S204).
[0080] その後、データ変数に 1を加算し、これを新たなデータ変数とする (ステップ S205) [0080] After that, 1 is added to the data variable to make this a new data variable (step S205).
[0081] ここで、データ変数を使用済みリストと比較する (ステップ S206)。使用済みリストに 当該データ変数と同じ値のデータが既に含まれていた場合は (ステップ S 207, Yes) 、ステップ S205に戻って新たなデータ変数を設定し、ステップ S206以降の処理を 繰り返す。 Here, the data variable is compared with the used list (step S206). If the used list already contains data with the same value as the data variable (step S207, Yes), the process returns to step S205, sets a new data variable, and repeats the processing from step S206.
[0082] 一方、使用済みリストに当該データ変数と同じ値のデータが含まれていな力つた場 合は (ステップ S207, No) ,当該データ変数を冗長選択信号に割り当て (ステップ S 208)、さらに、当該データ変数を使用済みリストに登録する (ステップ S209)。 [0082] On the other hand, if the used list does not contain data having the same value as the data variable (step S207, No), the data variable is assigned to the redundant selection signal (step S208), and further The data variable is registered in the used list (step S209).
[0083] ここで、データ変数に対して必要な数だけ冗長選択信号が割り当てられた場合は( ステップ S210, Yes)、処理を終了する。必要な数を満たしていない場合は (ステップ S210, No)、ステップ S205に戻って新たなデータ変数を設定し、ステップ S206以 降の処理を繰り返す。 Here, when the necessary number of redundant selection signals are assigned to the data variable (step S210, Yes), the process is terminated. If the required number is not satisfied (step S210, No), the process returns to step S205 to set a new data variable, and the processes after step S206 are repeated.
[0084] 図 7は、特定の冗長設定に重点的に冗長選択信号を割り当てる場合の一例を示す 図である。同図に示す例では、 4ビットの冗長選択信号を用い、冗長選択しない冗長 設定に対して、全ビットが「0」の冗長選択信号「0000」と、各ビットの 1ビット反転デー タ「0001」、「0010」、「0100」及び「1000」の合計 5つの冗長選択信号を割り当て、 その他のメモリセルグループ 1〜7と冗長メモリセルグループを置き換える 7通りの冗 長設定に対しては、それぞれ 1つずつ冗長選択信号を割り当てる。 [0084] FIG. 7 is a diagram illustrating an example in which a redundancy selection signal is assigned to a specific redundancy setting. In the example shown in the figure, a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit. ”,“ 0010 ”,“ 0100 ”and“ 1000 ”in total, allotting 5 redundant selection signals and replacing the redundant memory cell groups with other memory cell groups 1 to 7 Assign redundant selection signals one by one.
[0085] メモリセルグループ 1〜7と冗長メモリセルグループを置き換える 7通りの冗長設定の 場合には、メモリセルグループ 1〜7と冗長メモリグループとを置き換えることが必要で あり、 1ビットを反転した 1ビット反転データがそれぞれのメモリセルグループと対応す るため、上記のアルゴリズムで生成した冗長選択信号と、全ビットが「0」の冗長選択
信号の 1ビット反転データを用いて、メモリセルの置き換えパターンを示す冗長設定 を割り当てる。 [0085] Replacing memory cell groups 1 to 7 and redundant memory cell groups In the case of seven redundancy settings, it is necessary to replace memory cell groups 1 to 7 and redundant memory groups. Since 1-bit inverted data corresponds to each memory cell group, the redundancy selection signal generated by the above algorithm and redundancy selection with all bits set to “0” A redundant setting that indicates the replacement pattern of the memory cell is assigned using 1-bit inverted data of the signal.
[0086] このように、特定の冗長設定について重点的に 1ビット反転データを割り当てること によって、複数の冗長設定の中で、例えば冗長選択しない場合など、実際に設定さ れる可能性が高い冗長設定について重点的に冗長選択におけるソフトエラー耐性を 向上することができる。 [0086] In this way, by allocating 1-bit inverted data focusing on a specific redundancy setting, a redundancy setting that has a high possibility of being actually set, for example, when no redundancy is selected among a plurality of redundancy settings. As a result, it is possible to improve soft error tolerance in redundant selection.
[0087] また、図 6に示した冗長選択信号生成方法では、特定の冗長設定について重点的 に冗長選択信号を割り当てる場合について説明した。この方法では、特定の冗長設 定について、その冗長設定に対して割り当てた冗長選択信号において、 1ビットのみ が反転して 、た場合でも冗長設定が判定できるように 1ビット反転データを割り当てた 力 さらに 2ビット反転データを割り当てることにより、 2ビットが反転していた場合でも 冗長設定が判定できるようにしてもよい。 [0087] Further, in the redundancy selection signal generation method shown in Fig. 6, the case has been described in which the redundancy selection signal is assigned with priority to a specific redundancy setting. In this method, for a specific redundancy setting, the power of assigning 1-bit inverted data so that the redundancy setting can be determined even if only 1 bit is inverted in the redundancy selection signal assigned to that redundancy setting. Furthermore, by assigning 2-bit inverted data, the redundant setting may be determined even if the 2 bits are inverted.
[0088] 図 8は、特定の冗長設定に対して 2ビット反転データをさらに割り当てる場合の冗長 選択信号生成アルゴリズムを示すフローチャートである。 FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in the case where 2-bit inverted data is further assigned to a specific redundancy setting.
[0089] 図 8に示すように、この冗長選択信号生成アルゴリズムでは、まず、生成する冗長信 号のビット数と同じビット数のデータ変数を定義する。このデータ変数には、 2進数の 数値が設定される。そして、このデータ変数の全てのビットに初期値として「0」を設定 する (ステップ S301)。例えば、冗長選択変数力 ビットである場合は、「0000」を設 定する。 As shown in FIG. 8, in this redundant selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S301). For example, if it is a redundant selection variable force bit, set “0000”.
[0090] そして、データ変数の 1ビットのみを反転した 1ビット反転データと、 2ビットを反転し た 2ビット反転データとを作成する (ステップ S302)。例えば、冗長選択信号が 4ビット である場合は、「0001」、 「0010」、 「0100」、および「1000」の 4通りの 1ビット反転デ ータと、「0011」、 「0101」、 「0110」、 「1001」、 「1010」および「1100」の 6通りの 2 ビット反転データとからなる合計 10通りの反転データを作成する。 [0090] Then, 1-bit inverted data obtained by inverting only 1 bit of the data variable and 2-bit inverted data obtained by inverting 2 bits are created (step S302). For example, when the redundancy selection signal is 4 bits, four types of 1-bit inverted data of “0001”, “0010”, “0100”, and “1000”, “0011”, “0101”, “ A total of 10 inverted data consisting of 6 2-bit inverted data of “0110”, “1001”, “1010” and “1100” is created.
[0091] そして、データ変数を冗長選択信号に割り当てるとともに (ステップ S303)、当該デ ータ変数と、当該データ変数の 1ビット反転データおよび 2ビット反転データを全て使 用済みリストに登録する (ステップ S304)。 [0091] Then, the data variable is assigned to the redundancy selection signal (step S303), and the data variable, the 1-bit inverted data and the 2-bit inverted data of the data variable are all registered in the used list (step S303). S304).
[0092] その後、データ変数に 1を加算し、これを新たなデータ変数とする (ステップ S305)
[0093] ここで、新たなデータ変数を使用済みリストと比較する (ステップ S306)。使用済みリ ストに当該データ変数と同じ値のデータが既に含まれていた場合は (ステップ S307, Yes)、当該データ変数が所与のビット数で表される最大値 (例えば「1111」)である か否かを判定する(ステップ S311)。 [0092] After that, 1 is added to the data variable to make this a new data variable (step S305). Here, the new data variable is compared with the used list (step S306). If the used list already contains data with the same value as the relevant data variable (step S307, Yes), the data variable will be the maximum value represented by the given number of bits (eg “1111”). It is determined whether or not there is (step S311).
[0094] そして、当該データ変数が所与のビット数で表される最大値 (例えば「1111」)と等 しい場合は (ステップ S311, Yes)、データ変数に対して必要な数を満たすまで、使 用済みリスト中の 2ビット反転データを冗長選択信号に割り当てる (ステップ S 312)。 一方、当該データ変数が最大値でな力つた場合は (ステップ S311, No)、ステップ S 305に戻って新たなデータ変数を設定し、ステップ S306以降の処理を繰り返す。ま た、使用済みリストに当該データ変数と同じ値のデータが含まれていな力つた場合は (ステップ S307, No) ,当該データ変数を冗長選択信号に割り当て (ステップ S308) 、さらに、当該データ変数を使用済みリストに登録する (ステップ S309)。 [0094] If the data variable is equal to the maximum value represented by the given number of bits (eg, "1111") (step S311, Yes), until the required number is satisfied for the data variable, The 2-bit inverted data in the used list is assigned to the redundancy selection signal (step S312). On the other hand, if the data variable is weak at the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated. If the used list does not contain data with the same value as the data variable (Step S307, No), the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).
[0095] ここで、データ変数に対して必要な数だけ冗長選択信号が割り当てられた場合は( ステップ S310, Yes)、処理を終了する。必要な数を満たしていない場合は (ステップ S310, No) ,当該データ変数が、所与のビット数で表される最大値である力否かを 判定する。 Here, when the necessary number of redundant selection signals are assigned to the data variable (step S310, Yes), the process is terminated. If the required number is not satisfied (step S310, No), it is determined whether or not the data variable is the maximum value represented by the given number of bits.
[0096] そして、当該データ変数が最大値であった場合は (ステップ S311, Yes)、必要な 数を満たすまで、使用済みリスト中の 2ビット反転データを冗長選択信号に割り当てる (ステップ S312)。一方、当該データ変数が最大値でな力つた場合は (ステップ S31 1, No)、ステップ S305に戻って新たなデータ変数を設定し、ステップ S306以降の 処理を繰り返す。 [0096] If the data variable has the maximum value (step S311, Yes), the 2-bit inverted data in the used list is assigned to the redundant selection signal until the required number is satisfied (step S312). On the other hand, when the data variable is weak at the maximum value (step S311, No), the process returns to step S305 to set a new data variable and repeats the processing after step S306.
[0097] 上記のアルゴリズムで生成した冗長選択信号と、全ビットが「0」の冗長選択信号の 1ビット反転データおよび 2ビット反転データを用いて、冗長設定を割り当てる。図 9は 、特定の冗長設定に余った冗長選択信号をさらに割り当てる場合の一例を示す図で ある。同図に示す例では、 4ビットの冗長選択信号を用い、冗長選択しない冗長設定 に対して、全ビットが「0」の冗長選択信号と、その全ての 1ビット反転データと、 2ビット 反転データのうち冗長選択信号に割り当てられなカゝつたものとを割り当て、メモリセル
グループ 1〜7と冗長メモリセルグループを置き換える 7通りの冗長設定に対しては、 それぞれ 1つずつ冗長選択信号を割り当てる。 Redundancy settings are assigned using the redundancy selection signal generated by the above algorithm and the 1-bit inverted data and 2-bit inverted data of the redundancy selection signal with all bits being “0”. FIG. 9 is a diagram showing an example in which redundant selection signals remaining for a specific redundant setting are further allocated. In the example shown in the figure, a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, a redundancy selection signal with all bits set to “0”, all 1-bit inverted data, and 2-bit inverted data. Memory cells that are assigned to the redundant selection signal. Redundant selection signals are assigned to each of the seven redundancy settings that replace redundant memory cell groups with groups 1-7.
[0098] なお、ここでは、 1ビット反転データおよび 2ビット反転データを特定の冗長設定に 対して割り当てる場合を説明したが、より多くのビット数を冗長選択信号に用いること ができる場合は、 3ビット以上が反転したデータをさらに割り当ててもよい。 [0098] Although the case where 1-bit inverted data and 2-bit inverted data are assigned to a specific redundancy setting has been described here, if a larger number of bits can be used for the redundancy selection signal, 3 Data in which bits or more are inverted may be further allocated.
[0099] このように、冗長選択信号に用いることができるビット数に応じて、可能な限り複数 のビットが反転したデータを割り当てることによって、特定の冗長設定について冗長 選択におけるソフトエラー耐性をより向上することができる。 [0099] As described above, by assigning data in which a plurality of bits are inverted as much as possible according to the number of bits that can be used for the redundancy selection signal, soft error resistance in redundancy selection is further improved for a specific redundancy setting. can do.
[0100] 図 10は、図 9に示した冗長設定による冗長デコード回路の一例を示す図である。同 図に示す例の冗長デコード回路は、 4つのインバータ回路と、 7つの AND回路と、 6 つの OR回路力も構成されている。この冗長デコード回路は、 4ビットの冗長選択信号 RED0〜RED3に応じて、 7ビットの冗長デコード信号 SEL0〜SEL6を出力する。 FIG. 10 is a diagram showing an example of a redundant decoding circuit based on the redundant setting shown in FIG. The redundant decoding circuit of the example shown in the figure also consists of four inverter circuits, seven AND circuits, and six OR circuit powers. This redundant decode circuit outputs 7-bit redundant decode signals SEL0 to SEL6 in response to 4-bit redundant select signals RED0 to RED3.
[0101] 4ビットの冗長選択信号 RED0〜RED3をデコードすることにより、出力される冗長 デコード信号 SEL0〜SEL6は、「0000000」、 「1111111」、 「1111110」、 「1111 100」、 「1111000」、 「1110000」、 「1100000」および「1000000」の 8種類となる 。これらの冗長デコード信号 SEL0〜SEL6は、それぞれ、 8通りの冗長設定にひと つずつ対応付いている。そして、これらの冗長デコード信号 SEL0〜SEL6に基づい て、冗長スィッチ回路によって、メモリセルグループの冗長設定が行われる。 [0101] The redundant decode signals SEL0 to SEL6 output by decoding the 4-bit redundancy selection signals RED0 to RED3 are "0000000", "1111111", "1111110", "1111 100", "1111000", There are 8 types of “1110000”, “1100000” and “1000000”. Each of these redundant decode signals SEL0 to SEL6 is associated with eight redundancy settings. Then, based on these redundant decode signals SEL0 to SEL6, the redundant setting of the memory cell group is performed by the redundant switch circuit.
[0102] 上述してきたように、本実施例では、冗長設定用ラッチ 5〜5力 メモリセルグルー [0102] As described above, in this embodiment, the redundancy setting latch 5 to 5 force memory cell group
1 n 1 n
プの置き換えパターンを示す冗長設定に対応付けられた冗長選択信号をあらかじめ 保持し、冗長選択回路 21が、この冗長選択信号を入力して冗長選択信号の一部が 反転していた場合でも反転する前の冗長選択信号に対応付けられた冗長設定と同 じ冗長設定を導出し、冗長スィッチ回路 22が、導出した冗長設定に基づいてメモリセ ルグループの置き換えを行うこととしたので、宇宙からの放射線などの影響により冗 長設定用ラッチ 5〜5に保持している冗長選択信号にソフトエラーが発生していた The redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the group is held in advance, and the redundancy selection circuit 21 inverts even when a part of the redundancy selection signal is inverted by inputting this redundancy selection signal. The redundancy setting same as the redundancy setting associated with the previous redundancy selection signal is derived, and the redundancy switch circuit 22 replaces the memory cell group based on the derived redundancy setting. The redundancy selection signal held in the redundancy setting latches 5 to 5 caused a soft error due to
1 n 1 n
場合でも、正しく冗長選択を行うことができるため、冗長選択におけるソフトエラー耐 性を向上することができる。 Even in this case, since the redundancy selection can be performed correctly, the soft error resistance in the redundancy selection can be improved.
産業上の利用可能性
以上のように、本発明に係る冗長選択装置および冗長選択方法は、不良メモリセル を冗長メモリセルで置き換える冗長選択を行う半導体記憶装置に有用であり、特に、 冗長選択信号などの冗長選択を制御するデータを長期間保持する半導体装置を内 蔵するプロセサゃ DSP(Digital Signal Processor), SOC(System On Chip)等の L SIに適している。
Industrial applicability As described above, the redundancy selection device and the redundancy selection method according to the present invention are useful for a semiconductor memory device that performs redundancy selection in which a defective memory cell is replaced with a redundancy memory cell, and in particular, controls redundancy selection such as a redundancy selection signal. Processors that contain semiconductor devices that hold data for a long time are suitable for LSI such as DSP (Digital Signal Processor) and SOC (System On Chip).
Claims
[1] 記憶装置を構成するメモリセルと冗長メモリセルとに接続され、前記メモリセル又は 前記冗長メモリセルの何れかの入出力を選択する冗長選択を行うメモリ冗長選択装 置であって、 [1] A memory redundancy selection device that is connected to a memory cell and a redundancy memory cell constituting a storage device and performs redundancy selection for selecting an input / output of either the memory cell or the redundancy memory cell,
前記メモリセルの選択情報を示す冗長選択信号を保持する冗長選択信号保持手 段と、 A redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell;
前記冗長選択情報保持手段に保持された前記冗長選択信号を入力して、前記冗 長選択信号の一部が反転していた場合においても反転する前と同じ冗長設定をデコ ード結果として出力を行う冗長デコード手段と、 When the redundancy selection signal held in the redundancy selection information holding means is input, even if a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decode result. Redundant decoding means to perform,
前記デコード結果に基づ!、て、前記メモリセル又は前記冗長メモリセルの何れかの 入出力の選択を行う冗長スィッチ手段と、 Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
を備えたことを特徴とするメモリ冗長選択装置。 A memory redundancy selection device comprising:
[2] 前記冗長選択信号保持手段は、スキャンラッチ手段により構成されることを特徴と する請求項 1記載のメモリ冗長選択装置。 2. The memory redundancy selection device according to claim 1, wherein the redundancy selection signal holding means is constituted by a scan latch means.
[3] 前記冗長デコード手段は、デコード結果として出力する同一の冗長設定について、 少なくとも二以上の冗長選択信号が入力として対応付けられるように構成されることを 特徴とする請求項 1記載のメモリ冗長選択装置。 3. The memory redundancy according to claim 1, wherein the redundancy decoding means is configured to associate at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result. Selection device.
[4] 前記冗長選択信号は nビット (n> 1)で構成され、 [4] The redundancy selection signal is composed of n bits (n> 1),
前記冗長デコード手段は、前記冗長選択信号を構成する nビットのうち kビット (0< k≤n— 1)までが反転していた場合においても反転する前と同じ冗長設定をデコード 結果として出力を行うことを特徴とする請求項 1記載のメモリ冗長選択装置。 The redundant decoding means outputs the same redundancy setting as the decoding result as the decoding result even when k bits (0 <k≤n-1) of n bits constituting the redundancy selection signal are inverted. The memory redundancy selection device according to claim 1, wherein the memory redundancy selection device is performed.
[5] メモリセノレと、 [5] Memory Senore and
冗長メモリセルと、 Redundant memory cells;
前記メモリセルと前記冗長メモリセルとに接続され、前記メモリセル又は前記冗長メ モリセルの何れかの入出力を選択する冗長選択を行う冗長選択手段とを有し、 前記冗長選択手段は、 Redundant selection means connected to the memory cell and the redundant memory cell, and performing redundant selection for selecting input / output of either the memory cell or the redundant memory cell; and
前記メモリセルの選択情報を示す冗長選択信号を保持する冗長選択信号保持手 段と、
前記冗長選択情報保持手段に保持された前記冗長選択信号を入力して、前記冗 長選択信号の一部が反転していた場合においても反転する前と同じ冗長設定をデコ ード結果として出力を行う冗長デコード手段と、 A redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell; When the redundancy selection signal held in the redundancy selection information holding means is input, even if a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decode result. Redundant decoding means to perform,
前記デコード結果に基づ!、て、前記メモリセル又は前記冗長メモリセルの何れかの 入出力の選択を行う冗長スィッチ手段と、 Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
を備えたことを特徴とする記憶装置。 A storage device comprising:
[6] メモリセノレと、 [6] Memory Senore,
冗長メモリセルと、 Redundant memory cells;
前記記憶装置に接続される演算処理装置と、 An arithmetic processing unit connected to the storage device;
前記メモリセルと前記冗長メモリセルとに接続され、前記メモリセル又は前記冗長メ モリセルの何れかの入出力を選択する冗長選択を行う冗長選択手段とを有し、 前記冗長選択手段は、 Redundant selection means connected to the memory cell and the redundant memory cell, and performing redundant selection for selecting input / output of either the memory cell or the redundant memory cell; and
前記メモリセルの選択情報を示す冗長選択信号を保持する冗長選択信号保持手 段と、 A redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell;
前記冗長選択情報保持手段に保持された前記冗長選択信号を入力して、前記冗 長選択信号の一部が反転していた場合においても反転する前と同じ冗長設定をデコ ード結果として出力を行う冗長デコード手段と、 When the redundancy selection signal held in the redundancy selection information holding means is input, even if a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decode result. Redundant decoding means to perform,
前記デコード結果に基づ!、て、前記メモリセル又は前記冗長メモリセルの何れかの 入出力の選択を行う冗長スィッチ手段と、 Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
を備えたことを特徴とする情報処理装置。 An information processing apparatus comprising:
[7] 前記情報処理装置はさらに、スキャンシフト制御を行う TAPコントローラ手段と、 前記 TAPコントローラ手段から出力されるスキャンクロックによりスキャンシフトを行 い、前記冗長選択信号保持手段を含むスキャンラッチ手段と、 [7] The information processing apparatus further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and includes a redundancy selection signal holding unit;
前記スキャンラッチ手段に接続され、冗長選択信号を設定するヒューズ手段とを有 し、 A fuse means connected to the scan latch means for setting a redundancy selection signal;
前記ヒューズ手段に設定された冗長選択信号を前記スキャンラッチ手段に出力し、 前記スキャンシフトを行うことにより、前記冗長選択信号保持手段に前記冗長選択信 号を保持することを特徴とする請求項 6記載の情報処理装置。
7. The redundancy selection signal set in the fuse means is output to the scan latch means, and the redundancy selection signal is held in the redundancy selection signal holding means by performing the scan shift. The information processing apparatus described.
[8] 前記情報処理装置はさらに、スキャンシフト制御を行う TAPコントローラ手段と、 前記 TAPコントローラ手段から出力されるスキャンクロックによりスキャンシフトを行 い、前記冗長選択信号保持手段を含むスキャンラッチ手段と、 [8] The information processing apparatus further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and includes a redundancy selection signal holding unit;
前記スキャンラッチ手段に接続されるスキャン入力とを有し、 A scan input connected to the scan latch means;
前記スキャン入力から前記冗長選択信号を入力し、前記スキャンシフトを行うことに より、前記冗長選択信号保持手段に前記冗長選択信号を保持することを特徴とする 請求項 6記載の情報処理装置。 7. The information processing apparatus according to claim 6, wherein the redundancy selection signal is held in the redundancy selection signal holding unit by inputting the redundancy selection signal from the scan input and performing the scan shift.
[9] 記憶装置を構成するメモリセル又は冗長メモリセルの何れかの入出力を選択するメ モリセルの冗長選択の方法であって、 [9] A memory cell redundancy selection method for selecting input / output of a memory cell or a redundant memory cell constituting a storage device,
前記メモリセルの選択情報を示す冗長選択信号を保持するステップと、 前記保持された前記冗長選択信号を入力して、前記冗長選択信号の一部が反転 していた場合においても反転する前と同じ冗長設定をデコード結果として出力を行う ステップと、 A step of holding a redundancy selection signal indicating selection information of the memory cell, and inputting the held redundancy selection signal, and even when a part of the redundancy selection signal is inverted, the same as before the inversion A step of outputting the redundant setting as a decoding result; and
前記デコード結果に基づ!、て、前記メモリセル又は前記冗長メモリセルの何れかの 入出力の選択を行うステップと、 Based on the decoding result !, selecting the input / output of either the memory cell or the redundant memory cell;
を備えたことを特徴とするメモリセルの冗長選択の方法。 A method for redundant selection of memory cells, comprising:
[10] 前記保持された前記冗長選択信号を入力して、前記冗長選択信号の一部が反転 していた場合においても反転する前と同じ冗長設定をデコード結果として出力を行う 前記ステップにおいて、 [10] The retained redundancy selection signal is input, and even when a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is output as a decoding result.
デコード結果として出力する同一の冗長設定について、少なくとも二以上の冗長選 択信号が入力として対応付けられることを特徴とする請求項 9記載のメモリセルの冗 長選択の方法。 10. The method for redundant selection of memory cells according to claim 9, wherein at least two redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.
[11] 半導体記憶装置において不良メモリセルを冗長メモリセルで置き換える冗長選択を 行うメモリ冗長選択装置であって、 [11] A memory redundancy selection device for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor memory device,
メモリセルの置き換えパターンを示す冗長設定に対応付けられた冗長選択信号を あらかじめ保持する冗長選択信号保持手段と、 Redundancy selection signal holding means for holding in advance a redundancy selection signal associated with a redundancy setting indicating a replacement pattern of a memory cell;
前記冗長選択信号を入力して該冗長選択信号の一部が変化していた場合でも変 化する前と同じ冗長設定を導出する冗長デコード手段と、
前記冗長デコード手段によって導出された冗長設定に基づいてメモリセルの置き 換えを行う冗長スィッチ手段と、 Redundant decoding means for deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal; Redundant switch means for replacing a memory cell based on the redundancy setting derived by the redundant decoding means;
を備えたことを特徴とするメモリ冗長選択装置。 A memory redundancy selection device comprising:
[12] 前記冗長選択信号は nビット (n> 1)で構成され、 [12] The redundancy selection signal is composed of n bits (n> 1),
前記冗長デコード手段は、前記冗長選択信号を構成する nビットのうち n— kビット ( 0<k≤n— 1)までが反転していた場合でも反転する前の冗長選択信号に対応付け られた冗長設定と同じ冗長設定を導出することを特徴とする請求項 11に記載のメモリ 冗長選択装置。 The redundant decoding means is associated with the redundant selection signal before inversion even when n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 12. The memory redundancy selection device according to claim 11, wherein a redundancy setting that is the same as the redundancy setting is derived.
[13] 前記冗長デコード手段は、前記冗長選択信号を構成する nビットのうち所定のビット について n—kビット(0<k≤n— 1)までが反転していた場合でも反転する前の冗長 選択信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴とする請 求項 12に記載のメモリ冗長選択装置。 [13] The redundant decoding means may perform redundancy before inversion even if n-k bits (0 <k≤n-1) are inverted for a predetermined bit among n bits constituting the redundancy selection signal. 13. The memory redundancy selection device according to claim 12, wherein the redundancy setting that is the same as the redundancy setting associated with the selection signal is derived.
[14] 前記冗長デコード手段は、特定の冗長設定につ!ヽては前記冗長選択信号を構成 する nビットのうち n— kビット(0 < k≤ n— 1)までが反転して 、た場合でも反転する前 の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴と する請求項 12に記載のメモリ冗長選択装置。 [14] The redundancy decoding means inverts n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal for a specific redundancy setting. 13. The memory redundancy selection device according to claim 12, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.
[15] 前記冗長デコード手段は、メモリセルの置き換えを行わない冗長設定については 前記冗長選択信号を構成する nビットのうち n— kビット(0<k≤n— 1)までが反転し ていた場合でも反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長 設定を導出することを特徴とする請求項 14に記載のメモリ冗長選択装置。 [15] The redundancy decoding means inverts up to n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal for redundancy setting in which memory cells are not replaced. 15. The memory redundancy selection device according to claim 14, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.
[16] 前記冗長デコード手段は、前記冗長選択信号を構成する nビットのうちいずれかの [16] The redundant decoding means is any one of n bits constituting the redundant selection signal.
1ビットが反転していた場合でも反転する前の冗長選択信号に対応付けられた冗長 設定と同じ冗長設定を導出することを特徴とする請求項 12に記載のメモリ冗長選択 装置。 13. The memory redundancy selection device according to claim 12, wherein even if one bit is inverted, a redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before being inverted is derived.
[17] 前記冗長デコード手段は、特定の冗長設定については前記冗長選択信号を構成 する nビットのうちいずれかの 1ビットが反転していた場合でも反転する前の冗長選択 信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴とする請求項 14に記載のメモリ冗長選択装置。
[17] The redundant decoding means is associated with the redundant selection signal before inversion even if one of the n bits constituting the redundancy selection signal is inverted for a specific redundancy setting. 15. The memory redundancy selection device according to claim 14, wherein the same redundancy setting as the redundancy setting is derived.
[18] 前記冗長デコード手段は、メモリセルの置き換えを行わない冗長設定については 前記冗長選択信号を構成する nビットのうちいずれかの 1ビットが反転していた場合で も反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導出す ることを特徴とする請求項 17に記載のメモリ冗長選択装置。 [18] For the redundancy setting in which the memory cell is not replaced, the redundancy decoding means selects the redundancy before inversion even if any one of the n bits constituting the redundancy selection signal is inverted. 18. The memory redundancy selection device according to claim 17, wherein the redundancy setting same as the redundancy setting associated with the signal is derived.
[19] 前記冗長選択信号保持手段は、前記冗長選択信号を前記半導体記憶装置に搭 載されたラッチに保持することを特徴とする請求項 11〜18のいずれか一つに記載の メモリ冗長選択装置。 [19] The memory redundancy selection according to any one of [11] to [18], wherein the redundancy selection signal holding means holds the redundancy selection signal in a latch mounted on the semiconductor memory device. apparatus.
[20] 前記冗長選択信号保持手段は、ヒューズを切断することによって発生する信号によ つて前記ラッチに保持する冗長選択信号を設定することを特徴とする請求項 19に記 載のメモリ冗長選択装置。 20. The memory redundancy selection device according to claim 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by a signal generated by cutting a fuse. .
[21] 前記冗長選択信号保持手段は、外部から入力される信号によって前記ラッチに保 持する冗長選択信号を設定することを特徴とする請求項 19に記載のメモリ冗長選択 装置。 21. The memory redundancy selection device according to claim 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by an externally input signal.
[22] 半導体記憶装置において不良メモリセルを冗長メモリセルで置き換える冗長選択を 行うメモリ冗長選択方法であって、 [22] A memory redundancy selection method for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor memory device,
メモリセルの置き換えパターンを示す冗長設定に対応付けられた冗長選択信号を あらかじめ保持する冗長選択信号保持工程と、 A redundancy selection signal holding step for holding in advance a redundancy selection signal associated with a redundancy setting indicating a memory cell replacement pattern;
前記冗長選択信号を入力して該冗長選択信号の一部が変化していた場合でも変 化する前と同じ冗長設定を導出する冗長デコード工程と、 A redundancy decoding step of deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal;
前記冗長デコード工程によって導出された冗長設定に基づいてメモリセルの置き 換えを行う冗長スィッチ工程と、 A redundant switch step for replacing a memory cell based on the redundancy setting derived by the redundant decoding step;
を含んだことを特徴とするメモリセルの冗長選択の方法。 A method for redundant selection of memory cells, comprising:
[23] 前記冗長選択信号は nビット (n> 1)で構成され、 [23] The redundancy selection signal is composed of n bits (n> 1),
前記冗長デコード工程は、前記冗長選択信号を構成する nビットのうち n— kビット ( 0<k≤n— 1)までが反転していた場合でも反転する前の冗長選択信号に対応付け られた冗長設定と同じ冗長設定を導出することを特徴とする請求項 22に記載のメモリ セルの冗長選択の方法。 The redundant decoding step is associated with the redundant selection signal before inversion even when n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 23. The method for redundant selection of memory cells according to claim 22, wherein a redundancy setting that is the same as the redundancy setting is derived.
[24] 前記冗長デコード工程は、前記冗長選択信号を構成する nビットのうち所定のビット
について n—kビット(0<k≤n— 1)までが反転していた場合でも反転する前の冗長 選択信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴とする請 求項 23に記載のメモリセルの冗長選択の方法。 [24] The redundant decoding step includes a predetermined bit of n bits constituting the redundant selection signal. A request characterized by deriving the same redundancy setting as that associated with the redundancy selection signal before inversion even if n−k bits (0 <k≤n—1) are inverted. 24. A method of redundant selection of memory cells according to item 23.
[25] 前記冗長デコード工程は、特定の冗長設定につ!ヽては前記冗長選択信号を構成 する nビットのうち n— kビット(0 < k≤ n— 1)までが反転して 、た場合でも反転する前 の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴と する請求項 23に記載のメモリセルの冗長選択の方法。 [25] In the redundancy decoding step, n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal are inverted for a specific redundancy setting. 24. The method of redundant selection of memory cells according to claim 23, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived even in the case.
[26] 前記冗長デコード工程は、メモリセルの置き換えを行わない冗長設定については 前記冗長選択信号を構成する nビットのうち n— kビット(0<k≤n— 1)までが反転し ていた場合でも反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長 設定を導出することを特徴とする請求項 25に記載のメモリセルの冗長選択の方法。 [26] In the redundancy decoding step, n−k bits (0 <k ≦ n−1) out of n bits constituting the redundancy selection signal were inverted for the redundancy setting in which the memory cell is not replaced. 26. The method of redundant selection of a memory cell according to claim 25, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.
[27] 前記冗長デコード工程は、前記冗長選択信号を構成する nビットのうちいずれかの 1ビットが反転していた場合でも反転する前の冗長選択信号に対応付けられた冗長 設定と同じ冗長設定を導出することを特徴とする請求項 23に記載のメモリセルの冗 長選択の方法。 [27] In the redundancy decoding step, even if any one of the n bits constituting the redundancy selection signal is inverted, the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion is performed. 24. The method for redundantly selecting memory cells according to claim 23, wherein:
[28] 前記冗長デコード工程は、特定の冗長設定につ!ヽては前記冗長選択信号を構成 する nビットのうちいずれかの 1ビットが反転していた場合でも反転する前の冗長選択 信号に対応付けられた冗長設定と同じ冗長設定を導出することを特徴とする請求項 25に記載のメモリセルの冗長選択の方法。 [28] The redundant decoding process is for a specific redundant setting! In other words, even if any one of the n bits constituting the redundancy selection signal is inverted, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. 26. The method for redundant selection of memory cells according to claim 25.
[29] 前記冗長デコード工程は、メモリセルの置き換えを行わない冗長設定については 前記冗長選択信号を構成する nビットのうちいずれかの 1ビットが反転していた場合で も反転する前の冗長選択信号に対応付けられた冗長設定と同じ冗長設定を導出す ることを特徴とする請求項 28に記載のメモリセルの冗長選択の方法。 [29] In the redundancy decoding step, the redundancy selection before the inversion is performed even if one of the n bits constituting the redundancy selection signal is inverted for the redundancy setting in which the memory cell is not replaced. 30. The method for redundant selection of memory cells according to claim 28, wherein the same redundancy setting as that for the signal is derived.
[30] 前記冗長選択信号保持工程は、前記冗長選択信号を前記半導体記憶装置に搭 載されたラッチに保持することを特徴とする請求項 22〜29のいずれか一つに記載の メモリセルの冗長選択の方法。
30. The memory cell according to claim 22, wherein the redundancy selection signal holding step holds the redundancy selection signal in a latch mounted on the semiconductor memory device. Redundant selection method.
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