WO2007072580A1 - Dispositif de selection de redondance de memoire, dispositif de memoire, dispositif de traitement des informations et procede de selection de redondance de cellule de memoire - Google Patents

Dispositif de selection de redondance de memoire, dispositif de memoire, dispositif de traitement des informations et procede de selection de redondance de cellule de memoire Download PDF

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Publication number
WO2007072580A1
WO2007072580A1 PCT/JP2006/303153 JP2006303153W WO2007072580A1 WO 2007072580 A1 WO2007072580 A1 WO 2007072580A1 JP 2006303153 W JP2006303153 W JP 2006303153W WO 2007072580 A1 WO2007072580 A1 WO 2007072580A1
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Prior art keywords
redundancy
selection signal
redundant
memory cell
setting
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PCT/JP2006/303153
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English (en)
Japanese (ja)
Inventor
Masato Susuki
Hiroshi Nakadai
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Fujitsu Limited
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Publication of WO2007072580A1 publication Critical patent/WO2007072580A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching

Definitions

  • Memory redundancy selection device storage device, information processing device, and memory cell redundancy selection method
  • the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell for performing redundancy selection in which a defective memory cell is replaced with a redundant memory cell in a semiconductor storage device such as a RAM built in an LSI such as a processor
  • the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell redundancy selection method that can improve soft error tolerance in redundancy selection.
  • a processor incorporating a semiconductor memory device such as a RAM as a cache memory has a spare memory cell called a redundant memory cell in preparation for a manufacturing failure in an LSI such as a DSP (Digital Signal Processor) or SOC (System On Chip).
  • LSI Digital Signal Processor
  • SOC System On Chip
  • the address indicated by the defective memory cell is set by switching a memory cell by setting an address of the defective memory cell by cutting a fuse arranged on a semiconductor chip.
  • a technique for switching a memory cell to a redundant memory cell has been devised (for example, see Patent Document 1) o
  • a redundant selection signal when a memory cell is replaced using a signal for replacing a defective memory cell with a redundant memory cell (hereinafter referred to as a redundant selection signal), this signal is sent from the fuse to the memory cell. Although it may be input directly to a circuit for replacement (hereinafter referred to as a redundancy selection circuit), it is input via a scan chain composed of scan latches arranged on the chip to avoid complicated wiring. Sometimes.
  • FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.
  • the RAM macro shown in the figure includes three memory cell groups 1 to 3 and one redundant memory cell group (reserved memory group).
  • a memory cell is composed of a memory cell group) and a redundancy selection circuit.
  • the memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit.
  • the redundancy selection circuit selects the memory cell group as a write destination of the write data and selects the read circuit of the memory cell group as the read destination of the read data. It consists of a redundant switch circuit that switches between redundant memory cell groups and a redundant decoding circuit that decodes redundant selection signals.
  • the redundant switch circuit switches the defective memory cell group to the redundant memory cell group. Perform (redundant selection). At this time, the redundant switch circuit switches the memory cell groups in accordance with the redundant selection signal input via the redundant decoding circuit. The redundancy selection signal is held in the redundancy setting latch.
  • the redundancy setting is defined using a 2-bit redundancy selection signal so that four redundancy settings can be decoded by each redundancy selection signal.
  • FIG. 12 is a diagram illustrating an example of a redundancy selection signal in the redundancy selection of a conventional memory cell. As shown in the figure, a 2-bit redundancy selection signal is set by a combination of “0” and “1”, and four redundancy settings are assigned to each.
  • redundancy selection signal “00” is input as a redundancy selection signal.
  • a redundancy selection signal “00” is held in the redundancy setting latch.
  • the redundancy selection circuit decodes the redundancy selection signal “00”, but the redundancy switch circuit does not switch to the redundancy memory cell group.
  • the memory cell group 2 is a defective memory cell. Then, “10” is input as the redundancy selection signal. A redundancy selection signal “1 0” is held in the redundancy setting latch. The redundancy selection circuit decodes the redundancy selection signal “10”, and the redundancy switch circuit switches to the redundancy memory cell group.
  • FIG. 13 is a diagram illustrating an example of a conventional redundancy selection circuit.
  • FIG. 2A shows an example of a redundant switch circuit
  • FIG. 2B shows an example of a redundant decode circuit.
  • FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG.
  • the redundant decoding circuit includes two inverter circuits, three AND circuits, and two OR circuit forces.
  • This redundant decode circuit outputs 3-bit redundant decode signals SEL0 to SEL2, which are select signals for the redundant switch circuit, as shown in FIG. 14, in response to 2-bit redundant selection signals RED0 to RED1.
  • the redundant switch circuit is configured by a combination of three sets of AND-OR equivalent circuits configured by a combination circuit of three NAND circuits.
  • This redundant switch circuit includes memory cell groups ARRAY0 to ARRAY2 and redundant memory cell group ARRAYR as shown in FIG. Switches the connection with OUT0 to OUT2.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2005-149667
  • the present invention has been made to solve the above-described problems caused by the prior art, and an object thereof is to provide a redundancy selection device and a redundancy selection method that can improve soft error resistance in redundancy selection.
  • the redundancy selection device of the present invention is connected to a memory cell and a redundancy memory cell constituting a storage device, and the memory cell or the redundancy memory cell
  • redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.
  • the redundant selection signal holding means in the redundant selection device of the present invention is characterized by comprising a scan latch means.
  • the redundancy decoding means in the redundancy selection device of the present invention associates at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result when decoding the redundancy selection signal. It is characterized by being configured.
  • the redundancy selection signal in the redundancy selection device of the present invention is composed of n bits (n> 1), and the redundancy decoding means includes k bits (0 ⁇ k) of the n bits constituting the redundancy selection signal. Even when ⁇ n—1) is inverted, the same redundancy setting as before the inversion is output as a decoding result.
  • the memory device of the present invention is connected to the memory cell, the redundant memory cell, the memory cell and the redundant memory cell, and selects either the memory cell or the redundant memory cell.
  • Redundancy selection means for performing redundancy selection, and the redundancy selection means is held in a redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell and in the redundancy selection information holding means.
  • redundant decoding means for outputting the same redundancy setting as before decoding as a decoding result, and based on the decoding result
  • redundant switch means for selecting input / output of either the memory cell or the redundant memory cell.
  • the information processing apparatus includes a memory cell, a redundant memory cell, an arithmetic processing unit connected to the storage device, the memory cell and the redundant memory cell, and the memory cell Or redundancy selection means for performing redundancy selection for selecting any input / output of the redundant memory cell, wherein the redundancy selection means holds a redundancy selection signal indicating selection information of the memory cell.
  • the redundancy selection signal held in the holding means and the redundancy selection information holding means is inputted, and the part of the redundancy selection signal is inverted! Redundant decoding means for outputting as a decoding result, and redundant switching means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result.
  • the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit.
  • Latch means and fuse means connected to the scan latch means for setting a redundancy selection signal, outputting the redundancy selection signal set in the fuse means to the scan latch means, and performing the scan shift.
  • the redundancy selection signal is held in the redundancy selection signal holding means.
  • the information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift performed by a scan clock output from the TAP controller, and a scan that includes the redundancy selection signal holding unit.
  • the redundancy selection signal holding means includes the latch means and a scan input connected to the scan latch means, and inputs the redundancy selection signal from the scan input and performs the scan shift, so that the redundancy selection signal is held in the redundancy selection signal holding means. It is characterized by holding a signal.
  • the redundancy selection method of the present invention is a memory cell redundancy selection method for selecting input / output of either a memory cell or a redundant memory cell constituting a storage device, wherein the selection of the memory cell is performed.
  • a step of holding a redundant selection signal indicating information and a case where the held redundant selection signal is input and a part of the redundant selection signal is inverted! /! The step of outputting the same redundancy setting as the decoding result even before inversion, and the selection of the input / output of either the memory cell or the redundant memory cell based on the decoding result And a step of performing.
  • the redundancy selection method even when the retained redundancy selection signal is input and a part of the redundancy selection signal is inverted, the same redundancy setting as before the inversion is performed.
  • the step of outputting as a decoding result at least two or more redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.
  • the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell is held in advance, and a part of the redundancy selection signal is changed by inputting the redundancy selection signal. Even in this case, the same redundancy setting as before the change was derived, and based on the derived redundancy setting! /, The memory cell was replaced, so the redundancy selection signal held by the influence of radiation from space, etc. Even if a soft error occurs, the redundancy selection can be performed correctly, so that the soft error tolerance in the redundant selection can be improved.
  • the redundancy selection signal is composed of n bits (n> 1), and k bits (0 ⁇ k ⁇ n—1) of n bits constituting the redundancy selection signal. Even if is reversed, it is configured to derive the same redundancy setting as that associated with the redundancy selection signal before the inversion, so that a soft error has occurred in the retained redundancy selection signal. However, if k bits (0 ⁇ k ⁇ n—1) of n bits that make up the redundancy selection signal are inverted, the redundancy selection can be performed correctly, improving the soft error tolerance in the redundancy selection. If you can!
  • k bits (0 ⁇ k ⁇ n-1) are inverted with respect to a predetermined bit among n bits ( ⁇ > 1) constituting the redundancy selection signal,
  • n bits ( ⁇ > 1) constituting the redundancy selection signal
  • the same redundancy setting as that associated with the redundancy selection signal before inversion is derived, so that the redundancy selection signal can be determined by limiting the bits from which the same redundancy setting can be derived even if it is inverted. Even when the number of bits that can be used for the selection is limited, the soft error tolerance in redundancy selection can be improved.
  • n signals that constitute a redundancy selection signal. Inverting up to k bits (0 ⁇ k ⁇ n—1) in a set (n> 1), the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. As a result, it is possible to improve the resistance to soft errors in the redundant selection with a focus on the redundant setting having a high probability of being actually set among a plurality of redundant settings.
  • the redundant setting in which the memory cell is not replaced up to k bits (0 ⁇ k ⁇ n—1) out of n bits (n> 1) constituting the redundancy selection signal. Even if it is inverted, it is configured to derive the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion, so there is a high probability that it will actually be set, and redundancy that does not replace the memory cell It is possible to improve the tolerance of soft errors in redundant selection with emphasis on setting!
  • any one bit of n bits ( ⁇ > 1) constituting the redundant selection signal is inverted, it is associated with the redundant selection signal before being inverted. Since the same redundancy setting as the redundancy setting is derived, even if a soft error has occurred in the retained redundancy selection signal, one of the n bits that make up the redundancy selection signal is inverted. In such a case, since the redundant selection can be performed correctly, the soft error resistance in the redundant selection can be improved.
  • the redundant setting that is the same as the redundant setting associated with the redundant selection signal before the configuration is derived, the redundant setting that has a high probability of being actually set is selected among the redundant settings. There is an effect that resistance to soft errors can be improved.
  • one bit out of n bits (n> 1) constituting the redundancy selection signal is inverted by redundancy setting. Even if it is, the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived, so there is a high probability that it will actually be set, and the redundancy that does not replace the memory cell If you can improve the tolerance of soft errors in the redundant selection with emphasis on the setting!
  • FIG. 1 is an explanatory diagram for explaining an outline of redundancy selection according to the present embodiment.
  • FIG. 2 is a block diagram showing a configuration of a RAM macro according to the present embodiment.
  • FIG. 3 is a diagram illustrating an example of redundancy setting according to the present embodiment.
  • FIG. 4 is a flowchart showing an algorithm for generating the redundant selection signal shown in FIG.
  • FIG. 5 is a diagram showing an example of assigning two redundancy selection signals to one redundancy setting.
  • FIG. 6 is a flowchart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a specific redundancy setting with priority.
  • FIG. 7 is a diagram showing an example in which a redundancy selection signal is assigned to a specific redundancy setting.
  • FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in a case where 2-digit inversion data is further assigned to a specific redundancy setting.
  • FIG. 9 is a diagram showing an example in the case of further assigning redundant selection signals remaining in a specific redundancy setting.
  • FIG. 10 is a diagram showing an example of a redundancy decoding circuit with redundancy setting shown in FIG.
  • FIG. 11 is a diagram showing an example of conventional redundant selection of memory cells.
  • FIG. 12 is a diagram showing an example of a redundancy selection signal in redundancy selection of a conventional memory cell.
  • FIG. 13 is a diagram showing an example of a conventional redundancy selection circuit.
  • FIG. 14 is a diagram showing a list of signals generated by the redundant switch circuit and the redundant decoding circuit shown in FIG. 13.
  • FIG. 1 is an explanatory diagram for explaining an outline of redundant selection according to the present embodiment.
  • the LSI chip 1 shown in the figure includes a plurality of fuses 2 to 2, a plurality of latch trains 3 to 3, a plurality of RAM macros 4 to 4, and a plurality of fuses.
  • a processor core unit 6 that uses 1 5 1 m I n number of RAM macros as cache memory and a TAP (Test Access Port) controller 7 that controls scan of a plurality of latch rows are arranged.
  • Each of the latch trains 3 to 3 includes a plurality of scan latches.
  • H-rows 3 to 3 are connected in a daisy chain to form a scan chain with a scan latch
  • Latch row 3 has fuse 2 to 2 force Latch row 3 has RAM macro 4 to 4
  • the scan chain has a scan-in terminal as an input from the outside in the LSI chip 1 and a scan-out terminal as an output to the outside.
  • the scan chain can be controlled by a TAP controller 7 that is compliant with the JTAG Origin Test Architecture Group (compliant with IEEE 1149.1).
  • Each of the RAM macros 4 to 4 includes a plurality of memory cell groups and a redundant memory.
  • each RAM macro 4-4 has a cell group (reserve memory cell group) and a redundancy selection circuit.
  • the memory cell groups in each RAM macro 4-4 are inspected by pre-shipment testing of LSI chip 1.
  • the redundant setting is performed using a redundant selection signal.
  • the redundant selection signal here is a signal indicating which one of the plurality of memory cell groups is to be replaced with the redundant memory cell group, and is output from the fuse when the fuses 2 and 2 are cut.
  • the redundancy selection signal generated in this way is stored bit by bit in the latch of latch column 3,
  • a scan clock input (not shown) from the TAP controller 7 is scan-shifted via the scan chain (latch column 3 to latch column 3) and finally the redundancy of the latch column 3
  • the latching force is the same as the number of bits of the long selection signal.
  • each RAM macro is connected to a plurality of memory cell groups, a redundancy memory cell group, and redundancy setting latches 5 to 5 in the latch column 3.
  • the redundancy selection circuit inputs the redundancy selection signal held in the redundancy setting latches 5 to 5.
  • the defective memory cell group and the redundant memory cell group are replaced according to the decoding result of the input redundancy selection signal by the redundancy decoding circuit.
  • the redundant selection signal is generated using the
  • the scan-in terminal force may also be generated by directly scanning and shifting the redundant selection signal.
  • FIG. 2 is a block diagram showing the configuration of the RAM macro according to the present embodiment.
  • the redundancy selection circuit 20 in this RAM macro includes three memory cell groups 10 to 10 and
  • Memory cell groups 1 to 3 are connected.
  • Each redundant memory cell group has a read circuit and a write circuit.
  • the redundancy selection circuit 20 is a redundancy decoding circuit 21 that decodes a redundancy selection signal, and a selection of a write circuit of a memory cell group that is a write destination of write data and a read destination of the read data.
  • the redundant switch circuit 22 is configured to switch between the recell group and the redundant memory cell group.
  • the redundant switch circuit 22 includes the memory cell groups 10 to 10 and the redundant memory circuit.
  • Redundant decode circuit 21 connected to resell group 10 and redundant setting latches 5 to 5
  • the redundancy decode circuit 21 has a redundancy selection signal held in the redundancy setting latches 5 to 5.
  • the redundancy setting of the memory cell group is determined, and a redundancy decode signal for controlling the redundancy switch circuit is outputted.
  • the redundancy selection signal originally set in the redundancy setting latches 5 to 5 is one redundancy setting signal.
  • the value of the redundancy selection signal that should have been retained may change, so that decoding for redundancy setting that should be performed may not be output correctly.
  • the redundancy decoding circuit 21 indicates that the original redundancy selection signal is indicated even if one of the bits constituting the redundancy selection signal is inverted, V, or one of the bits! / Configure so that redundant settings can be judged.
  • the method for determining this redundancy setting is described below.
  • FIG. 3 is a diagram illustrating an example of the redundant selection setting according to the present embodiment.
  • the number of bits required for redundant setting is 2 bits, but in order to improve soft error tolerance, it is possible to further increase the bit width of redundant setting and increase the decoding pattern.
  • the number of bits of the redundancy setting signal is increased by 3 bits from the originally required 2 bits to 5 bits, each redundancy setting is first set in the redundancy setting latch. Assign one redundant selection signal to
  • any one of the memory cell groups 10 to 10 is a redundant memory cell.
  • the redundancy selection circuit 20 By decoding the redundancy setting based on the redundancy selection signal thus assigned and the 1-bit inverted data of the redundancy selection signal, the redundancy selection circuit 20 has the redundancy setting latches 5-5. If there is a soft error in the redundant selection signal held in
  • the redundancy switch circuit 22 replaces the defective memory cell group and the redundancy memory cell group 10 based on the redundancy setting decoded by the redundancy decoding circuit 21 (redundancy selection).
  • redundant selection is shown when a defective memory cell group is incapacitated.
  • the redundancy selection signal “00000” is set in the redundancy setting latch, it is determined that the redundancy decoding circuit 21 does not select redundancy, but the redundancy selection signal power 00001 ”,“ 00010 ”, Even if it is changed to “00100”, “01000”, or “10000”, it is determined by the redundant decoding circuit 21 that redundant selection is not performed.
  • FIG. 2B a case where a failure occurs in the memory cell group 2 is shown.
  • the redundancy selection signal “11001” is set in the redundancy setting latch
  • the power redundancy selection signal is “11000”, “11” which is determined to replace the memory cell group 2 and the redundancy memory cell group. Even if it is changed to “011”, “11101”, “10001” or “01001”, it is determined that the memory cell group 2 and the redundant memory cell group are exchanged.
  • the redundant decode circuit 21 is redundantly held in the redundancy setting latches 5 to 5.
  • the redundancy setting latch is determined by determining that the redundancy setting is the same as
  • the soft error rate per latch is ser (Soft ERror), for example, in the redundancy setting of the conventional memory cell in FIG. 12 described above, a 2-bit redundancy selection signal is used for one redundancy setting. Are assigned one by one, so the soft error rate SERO in the redundant selection is
  • the soft error resistance is increased by about 200 times.
  • FIG. 4 is a flowchart showing an algorithm for generating the redundancy selection signal shown in FIG.
  • a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined.
  • This data variable is set to a binary number.
  • “0” is set as an initial value for all bits of this data variable (step S101). For example, if the redundant selection signal is 5 bits, set “00000”.
  • 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S102). f, for example, when the redundant selection signal power S is “00000”, 5 bits of 1-bit inverted data of “00001”, “00010”, “00100”, “01000” and “10000” are created. .
  • the data variable is assigned to the redundancy selection signal (step S103), and the data variable and the 1-bit inverted data of the data variable are all assigned to the redundancy selection signal. It is registered in the used list indicating that it cannot be used (step S104).
  • step S105 1 is added to the data variable to make it a new data variable (step S105), and 1-bit inverted data of the new data variable is created (step S106).
  • step S107 the new data variable and the 1-bit inverted data of the data variable are compared with the contents of the used list. If the used list already contains the data variable or data with the same value as the 1-bit inverted data of the data variable (step S108, Yes), return to step S105 to add a new data variable. Set and repeat the process from step S106.
  • step S108 when the used list does not include the data variable and the data having the same value as the 1-bit inverted data of the data variable (step S108, No), the data variable is set to the redundant selection signal. (Step S109), and the data variable and the 1-bit inverted data of the data variable are registered in the used list (step S110).
  • step S111 when the necessary number of redundant selection signals are assigned to the data variable (step S111, Yes), the process is terminated. If the necessary number is not satisfied (step Sill, No), the process returns to step S105, a new data variable is set, and the processing after step S106 is repeated.
  • the redundancy selection signal generated by the above algorithm and the 1-bit inverted data of each redundancy selection signal are allocated to the redundancy setting.
  • FIG. 5 is a diagram showing a case where two redundancy selection signals are assigned to one redundancy setting.
  • there are 8 redundancy settings and a 4-bit redundancy selection signal is used, and for each redundancy setting, there is one redundancy selection signal and one redundancy selection signal. Allocate 1-bit inverted data.
  • redundancy selection signal is equally assigned to each redundancy setting indicating the replacement pattern of the memory cell so far, but by assigning more redundancy selection signals to a specific pattern, This can be achieved by improving the soft error tolerance with emphasis on patterns.
  • FIG. 6 is a flow chart showing a redundancy selection signal generation algorithm when a redundancy selection signal is assigned to a redundancy setting when no redundancy selection is performed as a specific redundancy setting.
  • a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined.
  • This data variable is set to a binary number.
  • “0” is set as an initial value in all bits of the data variable (step S 201). For example, if it is a redundant selection variable force bit, set “0000”.
  • 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S202). For example, in the case of the redundant selection signal power bit, four types of inverted data “0001”, “0010”, “010 0”, and “1000” are created.
  • the data variable is assigned to the redundancy selection signal (step S203), and all the data variable and 1-bit inverted data of the data variable are registered in the used list (step S204).
  • step S206 the data variable is compared with the used list (step S206). If the used list already contains data with the same value as the data variable (step S207, Yes), the process returns to step S205, sets a new data variable, and repeats the processing from step S206.
  • step S207, No if the used list does not contain data having the same value as the data variable (step S207, No), the data variable is assigned to the redundant selection signal (step S208), and further The data variable is registered in the used list (step S209).
  • step S210 when the necessary number of redundant selection signals are assigned to the data variable (step S210, Yes), the process is terminated. If the required number is not satisfied (step S210, No), the process returns to step S205 to set a new data variable, and the processes after step S206 are repeated.
  • FIG. 7 is a diagram illustrating an example in which a redundancy selection signal is assigned to a specific redundancy setting.
  • a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit.
  • redundancy selection signal “0000” with all bits set to “0” and 1-bit inverted data “0001” for each bit.
  • ”,“ 0010 ”,“ 0100 ”and“ 1000 ”in total allotting 5 redundant selection signals and replacing the redundant memory cell groups with other memory cell groups 1 to 7 Assign redundant selection signals one by one.
  • the redundancy selection signal generation method shown in Fig. 6 the case has been described in which the redundancy selection signal is assigned with priority to a specific redundancy setting.
  • the power of assigning 1-bit inverted data so that the redundancy setting can be determined even if only 1 bit is inverted in the redundancy selection signal assigned to that redundancy setting.
  • the redundant setting may be determined even if the 2 bits are inverted.
  • FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in the case where 2-bit inverted data is further assigned to a specific redundancy setting.
  • this redundant selection signal generation algorithm first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary number. Then, “0” is set as an initial value in all bits of the data variable (step S301). For example, if it is a redundant selection variable force bit, set “0000”.
  • 1-bit inverted data obtained by inverting only 1 bit of the data variable and 2-bit inverted data obtained by inverting 2 bits are created (step S302).
  • the redundancy selection signal is 4 bits
  • four types of 1-bit inverted data of “0001”, “0010”, “0100”, and “1000”, “0011”, “0101”, “ A total of 10 inverted data consisting of 6 2-bit inverted data of “0110”, “1001”, “1010” and “1100” is created.
  • the data variable is assigned to the redundancy selection signal (step S303), and the data variable, the 1-bit inverted data and the 2-bit inverted data of the data variable are all registered in the used list (step S303). S304).
  • step S305 1 is added to the data variable to make this a new data variable.
  • step S305 the new data variable is compared with the used list (step S306). If the used list already contains data with the same value as the relevant data variable (step S307, Yes), the data variable will be the maximum value represented by the given number of bits (eg “1111”). It is determined whether or not there is (step S311).
  • step S311, Yes If the data variable is equal to the maximum value represented by the given number of bits (eg, "1111") (step S311, Yes), until the required number is satisfied for the data variable, The 2-bit inverted data in the used list is assigned to the redundancy selection signal (step S312). On the other hand, if the data variable is weak at the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated. If the used list does not contain data with the same value as the data variable (Step S307, No), the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).
  • the data variable is assigned to the redundant selection signal (Step S308), and the data variable Is registered in the used list (step S309).
  • step S310, Yes when the necessary number of redundant selection signals are assigned to the data variable (step S310, Yes), the process is terminated. If the required number is not satisfied (step S310, No), it is determined whether or not the data variable is the maximum value represented by the given number of bits.
  • step S311, Yes If the data variable has the maximum value (step S311, Yes), the 2-bit inverted data in the used list is assigned to the redundant selection signal until the required number is satisfied (step S312). On the other hand, when the data variable is weak at the maximum value (step S311, No), the process returns to step S305 to set a new data variable and repeats the processing after step S306.
  • Redundancy settings are assigned using the redundancy selection signal generated by the above algorithm and the 1-bit inverted data and 2-bit inverted data of the redundancy selection signal with all bits being “0”.
  • FIG. 9 is a diagram showing an example in which redundant selection signals remaining for a specific redundant setting are further allocated.
  • a 4-bit redundancy selection signal is used, and for redundancy setting without redundancy selection, a redundancy selection signal with all bits set to “0”, all 1-bit inverted data, and 2-bit inverted data.
  • Memory cells that are assigned to the redundant selection signal. Redundant selection signals are assigned to each of the seven redundancy settings that replace redundant memory cell groups with groups 1-7.
  • FIG. 10 is a diagram showing an example of a redundant decoding circuit based on the redundant setting shown in FIG.
  • the redundant decoding circuit of the example shown in the figure also consists of four inverter circuits, seven AND circuits, and six OR circuit powers.
  • This redundant decode circuit outputs 7-bit redundant decode signals SEL0 to SEL6 in response to 4-bit redundant select signals RED0 to RED3.
  • the redundant decode signals SEL0 to SEL6 output by decoding the 4-bit redundancy selection signals RED0 to RED3 are "0000000", “1111111”, “1111110”, “1111 100", “1111000”, There are 8 types of “1110000”, “1100000” and “1000000”. Each of these redundant decode signals SEL0 to SEL6 is associated with eight redundancy settings. Then, based on these redundant decode signals SEL0 to SEL6, the redundant setting of the memory cell group is performed by the redundant switch circuit.
  • the redundancy setting latch 5 to 5 force memory cell group
  • the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the group is held in advance, and the redundancy selection circuit 21 inverts even when a part of the redundancy selection signal is inverted by inputting this redundancy selection signal.
  • the redundancy setting same as the redundancy setting associated with the previous redundancy selection signal is derived, and the redundancy switch circuit 22 replaces the memory cell group based on the derived redundancy setting.
  • the redundancy selection signal held in the redundancy setting latches 5 to 5 caused a soft error due to
  • the redundancy selection device and the redundancy selection method according to the present invention are useful for a semiconductor memory device that performs redundancy selection in which a defective memory cell is replaced with a redundancy memory cell, and in particular, controls redundancy selection such as a redundancy selection signal.
  • LSI such as DSP (Digital Signal Processor) and SOC (System On Chip).

Abstract

La présente invention concerne un dispositif de sélection de redondance de mémoire qui comprend des verrous de paramétrage de redondance (51-5n) pour maintenir au préalable des signaux de sélection de redondance correspondant à des jeux redondants indicatifs du remplacement des motifs de groupes de cellule mémoire, un circuit de décodage de redondance (21) pour dériver les mêmes jeux redondants que ceux correspondant aux signaux de sélection de redondance avant que les signaux ne soient inversés, même lorsque les signaux de sélection de redondance sont entrés et qu'une partie est inversée, ainsi qu'un circuit de commutation redondant (22) pour remplacer les groupes de cellules de mémoire basés sur des jeux de redondance dérivés.
PCT/JP2006/303153 2005-12-19 2006-02-22 Dispositif de selection de redondance de memoire, dispositif de memoire, dispositif de traitement des informations et procede de selection de redondance de cellule de memoire WO2007072580A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005-365544 2005-12-19
JP2005365544A JP2007172690A (ja) 2005-12-19 2005-12-19 メモリ冗長選択装置、記憶装置、情報処理装置およびメモリセルの冗長選択の方法

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WO2007072580A1 true WO2007072580A1 (fr) 2007-06-28

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001229690A (ja) * 2000-02-10 2001-08-24 Hitachi Ltd 半導体集積回路装置
JP2003317497A (ja) * 2002-04-24 2003-11-07 Hitachi Ltd 半導体集積回路装置の製造方法
JP2005116003A (ja) * 2003-10-03 2005-04-28 Toshiba Corp 半導体集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001229690A (ja) * 2000-02-10 2001-08-24 Hitachi Ltd 半導体集積回路装置
JP2003317497A (ja) * 2002-04-24 2003-11-07 Hitachi Ltd 半導体集積回路装置の製造方法
JP2005116003A (ja) * 2003-10-03 2005-04-28 Toshiba Corp 半導体集積回路

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