JP2007172690A - Memory redundancy selection device, memory system, information processor, and redundancy selection method for memory cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the soft error resistance when selecting redundant memory cells in a semiconductor memory system. <P>SOLUTION: The redundancy setup latches 5<SB>1</SB>-5<SB>n</SB>store in advance the redundancy selection signals associated with the redundancy setup showing the memory cell group replacement pattern. Even when this redundancy decoding circuit 21 inputs this redundancy selection signal to partly reverse, this device derives the same redundancy setup as the redundancy selection signals before the reversion, and the redundancy switch circuit 22 replaces the memory cell groups based on the derived redundancy setup. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a redundancy selection of a memory cell for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor storage device such as a RAM incorporated in an LSI such as a processor. More particularly, the present invention relates to a memory redundancy selection device, a storage device, an information processing device, and a memory cell redundancy selection method that can improve soft error tolerance in redundancy selection.

  2. Description of the Related Art Conventionally, a processor incorporating a semiconductor memory device such as a RAM as a cache memory, or an LSI such as a DSP (Digital Signal Processor) or an SOC (System On Chip) has a spare memory cell called a redundant memory cell in preparation for manufacturing defects. Technology that remedies defective memory cells by replacing defective memory cells and redundant memory cells when a defective memory cell is detected in a test prior to shipment, etc. mounted on a semiconductor chip (hereinafter redundant selection) Is used).

  As a method for replacing this defective memory cell, the address of the defective memory cell is set by cutting a fuse arranged on the semiconductor chip, and the defective memory cell indicated by the address is changed using a circuit for switching the memory cell. A technique for switching to a redundant memory cell has been devised (see, for example, Patent Document 1).

  As described above, when a memory cell is replaced using a signal for replacing a defective memory cell with a redundant memory cell (hereinafter referred to as a redundant selection signal), this signal is used to replace the memory cell from the fuse. May be directly input to the circuit (hereinafter referred to as a redundancy selection circuit), but may be input via a scan chain constituted by scan latches arranged on the chip in order to avoid complicated wiring. .

  FIG. 11 is a diagram showing an example of redundant selection of a conventional memory cell. The RAM macro shown in FIG. 1 is composed of three memory cell groups 1 to 3, one redundant memory cell group (spare memory cell group), and a redundant selection circuit, thereby forming a memory cell. . Memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit. Here, the redundancy selection circuit selects the write circuit of the memory cell group that is the write destination of the write data and the read circuit of the memory cell group that is the read destination of the read data, thereby A redundant switch circuit for switching to a redundant memory cell group and a redundant decoding circuit for decoding a redundant selection signal are configured.

  When a defective memory cell group including a defective memory cell is detected among the three memory cell groups by a test before shipping, etc., the redundant switch circuit switches the defective memory cell group to the redundant memory cell group (redundant selection). )I do. At this time, the redundant switch circuit switches the memory cell group in accordance with the redundant selection signal input through the redundant decoding circuit. The redundancy selection signal is held in the redundancy setting latch.

  Here, in the RAM macro of the example shown in FIGS. 11A and 11B, since there is a defective memory cell group, one of the three memory cell groups is replaced with a redundant memory cell group, and There are four possible redundant settings, including the case where no cell group exists and no replacement is performed (redundancy is not selected).

  Further, here, the redundancy setting is defined using a 2-bit redundancy selection signal so that four redundancy settings can be decoded by each redundancy selection signal. FIG. 12 is a diagram illustrating an example of a redundancy selection signal in redundancy selection of a conventional memory cell. As shown in the figure, a value is set by a combination of “0” and “1” to a 2-bit redundancy selection signal, and four types of redundancy settings are assigned.

  In the example shown in FIG. 11A, “00” is input as the redundancy selection signal because there is no memory cell group including a defective memory cell in the memory cell groups 1 to 3. The redundancy setting latch holds the redundancy selection signal “00”. The redundant decode circuit decodes the redundant selection signal “00”, but the redundant switch circuit does not switch to the redundant memory cell group.

  In the example shown in FIG. 11B, since the memory cell group 2 is a defective memory cell, “10” is input as the redundancy selection signal. The redundancy setting latch holds a redundancy selection signal “10”. The redundancy selection circuit decodes the redundancy selection signal “10”, and the redundancy switch circuit switches to the redundancy memory cell group.

  FIG. 13 is a diagram showing an example of a conventional redundancy selection circuit. FIG. 2A shows an example of a redundant switch circuit, and FIG. 2B shows an example of a redundant decode circuit. FIG. 14 is a list of signals generated by the redundant switch circuit and the redundant decode circuit shown in FIG.

  As shown in FIG. 13B, the redundant decode circuit is composed of two inverter circuits, three AND circuits, and two OR circuits. This redundant decode circuit outputs 3-bit redundant decode signals SEL0 to SEL2, which are select signals for the redundant switch circuit, as shown in FIG. 14, in response to 2-bit redundant selection signals RED0 to RED1.

  Further, as shown in FIG. 13A, the redundant switch circuit is configured by a combination of three sets of AND-OR equivalent circuits configured by a combination circuit of three NAND circuits. As shown in FIG. 14, the redundant switch circuit includes memory cell groups ARRAY0 to ARRAY2 and redundant memory cell group ARRAYR, and output terminals OUT0 to OUT0 in response to redundant decode signals SEL0 to SEL2, which are select signals output from the redundant decode circuit. Switches the connection with OUT2.

JP 2005-149667 A

  However, in the redundant selection of the memory cell described above, when a soft error occurs in the redundant selection signal held in the latch due to the influence of α rays (helium (He) nuclei) falling from the universe to the earth, that is, redundant selection. When the set value of the signal is inverted bit by bit, there is a problem that the redundant selection of the memory cell cannot be performed correctly.

  The present invention has been made to solve the above-described problems caused by the prior art, and an object of the present invention is to provide a redundant selection device and a redundant selection method that can improve soft error tolerance in redundant selection.

  In order to solve the above-described problems and achieve the object, a redundancy selection device of the present invention is connected to a memory cell and a redundancy memory cell constituting a storage device, and either the memory cell or the redundancy memory cell is inserted. A redundancy selection device for performing redundancy selection for selecting an output, the redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell, and the redundancy selection signal held in the redundancy selection information holding means And when the redundancy selection signal is partially inverted, redundant decoding means for outputting the same redundancy setting as before decoding as a decoding result, and based on the decoding result, the memory cell or Redundant switch means for selecting input / output of any one of the redundant memory cells.

  Further, the redundant selection signal holding means in the redundant selection device of the present invention is constituted by a scan latch means.

  Further, the redundancy decoding means in the redundancy selection device of the present invention is configured such that, when decoding the redundancy selection signal, at least two or more redundancy selection signals are associated as inputs for the same redundancy setting output as a decoding result. It is characterized by being configured.

  In the redundancy selection device of the present invention, the redundancy selection signal is composed of n bits (n> 1), and the redundancy decoding means includes k bits (0 <k ≦ n−) of the n bits constituting the redundancy selection signal. Even when 1) is inverted, the same redundancy setting as before the inversion is output as a decoding result.

  Further, the memory device of the present invention is connected to the memory cell, the redundant memory cell, the memory cell and the redundant memory cell, and selects a memory cell or an input / output of the redundant memory cell. Redundant selection means for performing redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell, and redundancy selection held in the redundancy selection information holding means A redundancy decoding means for inputting a signal and outputting the same redundancy setting as a decoding result even when a part of the redundancy selection signal is inverted, as a decoding result, and based on the decoding result, the memory cell Or redundant switch means for selecting input / output of any one of the redundant memory cells.

  The information processing apparatus according to the present invention includes a memory cell, a redundant memory cell, an arithmetic processing unit connected to the storage device, the memory cell and the redundant memory cell, and the memory cell or the redundant memory cell. Redundancy selection means for performing redundancy selection for selecting any input / output of the memory cell, and the redundancy selection means includes redundancy selection signal holding means for holding a redundancy selection signal indicating selection information of the memory cell; Redundant decoding that inputs the redundant selection signal held in the redundant selection information holding means and outputs the same redundant setting as a decoding result even when part of the redundant selection signal is inverted And redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result. .

  The information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift that performs a scan shift by a scan clock output from the TAP controller, and includes the redundant selection signal holding unit; Fuse means for setting a redundancy selection signal connected to the scan latch means, outputting the redundancy selection signal set in the fuse means to the scan latch means, and performing the scan shift, thereby making the redundancy The redundant selection signal is held in the selection signal holding means.

  The information processing apparatus of the present invention further includes a TAP controller that performs scan shift control, a scan shift that performs a scan shift by a scan clock output from the TAP controller, and includes the redundant selection signal holding unit; A scan input connected to the scan latch means, the redundancy selection signal is inputted from the scan input, and the redundancy selection signal holding means holds the redundancy selection signal by performing the scan shift. It is characterized by.

  The redundant selection method of the present invention is a redundant selection method of a memory cell for selecting input / output of either a memory cell constituting a storage device or a redundant memory cell, and indicates selection information of the memory cell. A step of holding a redundancy selection signal; and inputting the held redundancy selection signal and outputting the same redundancy setting as a decoding result even when a part of the redundancy selection signal is inverted And a step of selecting input / output of either the memory cell or the redundant memory cell based on the decoding result.

  In the redundancy selection method of the present invention, even when a part of the redundancy selection signal is inverted by inputting the held redundancy selection signal, the same redundancy setting as before the inversion is used as a decoding result. In the step of outputting, at least two or more redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.

  According to the present invention, the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell is held in advance, and even when a part of the redundancy selection signal is changed by inputting this redundancy selection signal, the change occurs. The same redundancy setting as before was derived, and the memory cells were replaced based on the derived redundancy setting. Therefore, a soft error occurred in the redundancy selection signal held by the influence of radiation from space. Even in such a case, since the redundant selection can be performed correctly, the soft error tolerance in the redundant selection can be improved.

  Further, according to the present invention, the redundancy selection signal is composed of n bits (n> 1), and k bits (0 <k ≦ n−1) of the n bits constituting the redundancy selection signal are inverted. Even if a soft error has occurred in the retained redundancy selection signal, the redundancy selection signal is generated because the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. When k bits (0 <k ≦ n−1) are inverted among n bits that constitute N, the redundancy selection can be performed correctly, so that the soft error resistance in the redundancy selection can be improved. Play.

  Further, according to the present invention, even when a predetermined bit out of n bits (n> 1) constituting the redundant selection signal is inverted up to k bits (0 <k ≦ n−1), The number of bits that can be used for the redundant selection signal by limiting the number of bits that can be derived even if it is inverted, because the same redundant setting as the redundant setting associated with the redundant selection signal is derived. Even when the limit is limited, it is possible to improve the soft error resistance in the redundant selection.

  Further, according to the present invention, a specific redundancy setting is inverted even when k bits (0 <k ≦ n−1) of n bits (n> 1) constituting the redundancy selection signal are inverted. Since it is configured to derive the same redundancy setting as the redundancy setting associated with the previous redundancy selection signal, among the redundancy settings, the redundancy selection software that focuses on the redundancy setting that has a high probability of being actually set is selected. There is an effect that error tolerance can be improved.

  Further, according to the present invention, with respect to the redundancy setting in which the memory cell is not replaced, up to k bits (0 <k ≦ n−1) of n bits (n> 1) constituting the redundancy selection signal are inverted. In this case, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived. Therefore, the redundancy setting that does not replace the memory cell with high probability of being actually set is emphasized. In addition, the soft error tolerance in the redundant selection can be improved.

  Further, according to the present invention, even when any one bit of n bits (n> 1) constituting the redundancy selection signal is inverted, the redundancy setting associated with the redundancy selection signal before being inverted Since the same redundancy setting is derived, even if a soft error has occurred in the retained redundancy selection signal, if any one of the n bits constituting the redundancy selection signal is inverted Since the redundant selection can be performed correctly, the soft error resistance in the redundant selection can be improved.

  According to the present invention, for a specific redundancy setting, even if any one of n bits (n> 1) constituting the redundancy selection signal is inverted, the redundancy selection signal before being inverted Since it is configured to derive the same redundancy setting as the associated redundancy setting, among the multiple redundancy settings, the tolerance of soft errors in redundancy selection is improved with a focus on redundancy settings that have a high probability of being actually set. There is an effect that can be.

  Further, according to the present invention, for redundancy setting in which memory cells are not replaced, even if one of the n bits (n> 1) constituting the redundancy selection signal is inverted, it is not inverted. Since the same redundancy setting as that associated with the redundancy selection signal is derived, a soft error in the redundancy selection is focused on the redundancy setting that does not replace the memory cell with a high probability of being actually set. There is an effect that the tolerance of the can be improved.

  Exemplary embodiments of a redundancy selection device and a redundancy selection method according to the present invention will be described below in detail with reference to the accompanying drawings.

First, an outline of redundant selection according to the present embodiment will be described. FIG. 1 is an explanatory diagram for explaining an overview of redundant selection according to the present embodiment. In the LSI chip 1 shown in the figure, a plurality of fuses 2 ₁ to 2 ₅ , a plurality of latch rows 3 _{1 to} 3 _m , a plurality of RAM macros 4 ₁ to 4 _n, and a plurality of RAM macros are used as cache memories. A processor core unit 6 to be used and a TAP (Test Access Port) controller 7 that performs scan control of a plurality of latch rows are arranged.

Each of the latch trains 3 _{1 to} 3 _m includes a plurality of scan latches, and all the latch trains 3 _{1 to} 3 _m are connected in a daisy chain to form a scan chain by the scan latches. Further, the fuse 2 ₁ to 2 ₅ to latch column 3 _1, RAM macro 4 ₁ to 4 _n are connected to the latch column 3 _n. Further, the scan chain has a scan-in terminal as an input from the outside in the LSI chip 1 and a scan-out terminal as an output to the outside. For example, the control of the scan chain can be performed by a TAP controller 7 compliant with JTAG (Joint Test Architecture Group) compliant with IEEE 1149.1.

Each of the RAM macros 4 ₁ to 4 _n has a plurality of memory cell groups, a redundant memory cell group (a spare memory cell group), and a redundant selection circuit. The memory cell groups of the RAM macros 4 ₁ to 4 _n are inspected by a pre-shipment test of the LSI chip 1. In this pre-shipment test, when a memory cell group including a defective memory cell is detected, a setting for replacing the defective memory cell group with a redundant memory cell group (redundancy setting) is performed for each RAM macro.

Such redundancy setting is performed using a redundancy selection signal. The redundant selection signal here is a signal indicating which one of the plurality of memory cell groups is replaced with the redundant memory cell group, and is output from the fuse by cutting the fuses 2 ₁ to _25. It is generated by combining signals of “0” and “1” with a predetermined number of bits.

Thus generated redundancy selection signal is stored bit by bit in the latch of the latch column 3 _1, the scan clock input from the TAP controller 7 (not shown), the scan chain (latch columns 3 ₁ to latch column 3 _m ), and is finally held in the redundancy setting latches 5 _{1 to} 5 _n of the latch train 3 _m . Each of the redundancy setting latches 5 _{1 to} 5 _n is composed of the same number of latches as the number of bits of the redundancy selection signal.

The redundancy selection circuit of each RAM macro is connected to a plurality of memory cell groups, a redundancy memory cell group, and redundancy setting latches 5 _{1 to} 5 _{n of} the latch column 3 _m . The redundancy selection circuit receives the redundancy selection signal held in the redundancy setting latches 5 _{1 to} 5 _n , and determines a defective memory cell group and redundancy according to the decoding result of the input redundancy selection signal by the redundancy decoding circuit. Replace with memory cell group.

Here, a case has been described to generate a redundancy selection signal using the signal output from the fuse by cutting the fuse 2 ₁ to 2 _5, without using the fuses 2 ₁ to 2 _5, the scan -You may produce | generate by carrying out a scan shift of a redundant selection signal directly from an IN terminal.

Next, the configuration of the RAM macro according to the present embodiment will be described. FIG. 2 is a block diagram illustrating the configuration of the RAM macro according to the present embodiment. As shown in FIGS. 4A and 4B, the redundancy selection circuit 20 in this RAM macro is connected to three memory cell groups 10 ₁ to 10 ₃ and one redundant memory cell group 10 ₄ . Memory cell groups 1 to 3 and the redundant memory cell group each have a read circuit and a write circuit.

Further, the redundancy selection circuit 20 selects a redundancy decoding circuit 21 that decodes a redundancy selection signal, and selects a write circuit of a memory cell group that is a write destination of write data and a memory cell group that is a destination of read data. The redundant switch circuit 22 is configured to switch between a memory cell group and a redundant memory cell group by selecting a read circuit. The redundant switch circuit 22 includes the memory cell groups 10 ₁ to 10 ₃ and the redundant memory cell group. is connected to 10 _4, the redundant decode circuit 21 is connected to the redundant set latch 5 ₁ to 5 _n.

The redundancy decoding circuit 21 receives the redundancy selection signal held in the redundancy setting latches 5 _{1 to} 5 _n , determines the redundancy setting of the memory cell group based on the inputted redundancy selection signal, and the redundancy switch circuit A redundant decode signal for controlling the output is output. Here, the redundancy selection signal originally set in the redundancy setting latches 5 _{1 to} 5 _n should indicate one redundancy setting. However, when a soft error occurs in the redundancy setting latches 5 _{1 to} 5 _n , the value of the redundancy selection signal that should have been held changes, and therefore the decoding for the redundancy setting that should be performed is output correctly. It may not be done.

  Therefore, the redundancy decoding circuit 21 can determine the redundancy setting indicated by the original redundancy selection signal even when any one of the plurality of bits constituting the redundancy selection signal is inverted. Configure as follows. Hereinafter, a method for determining the redundancy setting will be described.

  FIG. 3 is a diagram illustrating an example of redundant selection setting according to the present embodiment. Originally, when the number of bits necessary for the redundancy setting is two bits, it is conceivable to further increase the bit width of the redundancy setting and increase the decoding pattern in order to improve the soft error resistance. As shown in the figure, for example, when the number of bits of the redundancy setting signal is increased by 3 bits from the originally required 2 bits to 5 bits, each redundancy setting is first set in the redundancy setting latch. One redundant selection signal is assigned.

In the example shown in FIG. 2, _four types of redundancy settings are conceivable, in which one of the memory cell groups 10 ₁ to 10 ₃ is replaced with the redundant memory cell group 10 ₄ and when no redundancy selection is performed. Therefore, among the four redundant selection signals, “00000” is assigned to the case where no redundant selection is performed, and “00111”, “10111” and “11110” are assigned to the case where redundant selection is performed.

  Then, five values obtained by inverting any one bit of the already-selected redundancy selection signal are further assigned to each redundancy setting. For example, five values “00001”, “00010”, “00100”, “01000”, and “10000” are assigned to “00000” corresponding to the case where no redundant selection is performed.

By decoding the redundancy setting based on the redundancy selection signal thus assigned and the 1-bit inverted data of the redundancy selection signal, the redundancy selection circuit 20 holds the redundancy setting in the redundancy setting latches 5 _{1 to} 5 _n. Even if a soft error has occurred in the redundant selection signal, if any one of the bits constituting the redundant selection signal is inverted, the redundant selection can be performed correctly. Can improve the soft error resistance.

Furthermore, redundant switch circuit 22, a redundant decoder circuit 21 is substituted for the defective memory cell group and the redundant memory cell group 10 ₄ based on the redundant set of decoding performs (redundancy selection).

  In the example shown in FIG. 2A, redundancy selection is shown when there is no defective memory cell group. In the figure, since the redundancy selection signal “00000” is set in the redundancy setting latch, it is determined by the redundancy decoding circuit 21 that no redundancy selection is made, but the redundancy selection signals are “00001”, “00010”, Even if it has changed to “00100”, “01000”, or “10000”, it is determined by the redundant decoding circuit 21 that redundant selection is not performed.

  In the example shown in FIG. 2B, a case where a failure occurs in the memory cell group 2 is shown. Thus, when a failure occurs in the memory cell group 2, it is necessary to replace the failed memory cell group 2 with a redundant cell group. In the figure, since the redundancy selection signal “11001” is set in the redundancy setting latch, it is determined that the memory cell group 2 and the redundancy memory cell group are exchanged, but the redundancy selection signal is “11000”, “11011”. ”,“ 11101 ”,“ 10001 ”, or“ 01001 ”, it is determined that the memory cell group 2 and the redundant memory cell group are exchanged.

As described above, even when the redundancy decoding circuit 21 receives the redundancy selection signal held in the redundancy setting latches 5 _{1 to} 5 _n and the input redundancy selection signal has changed from the originally set value, If only one bit is an inverted value, a soft error occurs in the redundancy setting latches 5 _{1 to} 5 _n by determining that it is the same as the redundancy setting indicated by the originally set redundancy selection signal. Thus, even when one bit of the redundancy selection signal is inverted, the redundancy selection can be performed correctly, so that the soft error resistance in the redundancy selection can be improved.

Assuming that the soft error rate per latch is ser (Soft Error), for example, in the redundant setting of the conventional memory cell of FIG. 12 described above, one 2-bit redundant selection signal is provided for one redundant setting. Since the soft error rate SERO ₁ in the redundant selection is
SERO ₁ = 1 − {(1-ser) ² }
It becomes.

On the other hand, in the redundant setting shown in FIG. 3, one redundant setting signal is assigned one 5-bit redundant selection signal and five values obtained by inverting one bit of the redundant selection signal. The soft error rate SERN ₁ at
SERN ₁ = 1 − {(1-ser) ⁵ + 5 × (1-ser) ⁴ × ser}
It becomes.

Therefore, when ser = 0.001, SERO ₁ = 0.002 and SERN ₁ = 9.98 × 10 ⁻⁶ , and the soft error resistance is increased by about 200 times compared to the conventional redundant selection of memory cells. Result.

  In this way, by increasing the number of bits of the redundancy selection signal held in the latch and assigning one redundancy selection signal and a plurality of 1-bit inverted data to one redundancy setting, resistance to soft errors in redundancy selection Can be improved.

  Although the case where 1-bit inverted data is assigned to each redundant setting has been described here, when a larger number of bits can be used for the redundant selection signal, data in which a plurality of bits are inverted can be further assigned. Is possible.

  Next, a method for generating a redundant selection signal according to the present embodiment will be described. FIG. 4 is a flowchart showing an algorithm for generating the redundant selection signal shown in FIG.

  As shown in FIG. 4, in this redundant selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary numerical value. Then, “0” is set as an initial value for all the bits of the data variable (step S101). For example, when the redundant selection signal is 5 bits, “00000” is set.

  Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S102). For example, when the redundant selection signal is “00000”, five types of 1-bit inverted data of “00001”, “00010”, “00100”, “01000”, and “10000” are created.

  Then, the data variable is assigned to the redundancy selection signal (step S103), and all the 1-bit inverted data of the data variable and the data variable cannot be used because the data variable is assigned to the redundancy selection signal. Register in the used list (step S104).

  Thereafter, 1 is added to the data variable to make it a new data variable (step S105), and 1-bit inverted data of the new data variable is created (step S106).

  Here, the new data variable and the 1-bit inverted data of the data variable are compared with the contents of the used list (step S107). If the used list already contains the data variable or data having the same value as the 1-bit inverted data of the data variable (Yes in step S108), the process returns to step S105 to set a new data variable. The processes after S106 are repeated.

  On the other hand, if the used list does not include the data variable and data having the same value as the 1-bit inverted data of the data variable (No in step S108), the data variable is assigned to the redundant selection signal (step S109). In addition, the data variable and 1-bit inverted data of the data variable are registered in the used list (step S110).

  Here, when the necessary number of redundant selection signals are assigned to the data variable (step S111, Yes), the process is terminated. When the necessary number is not satisfied (No at Step S111), the process returns to Step S105, a new data variable is set, and the processes after Step S106 are repeated.

  The redundancy selection signal generated by the above algorithm and 1-bit inverted data of each redundancy selection signal are assigned to the redundancy setting as shown in FIG.

  Here, for one redundancy setting, all redundancy obtained by inverting only one bit for one redundancy selection signal set in the latch and a plurality of bits constituting the redundancy selection signal. The case where 1-bit inverted data is assigned has been described.

  In this case, for example, in the case of seven redundant settings for replacing the memory cell groups 1 to 7 and the redundant memory cell group, 1 bit is obtained by inverting 1 bit in order to replace the memory cell groups 1 to 7 and the redundant memory group. Since the inverted data corresponds to each memory cell group, a redundant selection signal of at least 7 bits is required. However, even if only 4 bits can be secured for the redundancy selection signal due to circuit area restrictions, etc., one 4-bit redundancy selection signal and 1 of the 4 bits for the redundancy selection signal for each redundancy setting. Even if only one 1-bit inverted data with bits inverted is assigned, the soft error resistance is improved as compared with the case of decoding with only one redundant selection signal.

  FIG. 5 is a diagram illustrating a case where two redundant selection signals are assigned to one redundant setting. In the example shown in the figure, there are 8 redundancy settings, and a 4-bit redundancy selection signal is used, and for each redundancy setting, one redundancy selection signal and one 1-bit inversion of the redundancy selection signal. Data is allocated.

  In this way, by limiting the 1-bit inversion data to be assigned to each redundancy setting, even when the number of bits that can be used for the redundancy selection signal is limited due to restrictions on the circuit area, etc. Error tolerance can be improved.

  In the above description, a case has been described in which a redundancy selection signal is equally allocated to each redundancy setting indicating a memory cell replacement pattern. However, by assigning a larger number of redundancy selection signals to a specific pattern, the pattern is emphasized. In addition, the soft error resistance can be improved.

  FIG. 6 is a flowchart showing a redundancy selection signal generation algorithm in the case where a redundancy selection signal is assigned to a redundancy setting when no redundancy selection is performed as a specific redundancy setting.

  As shown in FIG. 6, in this redundant selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary numerical value. Then, “0” is set as an initial value for all the bits of the data variable (step S201). For example, when the redundant selection variable is 4 bits, “0000” is set.

  Then, 1-bit inverted data is generated by inverting only 1 bit of the data variable (step S202). For example, when the redundant selection signal is 4 bits, four types of inverted data “0001”, “0010”, “0100”, and “1000” are created.

  Then, the data variable is assigned to the redundancy selection signal (step S203), and all the data variable and the 1-bit inverted data of the data variable are registered in the used list (step S204).

  Thereafter, 1 is added to the data variable to make it a new data variable (step S205).

  Here, the data variable is compared with the used list (step S206). If the used list already contains data having the same value as the data variable (step S207, Yes), the process returns to step S205, a new data variable is set, and the processing after step S206 is repeated.

  On the other hand, if the used list does not include data having the same value as the data variable (No in step S207), the data variable is assigned to the redundant selection signal (step S208), and the data variable is used. Is registered in the completed list (step S209).

  Here, when a necessary number of redundant selection signals are assigned to the data variable (step S210, Yes), the process is terminated. If the required number is not satisfied (No at Step S210), the process returns to Step S205, a new data variable is set, and the processes after Step S206 are repeated.

FIG. 7 is a diagram illustrating an example in which a redundancy selection signal is assigned to a specific redundancy setting. In the example shown in the figure, a 4-bit redundancy selection signal is used, and a redundancy selection signal “0000” in which all bits are “0” and 1-bit inverted data “0001” of each bit for redundancy setting in which redundancy is not selected. , “0010”, “0100”, and “1000” are allotted to a total of five redundant selection signals, one for each of the seven redundant settings that replace the redundant memory cell groups with the other memory cell groups 1 to 7. Assign redundant selection signals one by one.
In the case of seven redundancy settings for replacing the memory cell groups 1 to 7 and the redundant memory cell group, it is necessary to replace the memory cell groups 1 to 7 and the redundant memory group, and one bit inversion is performed by inverting one bit. Since the data corresponds to each memory cell group, the redundancy selection signal generated by the above algorithm and the 1-bit inverted data of the redundancy selection signal whose all bits are “0” are used to indicate the replacement pattern of the memory cell. Assign settings.

  In this way, by allocating 1-bit inverted data mainly for a specific redundancy setting, for example, when there is no redundancy selection among a plurality of redundancy settings, a redundancy setting that is likely to be actually set is focused. In addition, it is possible to improve soft error tolerance in redundant selection.

  Further, in the redundancy selection signal generation method shown in FIG. 6, the case has been described in which a redundancy selection signal is assigned with a focus on a specific redundancy setting. In this method, for a specific redundancy setting, 1-bit inverted data is assigned so that the redundancy setting can be determined even when only 1 bit is inverted in the redundancy selection signal assigned to the redundancy setting. By assigning 2-bit inverted data, the redundancy setting may be determined even when 2 bits are inverted.

  FIG. 8 is a flowchart showing a redundancy selection signal generation algorithm in a case where 2-bit inverted data is further assigned to a specific redundancy setting.

  As shown in FIG. 8, in this redundant selection signal generation algorithm, first, a data variable having the same number of bits as the number of bits of the redundant signal to be generated is defined. This data variable is set to a binary numerical value. Then, “0” is set as an initial value for all bits of the data variable (step S301). For example, when the redundant selection variable is 4 bits, “0000” is set.

  Then, 1-bit inverted data obtained by inverting only 1 bit of the data variable and 2-bit inverted data obtained by inverting 2 bits are created (step S302). For example, when the redundant selection signal is 4 bits, four types of 1-bit inverted data “0001”, “0010”, “0100”, and “1000”, and “0011”, “0101”, “0110” , “1001”, “1010”, and “1100”, 6 types of 2-bit inverted data, a total of 10 types of inverted data are created.

  Then, the data variable is assigned to the redundancy selection signal (step S303), and the data variable and the 1-bit inverted data and 2-bit inverted data of the data variable are all registered in the used list (step S304).

  Thereafter, 1 is added to the data variable to make it a new data variable (step S305).

  Here, the new data variable is compared with the used list (step S306). If the used list already contains data having the same value as the data variable (Yes in step S307), the data variable is the maximum value (for example, “1111”) represented by a given number of bits. It is determined whether or not (step S311).

  If the data variable is equal to the maximum value (for example, “1111”) represented by the given number of bits (step S311, Yes), the data variable is in the used list until the necessary number is satisfied for the data variable. The 2-bit inverted data is assigned to the redundant selection signal (step S312). On the other hand, when the data variable is not the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated. If the used list does not include data having the same value as the data variable (No in step S307), the data variable is assigned to the redundant selection signal (step S308), and the data variable is used. Registered in the completed list (step S309).

  Here, when a necessary number of redundant selection signals are assigned to the data variable (step S310, Yes), the process is terminated. If the required number is not satisfied (No in step S310), it is determined whether or not the data variable is the maximum value represented by a given number of bits.

  If the data variable is the maximum value (step S311, Yes), the 2-bit inverted data in the used list is assigned to the redundant selection signal until the required number is satisfied (step S312). On the other hand, when the data variable is not the maximum value (step S311, No), the process returns to step S305, a new data variable is set, and the processing after step S306 is repeated.

  The redundancy setting is assigned using the redundancy selection signal generated by the above algorithm and the 1-bit inverted data and 2-bit inverted data of the redundancy selection signal having all bits of “0”. FIG. 9 is a diagram illustrating an example in which redundant selection signals remaining for a specific redundant setting are further allocated. In the example shown in the figure, a 4-bit redundancy selection signal is used, and a redundancy selection signal in which all bits are “0”, all 1-bit inversion data, and 2-bit inversion data for redundancy setting without redundancy selection. The redundant selection signal is assigned to each of the seven redundancy settings for replacing the memory cell groups 1 to 7 and the redundant memory cell group.

  Here, the case where 1-bit inverted data and 2-bit inverted data are assigned to a specific redundancy setting has been described. However, when a larger number of bits can be used for the redundancy selection signal, 3 bits or more are required. Inverted data may be further allocated.

  In this way, by assigning data in which a plurality of bits are inverted as much as possible according to the number of bits that can be used for the redundancy selection signal, soft error tolerance in redundancy selection can be further improved for a specific redundancy setting. it can.

  FIG. 10 is a diagram showing an example of a redundant decoding circuit with the redundant setting shown in FIG. The redundant decoding circuit of the example shown in the figure is composed of four inverter circuits, seven AND circuits, and six OR circuits. This redundant decode circuit outputs 7-bit redundant decode signals SEL0 to SEL6 in response to 4-bit redundant selection signals RED0 to RED3.

  By decoding the 4-bit redundancy selection signals RED0 to RED3, the output redundancy decode signals SEL0 to SEL6 are “0000000”, “1111111”, “1111110”, “1111100”, “1111000”, “111000”, There are eight types of “1100000” and “1000000”. Each of these redundant decode signals SEL0 to SEL6 corresponds to each of eight redundant settings. Based on these redundant decode signals SEL0 to SEL6, the redundant setting of the memory cell group is performed by the redundant switch circuit.

As described above, in this embodiment, the redundancy setting latches 5 _{1 to} 5 _n hold in advance the redundancy selection signal associated with the redundancy setting indicating the replacement pattern of the memory cell group, and the redundancy selection circuit 21 Even if a part of the redundancy selection signal is inverted by inputting this redundancy selection signal, the same redundancy setting as that associated with the redundancy selection signal before inversion is derived, and the redundancy switch circuit 22 Since the memory cell group is replaced based on the derived redundancy setting, a soft error occurs in the redundancy selection signal held in the redundancy setting latches 5 _{1 to} 5 _n due to the influence of radiation from the universe. Even in such a case, since the redundancy selection can be performed correctly, the soft error resistance in the redundancy selection can be improved.

(Supplementary note 1) A memory redundancy selection device that is connected to a memory cell and a redundancy memory cell constituting a storage device and performs redundancy selection for selecting an input / output of either the memory cell or the redundancy memory cell,
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundancy selection signal held in the redundancy selection information holding means and outputs the same redundancy setting as the decoding result even when a part of the redundancy selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A memory redundancy selection device comprising:

(Supplementary note 2) The memory redundancy selection device according to supplementary note 1, wherein the redundancy selection signal holding means comprises a scan latch means.

(Supplementary Note 3) The memory redundancy according to Supplementary Note 1, wherein the redundant decoding means is configured to associate at least two or more redundant selection signals as inputs for the same redundant setting output as a decoding result. Selection device.

(Supplementary Note 4) The redundant selection signal is composed of n bits (n> 1),
The redundancy decoding means outputs the same redundancy setting as the decoding result even when k bits (0 <k ≦ n−1) of the n bits constituting the redundancy selection signal are inverted. The memory redundancy selection device according to appendix 1, wherein the memory redundancy selection device is performed.

(Appendix 5) Memory cell;
Redundant memory cells;
Redundant selection means connected to the memory cell and the redundant memory cell and performing redundant selection for selecting input / output of either the memory cell or the redundant memory cell;
The redundancy selecting means includes
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundancy selection signal held in the redundancy selection information holding means and outputs the same redundancy setting as the decoding result even when a part of the redundancy selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A storage device comprising:

(Appendix 6) Memory cell;
Redundant memory cells;
An arithmetic processing unit connected to the storage device;
Redundancy selection means connected to the memory cell and the redundant memory cell and performing redundancy selection for selecting input / output of either the memory cell or the redundant memory cell;
The redundancy selecting means includes
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundant selection signal held in the redundant selection information holding means and outputs the same redundant setting as a decoding result even when part of the redundant selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
An information processing apparatus comprising:

(Appendix 7) The information processing apparatus further includes TAP controller means for performing scan shift control;
A scan latch means that performs a scan shift by a scan clock output from the TAP controller means, and includes the redundancy selection signal holding means;
A fuse means connected to the scan latch means for setting a redundancy selection signal;
The redundant selection signal set in the fuse means is output to the scan latch means, and the redundant selection signal is held in the redundant selection signal holding means by performing the scan shift. Information processing device.

(Supplementary Note 8) The information processing apparatus further includes TAP controller means for performing scan shift control;
A scan latch means that performs a scan shift by a scan clock output from the TAP controller means, and includes the redundancy selection signal holding means;
A scan input connected to the scan latch means;
7. The information processing apparatus according to claim 6, wherein the redundancy selection signal is input to the redundancy selection signal holding unit by inputting the redundancy selection signal from the scan input and performing the scan shift.

(Supplementary note 9) A memory cell redundant selection method for selecting input / output of a memory cell or a redundant memory cell constituting a storage device,
Holding a redundant selection signal indicating selection information of the memory cell;
Inputting the held redundancy selection signal, and outputting the same redundancy setting as the decoding result as before the inversion even when a part of the redundancy selection signal is inverted;
Selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A method for redundant selection of memory cells, comprising:

(Supplementary Note 10) In the step of inputting the retained redundancy selection signal and outputting the same redundancy setting as the decoding result even when a part of the redundancy selection signal is inverted, as a decoding result,
The method for redundant selection of memory cells according to appendix 9, wherein at least two redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.

(Supplementary note 11) A memory redundancy selection device for performing redundancy selection in which a defective memory cell is replaced with a redundancy memory cell in a semiconductor memory device,
A redundancy selection signal holding means for holding in advance a redundancy selection signal associated with a redundancy setting indicating a replacement pattern of a memory cell;
Redundancy decoding means for deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal;
Redundant switch means for replacing a memory cell based on the redundancy setting derived by the redundant decoding means;
A memory redundancy selection device comprising:

(Supplementary note 12) The redundant selection signal is composed of n bits (n> 1),
The redundant decoding means is associated with the redundant selection signal before inversion even when n-k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. The memory redundancy selection device according to appendix 11, wherein a redundancy setting that is the same as the redundancy setting is derived.

(Additional remark 13) The redundant decoding means, even if n-k bits (0 <k ≦ n−1) are inverted with respect to a predetermined bit among n bits constituting the redundant selection signal, 13. The memory redundancy selection device according to appendix 12, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal is derived.

(Supplementary Note 14) The redundant decoding means inverts a specific redundancy setting even if n-k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 14. The memory redundancy selection device according to appendix 12 or 13, wherein the same redundancy setting as the redundancy setting associated with the previous redundancy selection signal is derived.

(Supplementary Note 15) The redundancy decoding means inverts up to n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal for redundancy setting in which memory cells are not replaced. 15. The memory redundancy selection device according to appendix 14, wherein the redundancy setting that is the same as the redundancy setting associated with the redundancy selection signal before inversion is derived.

(Supplementary Note 16) The redundancy decoding means has the same redundancy as the redundancy setting associated with the redundancy selection signal before inversion even when one of the n bits constituting the redundancy selection signal is inverted. The memory redundancy selection device according to attachment 12, wherein the setting is derived.

(Supplementary Note 17) The redundant decoding means is associated with a redundant selection signal before inversion even if any one of n bits constituting the redundancy selection signal is inverted for a specific redundancy setting. 15. The memory redundancy selection device according to appendix 14, wherein the same redundancy setting as the redundant setting is derived.

(Supplementary Note 18) The redundancy decoding means performs redundancy selection before inversion even if one of the n bits constituting the redundancy selection signal is inverted for redundancy setting in which memory cells are not replaced. 18. The memory redundancy selection device according to appendix 17, wherein the same redundancy setting as the redundancy setting associated with the signal is derived.

(Supplementary note 19) The memory redundancy selection device according to any one of supplementary notes 11 to 18, wherein the redundancy selection signal holding means holds the redundancy selection signal in a latch mounted in the semiconductor memory device. .

(Supplementary note 20) The memory redundancy selection device according to supplementary note 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by a signal generated by cutting a fuse.

(Supplementary note 21) The memory redundancy selection device according to supplementary note 19, wherein the redundancy selection signal holding means sets a redundancy selection signal held in the latch by a signal inputted from the outside.

(Supplementary note 22) A memory redundancy selection method for performing redundancy selection in which a defective memory cell is replaced with a redundant memory cell in a semiconductor memory device,
A redundancy selection signal holding step for holding in advance a redundancy selection signal associated with a redundancy setting indicating a replacement pattern of a memory cell;
A redundancy decoding step for deriving the same redundancy setting as before the change even when a part of the redundancy selection signal is changed by inputting the redundancy selection signal;
A redundancy switch step for replacing a memory cell based on the redundancy setting derived by the redundancy decoding step;
A method for redundant selection of memory cells, comprising:

(Supplementary Note 23) The redundant selection signal is composed of n bits (n> 1),
The redundant decoding step is associated with the redundant selection signal before inversion even when n-k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted. 23. The method for redundant selection of memory cells according to appendix 22, wherein the same redundancy setting as the redundancy setting is derived.

(Supplementary Note 24) In the redundant decoding step, even if n-k bits (0 <k ≦ n−1) are inverted with respect to a predetermined bit among n bits constituting the redundant selection signal, 24. The method for redundant selection of memory cells according to appendix 23, wherein the same redundancy setting as the redundancy setting associated with the redundancy selection signal is derived.

(Supplementary Note 25) The redundancy decoding step is reversed even when n-k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are reversed for a specific redundancy setting. 25. The method for redundant selection of memory cells according to appendix 23 or 24, wherein the same redundancy setting as the redundancy setting associated with the previous redundancy selection signal is derived.

(Supplementary Note 26) In the redundancy decoding step, up to n−k bits (0 <k ≦ n−1) of n bits constituting the redundancy selection signal are inverted with respect to the redundancy setting in which the memory cell is not replaced. 26. The method of redundant selection of memory cells according to appendix 25, wherein the same redundancy setting as the redundancy setting associated with the redundancy selection signal before inversion is derived even in the case of inversion.

(Supplementary Note 27) In the redundant decoding step, even if any one of the n bits constituting the redundant selection signal is inverted, the redundancy is the same as the redundancy setting associated with the redundant selection signal before being inverted. 24. The method for redundant selection of memory cells according to appendix 23, wherein the setting is derived.

(Supplementary Note 28) The redundant decoding step is associated with a redundant selection signal before being inverted even when one of the n bits constituting the redundant selection signal is inverted for a specific redundancy setting. 26. The method for redundant selection of memory cells according to appendix 25, wherein the same redundancy setting as the redundant setting is derived.

(Supplementary Note 29) In the redundancy decoding step, for redundancy setting in which memory cells are not replaced, redundancy selection before inversion is performed even if one of n bits constituting the redundancy selection signal is inverted. 29. The method of redundant selection of memory cells according to appendix 28, wherein the same redundancy setting as the redundancy setting associated with the signal is derived.

(Supplementary note 30) The redundancy of the memory cell according to any one of supplementary notes 22 to 29, wherein the redundancy selection signal holding step holds the redundancy selection signal in a latch mounted in the semiconductor memory device. Selection method.

  As described above, the redundancy selection device and the redundancy selection method according to the present invention are useful for semiconductor memory devices that perform redundancy selection in which defective memory cells are replaced with redundancy memory cells, and in particular, control redundancy selection such as redundancy selection signals. It is suitable for a processor incorporating a semiconductor device that holds data to be stored for a long period of time, a DSP (Digital Signal Processor), an LSI such as an SOC (System On Chip).

It is explanatory drawing for demonstrating the outline | summary of the redundant selection which concerns on a present Example. It is a block diagram which shows the structure of the RAM macro which concerns on a present Example. It is a figure which shows an example of the redundant setting which concerns on a present Example. FIG. 4 is a flowchart showing an algorithm for generating a redundancy selection signal shown in FIG. 3. FIG. It is a figure which shows an example in the case of assigning two redundant selection signals to one redundant setting. It is a flowchart which shows the redundancy selection signal generation algorithm in the case of assigning a redundancy selection signal focusing on a specific redundancy setting. It is a figure which shows an example in the case of assigning a redundancy selection signal focusing on a specific redundancy setting. It is a flowchart which shows the redundancy selection signal generation algorithm in the case of assigning 2-digit inversion data further to a specific redundancy setting. It is a figure which shows an example in the case of further assigning the redundant selection signal surplus for a specific redundancy setting. It is a figure which shows an example of the redundant decoding circuit by the redundant setting shown in FIG. It is a figure which shows an example of the redundancy selection of the conventional memory cell. It is a figure which shows an example of the redundancy selection signal in the redundancy selection of the conventional memory cell. It is a figure which shows an example of the conventional redundancy selection circuit. 14 is a list of signals generated by the redundant switch circuit and the redundant decode circuit shown in FIG. 13.

Explanation of symbols

1 LSI chip 2 _{1 to} 2 ₅ fuse 3 _{1 to} 3 _m latch row 4 ₁ to 4 _n RAM macro 5 _{1 to} 5 _n redundancy setting latch 6 processor core section 7 TAP controller 10 ₁ to 10 ₃ memory cell group 10 ₄ redundant memory Cell group 20 Redundant selection circuit 21 Redundant decoding circuit 22 Redundant switch circuit

Claims (10)

A memory redundancy selection device which is connected to a memory cell and a redundancy memory cell constituting a storage device and performs redundancy selection for selecting an input / output of either the memory cell or the redundancy memory cell,
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundant selection signal held in the redundant selection information holding means and outputs the same redundant setting as a decoding result even when part of the redundant selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A memory redundancy selection device comprising:   2. The memory redundancy selection device according to claim 1, wherein the redundancy selection signal holding means is constituted by a scan latch means.   2. The memory redundancy selection device according to claim 1, wherein the redundancy decoding means is configured to associate at least two or more redundancy selection signals as inputs for the same redundancy setting output as a decoding result. The redundant selection signal is composed of n bits (n> 1),
The redundancy decoding means outputs the same redundancy setting as the decoding result even when k bits (0 <k ≦ n−1) of the n bits constituting the redundancy selection signal are inverted. The memory redundancy selection device according to claim 1, wherein the memory redundancy selection device is performed. A memory cell;
Redundant memory cells;
Redundancy selection means connected to the memory cell and the redundant memory cell and performing redundancy selection for selecting input / output of either the memory cell or the redundant memory cell;
The redundancy selecting means includes
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundant selection signal held in the redundant selection information holding means and outputs the same redundant setting as a decoding result even when part of the redundant selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A storage device comprising: A memory cell;
Redundant memory cells;
An arithmetic processing unit connected to the storage device;
Redundancy selection means connected to the memory cell and the redundant memory cell and performing redundancy selection for selecting input / output of either the memory cell or the redundant memory cell;
The redundancy selecting means includes
Redundant selection signal holding means for holding a redundant selection signal indicating selection information of the memory cell;
Redundant decoding that inputs the redundancy selection signal held in the redundancy selection information holding means and outputs the same redundancy setting as the decoding result even when a part of the redundancy selection signal is inverted Means,
Redundant switch means for selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
An information processing apparatus comprising: The information processing apparatus further includes TAP controller means for performing scan shift control;
A scan latch means that performs a scan shift by a scan clock output from the TAP controller means, and includes the redundancy selection signal holding means;
A fuse means connected to the scan latch means for setting a redundancy selection signal;
7. The redundancy selection signal set in the fuse means is output to the scan latch means, and the scan selection is performed to hold the redundancy selection signal in the redundancy selection signal holding means. Information processing device. The information processing apparatus further includes TAP controller means for performing scan shift control;
A scan latch means that performs a scan shift by a scan clock output from the TAP controller means, and includes the redundancy selection signal holding means;
A scan input connected to the scan latch means;
7. The information processing apparatus according to claim 6, wherein the redundancy selection signal is held in the redundancy selection signal holding unit by inputting the redundancy selection signal from the scan input and performing the scan shift. A memory cell redundancy selection method for selecting input / output of a memory cell or a redundant memory cell constituting a memory device,
Holding a redundant selection signal indicating selection information of the memory cell;
Inputting the held redundancy selection signal, and outputting the same redundancy setting as the decoding result as before the inversion even when a part of the redundancy selection signal is inverted;
Selecting input / output of either the memory cell or the redundant memory cell based on the decoding result;
A method for redundant selection of memory cells, comprising: In the step of inputting the held redundancy selection signal and outputting the same redundancy setting as the decoding result as before the inversion even when a part of the redundancy selection signal is inverted,
10. The method for redundant selection of memory cells according to claim 9, wherein at least two redundant selection signals are associated as inputs for the same redundant setting output as a decoding result.

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