JPH05206410A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enhance the reliability of the subject memory device by means of a simple structure by a method wherein a floating gate is formed in such a way that one part of it is overlapped with a control gate via a thin insulating film. CONSTITUTION:As the defect relief circuit of a memory circuit in which read- only memory elements are arranged in a matrix shape, a nonvolatile memory element QE which includes the following is used: a control gate 6 formed of a diffusion layer; a floating gate 8 which is formed in such a way that one part of it is overlapped with the control gate 6 via a thin insulating film 13 and which is composed of a conductor layer; and a barrier layer which is formed so as to cover one part or the whole of the floating gate 8 and which is composed of an aluminum layer. A defective address corresponding to a word line and a bit line is stored, and a piece of data corresponding to them is stored. Thereby, radical hydrogen which is diffused from a final passivation film in an element surface part is captured by the barrier layer, and it is possible to prevent an information charge from being destroyed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, it is used for a defect repair technique of a mask type ROM (read only memory) using a nonvolatile memory element having a single-layer polysilicon gate structure. It relates to effective technology.

[0002]

2. Description of the Related Art EPROM (Erasable & Electrical
A technique using a read only memory) is known. A technique using a single-layer polysilicon gate structure as the EPROM is described in, for example, "Technical Research Report of Institute of Electronics, Information and Communication Engineers" Vol.
o.47, page 51 to page 53.

[0003]

The inventor of the present application has found that the following phenomenon occurs when the data retention characteristic of the EPROM is analyzed. FIG.
Shows the data retention characteristics of EPROMs having different structures. The horizontal axis represents time, and the vertical axis represents the fluctuation rate of the threshold voltage [ΔVth _t ÷ ΔVth ₀ × 100]%. Here, ΔVth ₀ indicates the threshold voltage at the time of writing, and ΔVth _t indicates the threshold voltage after t time has elapsed. Further, the data retention characteristics were examined in an environment of leaving it in the air at a temperature of 300 ° C.

In FIG. 16, an element structure having a characteristic B is an EPROM having a single-layer polysilicon gate structure, and a characteristic D is an EPROM having a two-layer gate structure. The inventor of the present application does not prevent the reduction of the information charges accumulated in the floating gate by the control gate in the two-layer gate structure acting as a barrier layer because of the difference in the data retention characteristics of the two EPROMs. I guessed that. In order to confirm this, EPRO having a single-layer polysilicon gate structure in which an aluminum layer is provided on the entire upper surface of the floating gate made of the single-layer polysilicon.
When M was formed and the data retention characteristics thereof were examined, a significant improvement in the data retention characteristics like the characteristic A was recognized. Also,
It has been found that when the oxide film (P-SiO) formed by the plasma-CVD method is provided on the top of the device in the two-layer gate structure, good data retention characteristics such as the characteristic C can be obtained. The oxide film (P-SiO) is formed as an interlayer insulating film for the two-layer aluminum wiring. That is, the first aluminum layer is BPSG
(Boron-doped Phospho-Silicate Glass) is formed on the film, and a second layer is formed on the film through the oxide film (P-SiO).
This is an EPROM having a two-layer gate structure having a structure in which a third aluminum layer is formed.

From the result of careful analysis of the relationship between the device structure and the data retention characteristic as described above, the inventors of the present invention can obtain a non-volatile memory element having a single-layer gate structure with an improved data retention characteristic. Attention was paid to (1), and it was considered to utilize it for defect relief of the mask type ROM.

An object of the present invention is to provide a semiconductor memory device having a highly reliable defect relief circuit with a simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, as a defect relief circuit of a memory circuit in which read-only memory elements are arranged in a matrix, a control gate formed of a diffusion layer,
A floating gate formed of a conductor layer formed so as to partially overlap the control gate via a thin insulating film, and a barrier layer formed so as to cover a part or the entire surface of the floating gate. A non-volatile memory element including and is used to store a defective address corresponding to a word line and a bit line and to store data corresponding to each.

[0008]

According to the above means, the radical hydrogen, which is presumed to be diffused from the final passivation film on the surface of the device, is trapped by the barrier layer, so that the destruction of the information charge accumulated in the floating gate can be prevented. Therefore, the defect relief with high reliability can be realized by using the nonvolatile memory element having a simple structure.

[0009]

1 (A) to 1 (C) are sectional views of a manufacturing process for explaining a nonvolatile memory element used in the present invention. In these drawings, an N-channel MOSFET and a P-channel MOSFET that are formed at the same time as the nonvolatile memory element are shown together. In this specification, MOSFET is used to mean an insulated gate field effect transistor (IGFET).

In FIGS. 1A to 1C, a nonvolatile memory element Q having a one-layer polysilicon gate structure from the bottom is shown.
E, N channel MOSFET QN, P channel MO
The SFET QP is shown. N channel MOSFE
The TQN and the P-channel MOSFET QP are peripheral circuits such as the address selection circuit of the nonvolatile memory element QE,
It is used to configure other memory circuits formed on the same semiconductor substrate as the EPROM according to the present invention and peripheral circuits such as address selection circuits thereof. The nonvolatile memory element QE has a lower side perpendicular to the source and drain,
The upper side shows a cross-sectional view in the parallel direction.

In FIG. 1A, a P-type well 2 and an N-type well 102 are formed on one main surface of a P-type semiconductor substrate 1 by a known means. The field insulating film 3 having a large thickness is formed by a known means, and the P shown by a dotted line in the figure is formed below the field insulating film 3.
A channel type stopper 4 is formed. An N-type diffusion layer 6 to be the control gate of the non-volatile memory element QE is formed. The N-type diffusion layer 6 is not particularly limited, but after phosphorus is implanted at about 1 × 10 ¹⁴ cm ^-2 with an acceleration energy of 80 Kev through the insulating film by an ion implantation method, about 1% oxygen is added to nitrogen. 950 ℃ in an atmosphere
It is formed by performing heat treatment at the temperature of about 30 minutes. Of course, the impurities may be arsenic alone or both arsenic and phosphorus. Further, basically, it is not necessary to perform the heat treatment, but it is better to perform the heat treatment in order to recover the damage of the semiconductor substrate 1 damaged by the ion implantation.

Next, after the insulating film damaged by the ion implantation is removed, a clean gate insulating film 7 is formed by a thermal oxidation method. At this time, the N-type diffusion layer 6
The film thickness of the gate insulating film 7 on the upper part is about 10 to 20% thicker than the region without the N-type diffusion layer 6. The floating gate of the nonvolatile memory element QE, N
Channel MOSFET QN and P channel MOSFE
A conductor layer 8 to be the gate electrode of TQP is formed. The conductor layer 8 is composed of a polycrystalline silicon (polysilicon) film or a polycide film in which a silicide film is laminated on the polycrystalline silicon film.

As shown in FIG. 1B, N type diffusion layers 9 and 10 and a P type diffusion layer 109 are formed. The N-type diffusion layer 9 has an acceleration energy of 50 Kev due to the ion implantation method.
^Is formed by implanting about 2 × 10 ¹³ cm ^-2 . The N-type diffusion layer 10 is formed by ion implantation with phosphorus being implanted at an acceleration energy of 50 Kev at about 5 × 10 ¹⁵ cm ^-2 . The P-type diffusion layer 109 is 1 × 1 in boron with an acceleration energy of 15 Kev by an ion implantation method.
It is formed by implanting about 0 ¹³ cm ^-2 . next,
After the CVD insulating film is formed on the entire surface, the sidewalls 11 are formed by anisotropic etching. And N
The type diffusion layer 12 and the P type diffusion layer 112 are formed. The N-type diffusion layer 12 is formed by implanting arsenic at an acceleration energy of 80 Kev at about 5 × 10 ¹⁵ cm ⁻² by an ion implantation method. The P-type diffusion layer 112 is formed by the ion implantation method.
Boron is formed by implanting about 2 × 10 ¹⁵ cm ^-2 with an acceleration energy of ¹⁵ Kev. In this embodiment, the N-type diffusion layer 10 has been described as being formed before forming the sidewalls 11, but it may be formed after forming the sidewalls 11. In addition, the P-type diffusion layer 1
The manufacturing process of 09 may be omitted, and the P-type diffusion layer 112 may be formed before the formation of the sidewall 11. In this case, the N-type diffusion layer 9 can be formed by ion-implanting the entire surface without using the mask.

In FIG. 1C, the nonvolatile memory element Q
E is a one-layer gate in which the control gate is composed of the diffusion layers 6 and 10, the floating gate 8, the gate insulating film 7, the interlayer insulating film 7 between the control gate and the floating gate, and the source and the drain are composed of the N type diffusion layer 10. Structured. The source and the drain are formed by the N-type diffusion layer 10 in order to improve the writing characteristics. The N-type diffusion layer 10 has the same structure as the source and the drain of the N-channel MOSFET QN that constitutes the input / output. The N-channel MOSFET QN has a gate electrode 8,
Gate insulating film 7 and N-type diffusion layer 9 for source and drain
And a so-called LDD structure composed of 12 and. The P-channel MOSFET QP has a gate electrode 8,
The gate insulating film 7 and the source and drain are P-type diffusion layers 1
A so-called LDD structure composed of 09 and 112 is formed. Each element is separated by a field insulating film 3 and a P channel type stopper 4. Each element is connected by a wiring 15 made of aluminum through a contact hole formed in the insulating film 13.
The N-type diffusion layers 6 and 10 which are the control gates of the nonvolatile element QE are shunted by the wiring 15 to reduce the parasitic resistance. That is, the wiring 15 constitutes a word line and is connected to the control gate of each nonvolatile memory element. The N-type diffusion layer 10 is provided to make good ohmic contact with the wiring 15.

In this embodiment, in order to improve the data retention characteristics of the nonvolatile memory element QE having such a single-layer gate structure, the aluminum layer 15 covering the entire surface of the floating gate 8 with the insulating film 13 interposed therebetween serves as a barrier. Formed as a layer. The insulating film 13 is composed of a PSG film or a BPSG film. The insulating film 1 is not particularly limited.
The aluminum layer 15 as a barrier layer formed so as to cover the entire surface of the floating gate via 3 is integrally formed with a word line to which the control gate of the nonvolatile memory element QE is connected. The non-volatile memory element QE of this embodiment is used for defect relief of a mask ROM as described later, and the N-channel MOSFET QN
Has a structure similar to that of the memory element. However, Fig. 1 (A)
In the above, in the portion where the mask ROM is formed, N-type impurities are introduced by the ion implantation method, and the N-channel MOSFET formed there is placed in the depletion type.

FIG. 2 shows an element pattern diagram of one embodiment of the nonvolatile memory element QE. The N-type diffusion layer 6 which is the control gate is provided with an aluminum layer 15 shown by a dotted line in the figure through the contact hole 14.
Connected to the word line WL. Since the aluminum layer 15 is also used as a barrier layer of the floating gate 8, it extends rightward along the floating gate 8 so as to cover the entire surface of the floating gate 8 hatched by broken lines in the figure. Is formed as. In the figure, two memory cells are shown symmetrically with respect to the one-dot chain line ab. That is,
The drain of the upper nonvolatile memory element QE is connected to the aluminum layer 15 via the contact hole 14. This aluminum layer 15 is a contact hole 1
4 is connected to the data line DL formed of a polysilicon layer extending in the left-right direction. The N-type diffusion layer 10 that constitutes the source of the non-volatile memory element QE is integrally formed with the source of the lower non-volatile memory element QE, and the aluminum layer 15 and the drain that constitute the barrier layer are formed of poly-silicon. It extends rightward along the center line ab to a region which does not intersect with the aluminum layer connected to the word line made of a silicon layer, and extends vertically through the contact hole 14 formed therein, in other words, the word. It is connected to a source line SL made of an aluminum layer extending parallel to the line.

The non-volatile memory element QE having a single-layer (or one-layer) gate structure of this embodiment is provided with a barrier layer formed of an aluminum layer so as to cover the entire upper surface of the floating gate. In this embodiment, in order to prevent injection into the floating gate due to diffusion of radical hydrogen as described later, the floating gate 8
It is considered to be a large-sized barrier layer with a margin to exceed the size of.

From the data holding characteristics shown in FIG. 16,
The following is presumed. The characteristic D shows an improvement in the data retention characteristic as compared with the characteristic B. The structural difference between the two is that the characteristic B is a single-layer gate structure, while the characteristic D is a double-layer gate structure. From this, the inventor of the present application presumed that the control gate in the two-layer gate structure might have a function of preventing the factor that invades the floating gate and causes the retained charge to disappear. In order to confirm this, an element having an aluminum layer as shown in FIG. 1C or FIG. 3 as a barrier layer was formed on the floating gate in the single-layer gate structure.
Further, as shown in the characteristic A, the data retention characteristic is significantly improved.

It was speculated that one of the factors causing the loss of the information charges accumulated in the floating gate was radical hydrogen from the final passivation film.
The reason is as follows. That is, although omitted in FIG. 16, when a plasma nitride (P-SiN) film is used as the final passivation film,
It was confirmed that the data retention characteristics were worse than when using the CVD oxide (PSG) film. The difference between the two is a large difference in the amount of radical hydrogen. Then, it was concluded that the aluminum layer as a barrier layer itself acts as a dam containing a large amount of hydrogen and stopping radical hydrogen, and prevents diffusion of hydrogen to the floating gate.

The barrier layer may be a polysilicon layer. The polysilicon layer also has a property of easily containing hydrogen, and when it is used as a floating gate, it traps hydrogen diffused from the final passivation film and loses information charges. By utilizing this in reverse, a polysilicon layer is provided as a barrier layer on the floating gate. The polysilicon layer as the barrier layer first captures and takes in radical hydrogen diffused from the final passivation film, and acts to prevent the diffusion to the floating gate provided below the radical hydrogen. As a result, as in the case of the aluminum layer, the polysilicon layer serving as the barrier layer plays a so-called dam role for radical hydrogen, and prevents the entry into the floating gate.

The above phenomenon is only speculation,
As is clear from the data retention characteristics shown in FIG. 16, by providing the barrier layer as described above, the data retention characteristics of the nonvolatile memory element having the single-layer gate structure can be clearly improved. When plasma nitride (P-SiN) is used as the final passivation film, an inexpensive plastic package can be used. Therefore, by providing the barrier layer as in this embodiment, a semiconductor integrated circuit device using an inexpensive package can be obtained while improving the data retention characteristics.

In the characteristic diagram of FIG. 16, a characteristic C is a non-volatile memory element having a two-layer gate structure, and in order to form a two-layer aluminum wiring, a first-layer aluminum layer and a second-layer aluminum layer are used. An oxide film (P-SiO) formed by a plasma-CVD method is arranged as an interlayer insulating film provided between the two. Further, even with the same two-layer gate structure, it is possible to obtain much better data retention characteristics than the characteristics D of the nonvolatile memory element having no oxide film (P-SiO). It has been found that the oxide film (P-SiO) itself also has a function of preventing the diffusion of the radical hydrogen. Oxide film (P-Si
O) is monosilane (SiH ₄ ) + nitric oxide (N ₂ O)
It is assumed that the raw material gas is introduced into the plasma reaction chamber to be attached, and the amount of radical hydrogen itself is small, and it has an action of absorbing diffused radical hydrogen.

From this, the first interlayer insulating film 13 of FIG. 1C is formed of a PSG film or a BPSG film,
Although not shown, the second interlayer insulating film formed thereon is formed of the oxide film (P-SiO), and a plasma nitride film (P-P) is used as a final passivation film.
-SiN) may be used.

FIG. 4 shows a mask type ROM according to the present invention.
A block diagram of one embodiment of is shown. This mask type ROM is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technique of the semiconductor integrated circuit as shown in FIG. In the same figure, in order to facilitate understanding, the notation method of the logical symbols follows the general notation method. For example, a signal whose low level becomes an active level is overlined with an alpha bed indicating a control signal, but in the specification, the corresponding signal is represented by adding B (meaning a bar) at the end. For example, the chip enable signal is represented as CEB. This is
The same applies to the control signals of other drawings and the description of the specification corresponding thereto.

The memory mat MR-MAT is a mask type R.
The memory elements for OM are arranged in a matrix. The memory mat PR-MAT has a configuration in which the non-volatile storage elements having the single-layer gate structure as described above are arranged in a matrix, and has a defective word line and a defective bit line (or a defective data line or defective) in the memory mat MR-MAT. It may also be called a digit line) and is used for relieving defective data.

In the memory mat MR-MAT, a memory element is arranged at each intersection of a word line and a data line similarly to a known mask ROM, and the gate of the memory element is a word line, the drain is a data line, and the source is a source. Each is connected to the ground wire of the circuit. The word line of the memory mat MR-MAT is selected by the X decoder circuit MR-XDC.
The X decoder circuit MR-XDC has an X-system address signal A.
_{i + 1} to A _n decodes the internal address signals complementary formed by the address buffer ADB undergoing performs an operation for selecting one word line from a plurality of word lines of the memory mat MR-MAT.

The data line of the memory mat MR-MAT is connected to the common data line by the column switch gate MR-YGT. Column switch gate MR-YG
In the memory mat MR-MAT, T is in accordance with a decode signal formed by a Y decoder circuit YDC which decodes a complementary internal address signal formed by an address buffer ADB which receives Y system address signals A _{0 to} A _i . Then, the operation of connecting one data line to the common data line for each output mat is performed. The common data line is connected to the input terminal of the sense amplifier circuit MR-SAM.
The sense amplifier circuit MR-SAM amplifies the stored information read from the memory element at the intersection of the selected word line and data line.

The memory mat PR-MAT has the above-mentioned non-volatile memory element having a single-layer gate structure arranged at each intersection of a word line and a data line.
Used as a redundant circuit for defective data corresponding to a defective word line in MAT. The control gate of the nonvolatile memory element is connected to the word line, the drain is connected to the data line, and the source is connected to the ground line of the circuit. A redundant word line selection signal formed by a relief address storage circuit PR-ADD described later is supplied to the word line of the redundant memory mat PR-MAT.

The data line of the redundant memory mat PR-MAT is connected to the write data input circuit PR-PGC and the column switch gate PR-YGT. The write data input circuit PR-PGC has a Y-system address signal A.
Write data input D and complementary internal address signal formed by address buffer ADB receiving _{0 to} A _i
An operation of transmitting a write signal to one data line in the redundant memory mat PR-MAT is performed by the data signal formed by the input buffer DIB receiving I. The column switch gate PR-YGT is provided with a redundant memory mat according to an output signal of a Y decoder PR-YDC which decodes a complementary internal address signal formed by an address buffer ADB which receives the Y-system address signals A _{0 to} A _i. P
The operation of connecting one data line to the common data line is performed for each output mat of the R-MAT.

The common data line is the sense amplifier circuit PR.
-Connected to the input terminal of the SAM. Sense amplifier circuit P
The R-SAM amplifies stored information read from the memory cell (nonvolatile storage element) at the intersection of the selected word line and data line in the read mode. The output signal of the sense amplifier circuit PR-SAM is input to the multiplexer circuit MPX that switches the sense amplifier. This multiplexer circuit MPX has a sense amplifier circuit M for mask ROM when a word line is defective.
Redundant memory mat P in place of the output signal of R-SAM
The output signal of the R-MAT sense amplifier circuit PR-SAM is selected and transmitted to the output buffer DOB. The output buffer DOB outputs the read data transmitted through the multiplexer circuit MPX from the output terminals DO _{0 to} DO _m .

In this embodiment, a redundant circuit is provided even for a defective bit line. The redundant circuit PR-DAS corresponding to a defective bit line is a memory mat PR-BMAT in which the above-mentioned nonvolatile memory element having a single-layer gate structure is arranged at each intersection of a word line and a data line, and a gate circuit. It is composed of a PR-BYGT and a sense amplifier PR-BSAM. Each of these circuits PR-BMAT,
PR-BYGT and PR-BSAM are the circuits P described above.
The R-MAT, PR-YGT, and PR-SAM have the same configuration, and the mutual connections are also similar. Memory mat PR-B of this redundant circuit PR-DAS
Similar to the above, the MAT is constructed by connecting the control gate of the nonvolatile memory element to the word line, connecting the drain to the data line, and connecting the source to the ground line of the circuit. In the redundant memory mat PR-MAT in the redundant circuit corresponding to the defective word line, the word line corresponds to the word line of the memory mat MR-MAT, but the redundant memory mat P in this redundant circuit PR-DAS.
The word line of R-BMAT is a memory mat MR-MAT.
It corresponds to the bit line of. That is, by selecting the word line of the redundant memory mat PR-BMAT, it is possible to select a plurality of data corresponding to the defective bit line, and which of the redundant bits is selected depends on the X-system address signal. Determined by Therefore, the redundant circuit PR-DA
In S, the output signal of the X-system address decoder circuit PR-XDC is supplied to the gate circuit PR-BYGT.

The output signal of the sense amplifier circuit PR-BSAM of the redundant circuit PR-DAS is input to the multiplexer circuit MPX for switching the sense amplifier. When the bit line is defective, the multiplexer circuit MPX selects the output signal of the sense amplifier circuit PR-BSAM of the redundant circuit PR-DAS instead of the output signal of the sense amplifier circuit MR-SAM for the mask ROM. To the output buffer DOB. The output buffer DOB outputs the read data transmitted through the multiplexer circuit MPX from the output terminals DO _{0 to} DO _m .

The memory mat PR-MAT is commonly used as a redundant circuit corresponding to a defective word line and a defective bit line, and by selectively supplying X-system and Y-system address signals to the input of RP-YDC. Alternatively, the gate circuit and the sense amplifier may be shared.

Although not particularly limited, in this embodiment, the nonvolatile memory element is used to store the relief address. The relief address is written by the address buffer circuit ADB which receives the address signals A _{0 to} A _n.
By converting the X-system and Y-system address signals formed in 1 into write data by the relief address selection circuit RAS and writing them into the nonvolatile memory element arranged in the relief address memory circuit PR-ADD (PR-ADS). Remember. Although not particularly limited, the relief address storage circuit PR-
Addresses of a plurality of defective word lines and addresses of a plurality of defective bit lines can be stored in ADD (PR-ADS). Relief address storage circuit P for storing these defective word line addresses and defective bit line addresses
The address in R-ADD (PR-ADS) is determined by the word line selection circuit RAST which decodes the internal address signal. That is, the redundant word line selection circuit RAS
The address (defective address) of the defective word line (defective bit line) is written at the address assigned by the output signals AST _{1 to} AST _Z of T.

Relief address storage circuits PR-ADD, PR
-ADS stores the address to be relieved (defective address), and when an address that matches the written address is input, the word line selection signals RWS _{1 to} RWS
_p , RWS ₁ B to RWS _p B or RWS _{1 to} RWS _p B
And the word lines of the redundant memory mat PR-MAT and the redundant circuit PR-DAS are selected. Further, it forms an output switching signal of the multiplexer circuit MPX.

The control circuit CONT has a chip enable signal CEB for activating the present semiconductor integrated circuit device,
Upon receiving the output enable signal OEB for controlling the output buffer circuit DOB at the time of reading, the activation signal ceB of each circuit block and the sense amplifier circuit MR-SAM are received.
And the activation signal sacB of the output buffer circuit DOB.

In addition, the control circuit CONT has nonvolatile memory elements (PR-MAT, PR-B) arranged for redundancy.
MAT, PR-ADD, PR-DAS) write high voltage Vpp and a write enable signal WEB for performing write control, although not particularly limited, and receives an internal write control signal weB and a relief address storage write control signal R.
S, RWNS, etc. are formed.

Although not particularly limited, the high voltage Vpp and the write enable signal WEB are supplied to the pads Vpp and WEB provided on the semiconductor substrate. In this embodiment, these pads are not connected to external terminals (external pins). As a result, the mask ROM of this embodiment is
The external pins are compatible with the mask ROM that does not have the defect relief function. Further, the data input terminal DI is coupled to the data output terminal (external terminal) DO.

FIG. 5 shows the redundant word line selection circuit RA.
A circuit diagram of one embodiment of ST is shown. Although not particularly limited, the redundant word line selection circuit RAST has a complementary address signal a ₀ , which is formed by an address buffer circuit ADB receiving Y-system address signals A _{0 to} A _h (h ≦ i).
a ₀ B to a _h , a _h B, and the relief address storage circuit PR−
Receiving the signal RWNS activated at the time of writing ADD (PR-ADS) to the memory element, it forms memory location allocation signals AST _{1 to} AST _j . For example, when 4-bit address signals A _{0 to} A ₃ are used, 16 kinds of storage location allocation signals AST _{1 to} AST ₁₆ can be formed. Of these, the signal AST ₁ is applied to the defective word line.
~ By assigning AST ₈ , memory mat MR
Even if there is a maximum of eight defective word lines in the -MAT, it is possible to replace them with the memory cells of the redundant memory mat PR-MAT. Therefore, when the rescue address storage circuit PR-ADD as described above is used, the redundant memory mat PR-MAT is provided with the nonvolatile storage elements corresponding to the eight word lines arranged in a matrix. ..

Writing to the storage element of the relief address storage circuit PR-ADS corresponding to the defective bit line is performed by the address signals A _{0 to} A _n and the signal RWNS.
The rest of the storage location allocation signals AST _{1 to} AST _j may be used. For example, of the assignment signal AST ₁ ~AST ₁₆ storage locations 16 types as described above,
The remaining signals AST _{9 to} AST ₁₆ may be associated with the defective bit line. As a result, the bit lines of the memory mat MR-MAT having up to eight defects can be replaced with the memory cells of the redundancy memory mat PR-BMAT. Therefore, the relief address storage circuit P as described above is used.
When R-ADS is used, the redundant memory mat PR
In BMAT, nonvolatile memory elements corresponding to the above eight bit lines are arranged in a matrix.

That is, Y-system address signals A _{0 to} A _n
The relief address storage circuits PR-ADD and PR
-A storage element in ADS is selected, and the address of the defective word line or the address of the defective bit line is written in the selected storage element. In this case, the external address terminal that receives the Y-system address signal is used to select the storage element in the relief address storage circuit. Therefore, the Y-system address signal indicating the defective bit line may be supplied using, for example, the X-system external address terminal. That is, at this time, the X-system external address terminal is also used as the input of the X-system address signal indicating the defective word line and the Y-system address signal indicating the defective bit line.

As described above, the defective address corresponding to the defective bit line is the 4-bit address signal A ₀ -A.
Allocation signal AST of 16 different storage locations corresponding to ₃
It is distinguished by _{1 to} AST ₁₆ .

FIG. 6 shows the repair address selection circuit RA.
A circuit diagram of one embodiment of S is shown. The relief address selection circuit RAS uses the assignment signals AST _{1 to} AS.
It includes a number of unit selection circuits corresponding to T _j . That is, according to the example described above, 16 unit selection circuits are included. Although not particularly limited, the unit selection circuit corresponding to the defective word line is partially different in configuration from the unit selection circuit corresponding to the defective data line. In the figure, the unit selection circuit corresponding to the defective word line is mainly shown.

This defective address unit selection circuit RAS is
X-system address signal A _{i + 1} ~A _n receiving an address buffer circuit each address signal is formed by ADB a _{i + 1} ~a _n receive respective relief address storage circuit PR-
The input address signal a _{i + 1} is generated by the signal RWNS activated when the ADD is written in the nonvolatile memory element.
The ~a _n as write data RAWa _i + 1 ~RAWa _n, is transmitted to the relief address storage circuit PR-ADD.
Responsive address In response to a signal RS _i B generated by the storage circuit PR-ADD as described later, in order to compare the repair address stored in the Noto phrase circuit PR-ADD with the X-system external address signal. Address signal Ca
forming the _i + 1 _{~Ca n.}

The repair address unit selection circuit RASC corresponding to the defective data line is shown by a broken line in FIG. The unit selection circuit RASC is similar to the unit selection circuit RAS. That is, in the unit selection circuit RAS, address signals to the NOR gate circuit NOR a _i + 1 ~a _n
, And the signal RSi, the repair address unit selection circuit RASC corresponding to the defective data line
The NOR gate circuit NOR is supplied with the address signals a _{0 to} a _i formed by the address buffer circuit ADB which receives the signal RAi and the Y-system address signals a _{0 to} a _i , and the other parts are the same as the unit selection circuit RAS. .. The unit selection circuit RASC is provided with Y supplied via an X-system external terminal.
System address signals a _{0 to} a _i (in the figure, a _{i + 1} to
write in Aru) indicated that a _n data RAW _a0 ~RAW
It is sent to the relief address storage circuit PR-RDS as _a3 (RAW _{ai + 1 to} RAW _{n in the} figure). In addition, the memory circuit PR-
Y-system address signals C _{a0 to} C _ai for comparison with the relief address stored in ADS are output in response to signal RAS _i . The signal RS _i is formed by relief address storage circuits PR-ADD and PR-ADS described below.

FIG. 7 shows a relief address storage circuit PR-A.
A circuit diagram of one embodiment of DD is mainly shown. The repair address storage circuit PR-ADD (PR-AD shown in FIG.
Although not particularly limited, S) includes the repair address storage circuits shown in FIG. 7 in the number corresponding to the above-mentioned allocation signals AST _{1 to} AST _j . According to the above-described example, 16 repair address storage circuits are included, 8 of them are storage circuits PR-ADD corresponding to defective word lines, and the remaining 8 are storage circuits corresponding to defective data lines. Circuit PR
-ADS. However, the NOR gate circuit NOR and the inverter circuit IV are common between the memory circuits PR-ADD corresponding to the defective word line, and similarly the memory circuit PR-AD.
The NOR gate circuit NOR and the inverter circuit IV are common between S. Also, the assignment signal and the unit selection circuit RAS
(RASC), memory circuit PR-ADD (PR-ADS)
Have a one-to-one correspondence with each other.

Next, the relief address circuit will be described by taking the memory circuit PR-ADD as an example.
The same applies to ADS. The relief address storage write signal RS is transmitted to the word line to which the above-mentioned nonvolatile memory element having the single-layer gate structure arranged as a memory element is coupled, and at the same time, the relief address unit selection circuit RAS.
Storage address data R formed by (RASC)
By AWa i + ₁ ~RAWa _n is transmitted to the data line, the writing into the memory element of the address of the defective word line (defective data line) is performed.

The data line to which the memory element storing the relief address is connected is connected to the input terminal of the sense amplifier SA, and is amplified by the sense amplifier SA in the read operation. In this embodiment, although not particularly limited, a 1-bit memory element is additionally provided as a memory element for storing a relief address in addition to the relief address. By storing the data of "1" information or "0" information according to the corresponding allocation signal in this 1-bit memory element, it is confirmed whether or not the relief address is stored, and the sense amplifier is stored. SA activation signals and activation signals RS ₁ B to RS _p B for forming address comparison signals Ca _{i + 1 to} C _n (C _{a0 to} C _ai ) of the repair address selection circuit RAS (RASC) are formed.

[0049] When the reading of the memory device storing the repair address is performed, the output signal of the sense amplifier SA, the address comparison signal _{Ca i + 1 ~Ca n (C} a0 ~C
It is input to the exclusive OR circuit to confirm the match / mismatch with _ai ). The output of the exclusive OR circuit is the output of the sense amplifier SA and the address comparison signal Ca _{i + 1} .
_If C _n (C _{a0 to} C _ai ) matches, it becomes “0”, and if they do not match, it becomes “1”. When all the data of the memory elements for storing the relief address match, one of the redundant word line selection signals RWS _{1 to} RWS _p is activated as a selection signal. Further, the redundant word line selection signal R
When any one of WS _{1 to} RWS _p is selected, the sense amplifier circuit PR provided in the redundant memory mat PR-MAT (or the redundant memory mat PR-BMAT)
-Activation of SAM (or PR-BSAM) or the like, and switching signal RSDA supplied to the multiplexer MPX
1, RSDA1B (RSDA2, RSDA2B) are formed. The switching signals RSDA1 and RSDA1B are activated when the memory circuit PR-ADD corresponding to the defective word line outputs the activated word line selection signal. On the other hand, the switching signals RSDA2 and RSDA2B are
The memory circuit PR-ADS corresponding to the defective bit line is activated when the activated word line selection signal is output.

The write signal R is not particularly limited.
S is based on the corresponding allocation signal AST _i .
For example, the signal RS shown in FIG. 7 is formed on the basis of the allocation signal AST ₁ . Of course, the word line may be shared between the memory circuits. In this case, a signal that becomes high level when writing the relief address may be used as the signal RS.

FIG. 8 shows a write data input circuit PR-.
A circuit diagram of one embodiment of a PGC is shown. Address buffer circuit AD for receiving Y-system address signals A _{0 to} A _i
Complementary internal address signals a ₀ , a ₀ B formed by B
~ A _i , a _i B and the data Data are decoded, and write data Dy _{0 to} Dy _k are supplied to each data line of the redundant memory mat PR-MAT by the write signal we.

FIG. 9 shows a redundant Y decoder circuit PR-.
A circuit diagram of one embodiment of YDC is shown. Y for redundancy
The decoder circuit PR-YDC has a Y-system address signal A _0.
To A _i , complementary internal address signals a ₀ and a ₀ B to a _i and a _i formed by the address buffer circuit ADB.
B is decoded to form the column selection signals y _{0 to} y _k supplied to the column switch gate PR-YGT.

FIG. 10 shows the redundant memory mat P.
A circuit diagram of an embodiment of the R-MAT, the column switch gate PR-YGT, and the sense amplifier circuit PR-SAM is shown. When the redundant word line is prepared eight as above, the redundant word line selection signal RWS ₁ ~RW
One word line in response to S ₈ are selected, nonvolatile憶素Ko connection monolayer gate structure is selected to it.
Each bit line constitutes a column switch gate PR-YGT through a depletion type MOSFET that receives an internal write control signal weB, and is connected to a common data line through a MOSFET that is switch-controlled by selection signals y _{0 to} y _k . The sense amplifier includes a source input, a grounded gate amplification MOSFET, and a P provided on the drain side thereof.
It is composed of a channel type load MOSFET and a CMOS inverter circuit which receives the output signal thereof. The common data line has an inverting amplifier circuit composed of an N-channel MOSFET for receiving the signal level of the common data line and a P-channel type load MOSFET provided on the drain side thereof, and a bias of the common data line for receiving the output signal thereof. It includes a source follower MOSFET that forms a voltage. With the same bias circuit, the above amplification MOSFET
The gate bias voltage of is set. The P-channel load MOSFET of the bias circuit is a control signal RSD.
A1B activates only during the operation period. Further, the source follower MOSFET for biasing the common data line and the amplifying MOSFET are turned off by the N-channel MOSFET which receives the signal RSDA1B.

Redundant circuit PR-D corresponding to the defective bit line
Redundant memory mat PR-BMAT, column switch gate PR-BYGT, sense amplifier circuit PR in AS
-BSAM is the same as the circuit shown in FIG.

Redundant circuit PR-D corresponding to the defective data line
Data input circuit PR- for supplying write data to AS
The BPC is similar to the data input circuit PR-PGC shown in FIG. That is, the data input circuit PR-BPC
The address signal a _0, a ₀ B~a _i, instead of a _i B, the address signal X based _{a i + 1, a i +} 1 B~a n, a n
Receiving B, the write data is supplied to the data line in the redundant memory mat PR-BMAT (see FIG. 13) in the redundant circuit PR-DAS. As a result, the redundant memory mat PR
In the -BMAT, the write data line is supplied to the data line designated by the X-system address signal and written (see FIGS. 8 and 10).

Further, X system address signals a _{i + 1} , a _{i + 1}
B~a _n, a _n B is, X-system address decoder PR-XD
Supplied to C. This address decoder PR-XDC
Is similar to the Y-system address decoder PR-YDC, and the Y-system address signals a _0, a ₀ B to a _{i ,} a _i B.
Instead of X, the X-system address signals a _{i + 1} , a _{i + 1} B to a
Decode _n, a _n B to form selection signals x _{0 to} x _k (see FIG. 9). The formed selection signals x _{0 to} x _k are the column switch gates P provided between the data line and the common data line in the redundant memory mat PR-BMAT.
It is used as an R-BYGT selection signal (see FIG. 10).

The data input circuit PR-BPC is used when writing data to the memory cell in the redundant circuit PR-DAS, and the X-system address decoder PR-YDC is used for writing data from the memory cell in the redundant circuit PR-DAS. Used when reading data.

In the present embodiment, the X-system address signal is supplied to the data input circuit PR-BPC, but a Y-system address signal may be supplied instead. .. In this case, the data input circuit PR-PGC can be used instead of the data input circuit PR-BPC as shown by the dashed line in FIG.

FIG. 11 shows a circuit diagram of an embodiment of the multiplexer MPX. In this example, 3
A clocked inverter circuit having a status output function is used. When the inverted switching signal RSDAB is activated, the memory mat MR-MAT forming the mask ROM is formed.
The clocked inverter circuit that receives the read signal of the memory element selected in 1 is activated and transmits it to the output buffer circuit DOB. Non-inversion switching signal R
When SDA is activated, the redundant memory mat PR-
The clocked inverter circuit that receives the read signal of the memory element selected in the MAT or PR-BMAT is activated and transmits it to the output buffer circuit DOB.
That is, correct data stored in the redundant memory mat PR-MAT or PR-BMAT is output instead of the read data including the defective bit existing in the memory mat MR-MAT.

To facilitate the understanding of the invention, FIG.
Although the redundant circuit corresponding to the defective word line and the redundant circuit corresponding to the defective bit line are drawn separately, both of them can basically have the same configuration as described above. Is represented by one black box.
In this case, the sense amplifiers PR-SAM, PR-BS
A multiplexer MPXX is further provided on the output side of the AM. The multiplexer MPXX has a configuration similar to that described above, and when the output signals (switching signals) RSDA1 and RADA1B from the memory circuit PR-ADD are activated, the output of the sense amplifier PR-SAM is selected and output. .. On the other hand, when the switching signals RSDA2 and RSDA2B from the memory circuit PR-ADS are activated,
The output of the sense amplifier PR-BSAM is the multiplexer M.
It is selected and output by PXX.

Switching signal RSDA1 (RSDA2)
Becomes a high level switching level when the defective address written therein and the address input from the outside match in the memory circuit PR-ADD (PR-ADS).
The switching signal RSDA is the switching signal RSDA1.
Alternatively, when RSDA2 becomes the switching level, it becomes the high level (switching level). Therefore, the switching signal RSDA is the switching signals RSDA1 and RSDA.
2 and an inverter circuit receiving the output thereof.

FIG. 12 shows a circuit diagram of another embodiment of a mask type ROM to which the present invention is applied. The mask ROM of this embodiment is composed of a plurality of series circuits each having a plurality of N-channel type storage MOSFETs connected in series. Each of the storage MOSFETs Qm is formed as a depletion type or an enhancement type according to the stored information. Writing of stored information to such a memory element is performed by the ion implantation method as described above. In the figure, the depletion type MOSFET is distinguished from the enhancement type MOSFET by adding a straight line to its channel portion.

A series circuit corresponding to one data line D1 shown as a representative is an MO for column selection.
SFET T1, T2, etc. and memory MOSFE for data storage
It is composed of TQ1 to Q3 and the like. A series circuit adjacent to this and corresponding to another data line D2 which is exemplarily shown as a representative is composed of MOSFETs T3 and T4 for column selection, storage MOSFETs Q4 to Q6 for data storage, and the like. For example, the column selection MOSFETs T1 and T4 shown by way of example are depletion type MOSFs.
ET, T2 and T3 are enhancement type MOSFETs
When the other series MOSFETs, each of which is omitted in the figure, is in the ON state, the selection signal supplied to the gates of T1 and T3 by the column selector is low level and the selection signal supplied to the gates of T2 and T4. Is high level, both T1 and T2 are in the ON state,
Storage MOSFETs Q1 to Q3 in series with the data line D1
Etc. are connected. In addition, T1, T by the column selector
When the selection signal supplied to the gate of
When the selection signal supplied to the gates of T4 and T4 is low level, both T3 and T4 are turned on, and the series-type storage MOSFETs Q4 to Q6 and the like are connected to the data line D2. Therefore, although not shown, each data line D in FIG.
It is possible to provide a plurality of series circuits in parallel with respect to 1, D2 and the like.

Storage MOS of each series form of memory array
Of the FETs, the memory MOSFET Q corresponding to the lateral direction
The gates of m are commonly connected to word lines W1, W2, W3, etc. which are shown as representative examples. These word lines W1 to W3 are connected to the corresponding output terminals of the X decoder. The data lines D1, D2, etc. are Y
It is connected to the common data line CD via the decoder. The Y decoder shown in the figure is a combination of the Y decoder itself and a column switch circuit including switch elements which are switch-controlled by a selection signal thereof.

The common data line CD is connected to the input terminal of the sense amplifier SA. The sense amplifier SA refers to the reference voltage formed by the reference voltage generation circuit VRF,
The high level and the low level of the read signal of the selected memory cell are sense-amplified. Although not particularly limited, the sense amplifier SA may perform the sensing operation by referring to the reference voltages respectively formed by the dummy arrays including the memory circuits having the same configuration as the memory array section. The dummy array is a storage MOSFE
It is possible to use a transistor in which TQm is entirely composed of an enhancement type MOSFET and is constantly turned on by constantly supplying the power supply voltage Vcc to its gate.

The address selection operation of the vertical ROM in this embodiment will be described below. The X decoder decodes the internal address signal supplied from the row address buffer,
A decode output is formed in which the selected level is the low level and the non-selected level is the high level. For example, when the number of word lines is 512, one selected word line is set to low level and the other 511 remaining word lines are set to high level. Thus, if the storage MOSFET coupled to the selected word line is a depletion type, a current path is formed in the series circuit, and if it is an enhancement type, no current path is formed. The Y decoder YDCR decodes the internal address signal supplied through the address buffer and selects one of the 512 data lines and connects it to the common data line CD. As a result, the read signal on the selected one data line is changed to the sense amplifier S.
Amplified by A. When the read data is read in units of multiple bits such as 8 bits or 16 bits, 8 or 16 memory arrays similar to the above are provided, or
Alternatively, 8 or 16 data lines may be simultaneously selected by the Y decoder, and a sense amplifier and an output circuit may be provided corresponding to each. Such a vertical RO
The nonvolatile memory element as described above is used to relieve the defect of M. The circuit shown in FIG. 4 and the like can be used for the repair address storage circuit and the redundancy memory mat using this nonvolatile storage element.

FIG. 13 is a flow chart for explaining one embodiment of the write operation to the relief bit when the defect relief is performed. Although not particularly limited, in the mask type ROM of this embodiment, when a high voltage of 10 V or more is applied from the terminal Vpp, it is detected and the internal logic of the mask type ROM is switched to the repair selection mode. Then, the bit line relief or the word line relief is selected. This selection can be determined by the addresses supplied to the Y-system address terminals A _{0 to} A _i . That is, if performing the word line relief, and applies an address to instruct assignment signals AST ₁ ~AST ₈ assigned to the storage circuit PR-ADD to the terminal A ₀ to A _i, if performing bit line relief, storage Addresses indicating the assignment signals AST _{9 to} AST ₁₆ assigned to the circuit PR-ADS are applied to the terminals A _{0 to} A _i . In this way, by applying a desired address to the terminals A _{0 to} A _i , the memory circuit P
In R-ADD and PR-ADS, an area (write block) to be written is selected. . Next, the address to be relieved is applied to the X-system address terminals A _{i + 1 to} A _n , and the relief address is written and stored in the relief memory. That is, the X-system or Y-system address to be relieved is written in the area corresponding to the designated allocation signal.

Although not particularly limited, a writing method based on a writing and writing verifying algorithm used in a conventional EPROM writing method may be used here, if necessary. When the storage of the address is completed, the memory information (output data) is subsequently stored in the same manner as the address storage, whereby the relief is completed. Writing of this memory information is performed, for example,
The X-system or Y-system address to be relieved is supplied to the X-system or Y-system address terminal, and Y for selecting a desired cell is supplied.
The system or X system address is supplied to the Y or X system address terminal. As a result, the memory circuit PR-ADD or P
R-ADS to redundant memory mats PR-MAT, PR-
The word line selection signal RSW _i for BMAT is output, and the memory information is supplied from the data input circuit PR-PGC or PR-BPC to the redundant memory mat and written.

The selection of the bit line relief or the word line relief may be performed by providing a control terminal in advance and selecting the potential of the control terminal. When the data input circuit PR-PGC is also used as the input circuit PR-BPC, a latch circuit or the like is provided in the selection circuit RASC so that the address and the data input supplied to the memory circuit PR-ADS as an address to be compared. The address supplied to the circuit PR-PGC is preferably set separately.

The above writing operation is not particularly limited, but is performed in the probing process when the circuit is completed on the semiconductor wafer. That is, in the probing process, a mask ROM read test is performed, a defective bit is detected from the inspection result, a relief address is written, and storage data corresponding to the relief address is written. When the defect relief is performed, by performing the writing in the probing process as described above, when the mask ROM is completed, a special control terminal is not required for writing the relief address and the data corresponding thereto. ..

FIG. 14 is a flow chart for explaining one embodiment of the relief data read operation. When the read mode is set by the external control signal, it is automatically internally determined whether or not it is a repaired product by the repair selection signal RSp stored when the write block is selected at the time of repair writing described above. When not being relieved, the relief circuit section remains in the deactivated state, and the reading corresponding to the external address of the main body memory area is performed.

When the defect relief is being performed, the relief memory unit storing the address for relief is activated and it is determined whether or not the external address and the storage address match. If it is not the relief address, the data corresponding to the external address of the main body memory area is connected to the data output circuit to perform the read operation. On the other hand, when the external address and the storage address match, the sense amplifier of the main body memory unit is deactivated, and at the same time, the sense amplifier for reading the stored relief data is activated.
This output is connected to the data output circuit and read.

FIG. 15 shows a mask type RO according to the present invention.
A block diagram of another embodiment of M is shown. In this embodiment, a redundancy circuit PR-ADS for repairing bit lines,
The PR-DAS is provided and only the relief corresponding to the defective bit line is performed. That is, the repair part of the defective word line is omitted from the embodiment of FIG. 4, and the redundancy circuit is configured only by the repair part of the bit line. That is, the defect in the memory mat MR-MAT may be repaired only by the word line system or only by the bit line system.

In the mask type ROM, data is usually read in units of a plurality of bits. For example, 16 Mbits has a structure of 16 bits × 1048576 words.
Due to such a configuration, the number of memory cells connected to one word line or bit line is reduced to perform high speed access. For example, it is conceivable that the memory area is divided into 8 memory mats, and 2 bits are read for each memory mat so that data is read in units of 16 bits as a whole. In this case, one memory mat has a storage capacity of about 2 Mbits, about 2K memory cells are connected to the word lines, and about 1M memory cells are arranged on the bit lines to make a total of about 2M bits. It can have a bit storage capacity.

In this case, eight memory mats are selected in parallel and two bits of data are output from each memory mat, so that data of 16 bits in total can be read. In the ROM having such a memory mat structure, a defect of a word line or a bit line occurs in each memory mat. Therefore, the redundant word lines and bit lines of this embodiment have a relatively small storage capacity corresponding to the memory mat. In other words, 1
1 when data is read in units of 6 bits
Instead of replacing all 6 bits with data from the redundant circuit, only 2 bits for each memory mat are replaced when repairing a word line, and 1 bit is repaired when repairing a bit line.
Only one bit corresponding to one bit line is replaced. In such a configuration, each memory mat cannot be designated externally. Therefore, the defective address storage unit is provided with an internal address storage unit that specifies a memory mat. When the memory mat is composed of eight memory mats as described above, a 3-bit mat designation storage unit is provided. The information in the mat designation storage section is used not only as a signal for deactivating the defective mat, but also as a selection signal for selecting which output bit to replace the read data.

FIG. 3 is a plan view of another embodiment of the nonvolatile memory element according to the present invention. In the figure, as a result of providing the slits in the aluminum layer 15 forming the word line WL, a part of the floating gate 8 is exposed. This slit is not particularly limited, but has a rectangular shape that is parallel to a word line extending over two floating gates. When the word line is extended to cover the entire surface of the floating gate in order to form the barrier layer as described above, the word line becomes thicker accordingly. When the word line becomes thick in this way, cracks are formed in the aluminum layer 15 as the word line and the lower insulating film 13 of the aluminum layer 15 due to the stress of the final passivation film,
There is a risk that the device characteristics will be impaired. Therefore, in this embodiment, slits are provided in the aluminum layer that acts as the barrier layer to reduce the substantial thickness to prevent the above-described cracks from occurring.

The aluminum layer 15 forming the word line WL may be extended so as to cover a part of the floating gate. Instead of this, the data line D
Aluminum layer 1 forming L or source line SL
5 may be extended to form a barrier layer that covers a part or the entire surface of the floating gate. Similarly to the above, a slit may be provided to prevent cracks.

When the floating gate is partially exposed by providing the slits as described above, it becomes easy to test the semiconductor integrated circuit including the nonvolatile memory element having the single-layer gate structure. That is, the test of the non-volatile memory element is performed in both the state before writing the data and the state after writing the data.

In the erasing step, the nonvolatile memory element is returned to the initial state. That is, the state before writing data is set. In the non-volatile memory element having the single-layer gate structure of this embodiment, a barrier layer made of aluminum or the like is provided on the floating gate. Although this aluminum layer itself does not transmit ultraviolet rays, it can be erased by diffraction and irregular reflection of ultraviolet rays. In particular, when the barrier layer is provided only on a part of the floating gate or the slit is provided as in the above embodiment, the erasing can be efficiently performed. Even if the entire surface of the floating gate is covered with aluminum to prevent radical hydrogen from the final passivation film from reaching the floating gate, the distance that the barrier layer extends from the floating gate is short. It can be sufficiently erased by various ultraviolet diffraction and irregular reflection. As a result, the redundant circuit can be tested and used, and reliable defect relief can be realized in combination with the good data retention characteristic as described above.

FIG. 17 is a circuit diagram of another embodiment of the relief address storage circuit for storing the relief address. In the figure, M0 to Mm and MB0 to MBm are the above-mentioned nonvolatile memory elements (memory cells) of the one-layer gate structure. A0 to Am are input address signals. A
0B to AmB are signals obtained by inverting the phases of the input address signals A0 to Am. SA indicates a sense amplifier.

Address signal A as an address to be relieved
When 0 is at low level (Low) and the address signals A1 to Am are at high level (High), writing is performed on the cells MB0 and M1 to Mm of the EPROM. In such a state, the address to be relieved (A0 = Low, A1 to Am
= High) is input, the memory cells M0 and MB1
Low is supplied to the gate of ~ MBm. Therefore, these memory cells M0 and MB1 to MBm are cut off regardless of the presence or absence of writing. On the other hand, the memory cells MB0, M1 to Mm have High gates.
Is supplied, but the cells are cut off in the same manner because no writing is performed on these cells. Therefore, when an address that matches the stored relief address is input, no current flows through the memory cell.

On the other hand, for example, the address signal A0 =
When an address such as High is input, the memory cell M0 is not written as described above,
This memory cell M0 is turned on, a current flows through it, and a mismatch between the address stored in the repair address storage circuit and the input address can be detected.

When the memory cells Mi + 1 to Mm are written and the memory cells MBi + 1 to MBm are also written, the input address signals Ai + 1 to Am input to these memory cells are inputted. Irrespective of the level, it is possible to detect the match / mismatch between the repair addresses stored in the memory cells M0 to Mi and MB0 to MBi and the input addresses A0 to Ai input to their gates. Similarly, if data is written in the memory cells M0 to Mi and MB0 to MBi, the memory cells Mi + 1 to Mm, MBi + 1 to
Relief address and input address A stored in MBm
Matching / mismatching with i + 1 to Am can be detected.

Utilizing this fact, for example, M0 to Mi,
MB0 to MBi and A0 to Ai are assigned to X-system addresses, and Mi + 1 to Mm, MBi + 1 to MBm and Ai + 1 to A are assigned.
If m is assigned to a Y-system address, the same repair address storage circuit can be used for the X-system and the Y-system, and the match / mismatch detection can be performed. In order to store and detect a plurality of defective addresses less than or equal to the number of addresses (m + 1), this embodiment can reduce the number of sense circuits (SA).

The functions and effects obtained from the above-mentioned embodiment are as follows. (1) As a defect relief circuit of a memory circuit in which read-only memory elements are arranged in a matrix, a control gate formed of a diffusion layer and a part of the control gate via a thin insulating film are interposed. A nonvolatile memory element including a floating gate formed of conductor layers formed so as to overlap each other and a barrier layer formed so as to cover a part or the entire surface of the floating gate is used, and a word line and a bit line are formed. By storing the corresponding defective address and storing the corresponding data, radical hydrogen, which is presumed to be diffused from the final passivation film on the device surface, is trapped by the barrier layer. Non-volatile with a simple structure that can prevent the destruction of accumulated information charges Effect that defect relief under high reliability by using the memory element can be realized is obtained.

(2) By carrying out the relief of both the word line system and the bit line system, the effect that reliable and rational defect relief can be realized is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the barrier layer may be formed below the faunal passivation film and above the floating gate layer. Various patterns can be adopted for the pattern of the non-volatile memory element having the single-layer gate structure. Mask type RO
The M memory cells and memory mats can adopt various embodiments. The relief address storage circuit and the like can be changed in various ways. In addition, the X decoder PR-XD
As the C and Y decoders PR-YDC, Men's X decoders MR-XDC and Y decoders MR-YDC may be used.

In the above description, the defective bit,
It is shown that a redundant circuit is used to repair the bit line or the word line. However, the redundant circuit described above may be used to change the Noto phrase information of the mask type ROM without changing the stored information of the regular memory mat. The present invention can be widely used for semiconductor memory devices such as mask ROM.

[0089]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, as a defect relief circuit of a memory circuit in which read-only memory elements are arranged in a matrix, a control gate formed of a diffusion layer,
A floating gate formed of a conductor layer formed so as to partially overlap the control gate via a thin insulating film, and a barrier layer formed so as to cover a part or the entire surface of the floating gate. It is presumed that the non-volatile memory element including and is used to store the defective address corresponding to the word line and the bit line, and to store the data corresponding to each, so that the final passivation film on the element surface is diffused. Since radical hydrogen that is trapped by the barrier layer is trapped by the barrier layer, it is possible to prevent destruction of information charges accumulated in the floating gate, and to realize defect relief with high reliability by using a nonvolatile memory element with a simple structure. it can.

[Brief description of drawings]

FIG. 1 is a manufacturing step sectional view showing an embodiment for explaining a nonvolatile memory element according to the present invention.

FIG. 2 is an element pattern diagram showing an embodiment of a nonvolatile memory element used in a redundant circuit of a semiconductor memory device according to the present invention.

FIG. 3 is an element pattern diagram showing another embodiment of the nonvolatile memory element used in the redundant circuit of the semiconductor memory device according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a mask ROM according to the present invention.

FIG. 5 is a circuit diagram showing an example of a redundant word line selection circuit RAST in the mask ROM.

FIG. 6 is a circuit diagram showing an embodiment of a repair address selection circuit RAS in the mask ROM.

FIG. 7 is a circuit diagram showing an embodiment of a relief address storage circuit PR-ADD in the mask ROM.

FIG. 8 is a circuit diagram showing an embodiment of a write data input circuit PR-PGC in the mask ROM.

FIG. 9 is a circuit diagram showing an example of a redundant Y decoder circuit PR-YDC in the mask ROM.

FIG. 10 is a redundancy memory mat PR-MAT and a column switch gate PR-YG in the mask ROM.
It is a circuit diagram which shows one Example of T and sense amplifier circuit PR-SAM.

FIG. 11 is a circuit diagram showing an embodiment of a multiplexer MPX in the mask ROM.

FIG. 12 is a circuit diagram showing another embodiment of a mask type ROM to which the present invention is applied.

FIG. 13 is a flow chart diagram for explaining one example of a write operation to a repair bit when performing defect repair.

FIG. 14 is a flow chart diagram for explaining an example of a read operation of relief data.

FIG. 15 is a block diagram of another embodiment of the mask type ROM according to the present invention.

FIG. 16 is a data retention characteristic diagram of a nonvolatile memory element for explaining the present invention.

FIG. 17 is a circuit diagram showing another embodiment of a repair address storage circuit.

[Explanation of symbols]

QE ... Nonvolatile memory element, QN ... N channel MOSF
ET, QP ... P-channel MOSFET, 1 ... Semiconductor substrate, 2, 102 ... Well region, 3 ... Field insulating film,
4 ... Channel stopper, 7, 107 ... Gate insulating film, 5, 11, 13, 16, 201, 211 ... Insulating film (interlayer insulating layer), 8, 108, 204, 205 ... Conductive layer, 15, 17 ... Wiring layer , 6, 9, 10, 109, 11
2 ... Diffusion layer, 14, 114 ... Contact hole, 18 ...
Final passivation film, 204 ... Dielectric film, A
DB ... Address buffer, MR-MAT ... Mask RO
M, PR-MAT ... Memory circuit for word line redundancy, P
R-DAS ... Redundant circuit for bit line system, PR-BMAT ... Memory circuit for bit line system, MR-XDC ... X coder circuit, MR-YGT, PR-YGT, PR-BYGT ... Column switch gate, YDC ... Y decoder circuit , MR-
SAM, PR-SAM, PR-BSAM ... Sense amplifier circuit, PR-PBC ... Data input circuit, PR-XDC ...
Address decoder, DIB ... Input buffer circuit, DOB
... Output buffer circuit, MPX, MPXX ... Multiplexer, RAS ... Relief address selection circuit, PR-ADD, P
R-ADS ... Relief address storage circuit, RAST ... Redundant word line selection circuit, CONT ... Control circuit, PR-PGC ...
Write data input circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Yoshii 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor Hisahiro Morinuchi 5 Mizumizuhoncho, Kodaira-shi, Tokyo In the Musashi Factory, Hitachi 20-21, Ltd. (72) Inventor Kenichi Kuroda In the Musashi Factory, 5-200-1, Kamimizuhonmachi, Kodaira-shi, Tokyo (72) Incorporated, Akinori Matsuo Tokyo 5-20-1 Kamimizuhonmachi, Kodaira City

Claims (5)

[Claims] 1. A storage circuit having a plurality of read-only storage elements arranged in a matrix, a control gate formed of a diffusion layer, and a part of the control gate overlapping the control gate via a thin insulating film. Of a predetermined word line in the memory circuit by using a nonvolatile memory element including a floating gate formed of a conductor layer formed so as to cover the floating gate and a barrier layer formed so as to cover a part or the entire surface of the floating gate. An address storage unit for storing an address and an address of a predetermined bit line, and a data storage unit for storing data to be output instead of the data on the predetermined word line and the predetermined bit line. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the address storage means has means for storing an information bit indicating whether or not an address is written in addition to the word line and the bit line. .. 3. The semiconductor memory device according to claim 1, wherein the data storage unit has a plurality of elements having the same structure as the nonvolatile storage element, and these elements are arranged in a matrix. 4. The semiconductor memory device according to claim 2, wherein the data storage unit has a plurality of elements having the same configuration as the nonvolatile storage element, and these elements are arranged in a matrix. 5. The semiconductor memory device according to claim 4, wherein the memory circuit is a mask ROM.