JPH05144278A - Flash memory - Google Patents

Abstract

PURPOSE:To utilize the chip surface effectively and to downsize the chip by providing a redundancy block, having a source line independently from a plurality of erasing blocks, commonly for a plurality of erasing blocks. CONSTITUTION:A block 27 is sectioned into (m+1) erasing blocks having independent source lines 400-40m. Consequently, the erasing blocks 390-28m can be erased collectively as a unit. The erasing blocks 280-28m are commonly provided with a redundancy block 20 having a source line 40R independently from the erasing blocks 290-28m. Consequently, the number of columns of the redundancy block is reduced to one, for example, resulting in the prevention of increase of chip area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM as a memory cell transistor in a semiconductor memory device.
(Electrically Erasable and Programmable Read Only
Memory) A flash that has a cell transistor (hereinafter referred to as a cell transistor), and is configured to electrically erase data written in the cell transistor in a unit of a chip or a block. Regarding memory.

Generally, in a semiconductor memory device, since the manufacturing yield directly affects the manufacturing cost, it is important to improve the manufacturing yield. There is a redundancy technique as one method for improving the manufacturing yield. In flash memory,
Due to its operation, column redundancy (replacement of defective bit lines with redundant bit lines) is generally adopted.

[0003]

2. Description of the Related Art Conventionally, a flash memory shown in FIG.
It is known that the main part is shown in. 1 in the figure
If there is no defective cell, the original block is used as it is, and if there is a defective cell in block 1, 2 is a redundant block used in place of the column including the defective cell.

Further, 3 ₀ , 3 ₁ , 4 ₀ , 4 ₁ are original cell transistors, 5 ₀ , 5 ₁ are redundant cell transistors, and 6 ₀ , 6 ₁ are cell transistors. Word lines X ₀ and X ₁ are word line selection signals output from a row decoder (not shown) that decodes a row address.

Further, 7 ₀ and 7 _n are original bit lines, and 7 _R
Is a bit line for redundancy, 8 ₀ and 8 _n are nMOS transistors forming an original column gate, 8 _R is an nMOS transistor forming a column column for redundancy, Y ₀ and Y _n are original column selection signals, and RED Is a redundant column selection signal, and 9 is a sense amplifier for amplifying the read data.

[0006] Further, 10 is the cell of the original block 1
Source lines commonly provided to the transistors 3 ₀ , 3 ₁ ... 4 ₀ , 4 ₁ ... And the cell transistors 5 ₀ , 5 ₁ ... Of the block 2 for redundancy, 11 is a source line 10 Through the cell transistors 3 ₀ , 3 ₁ ... 4 ₀ , 4 ₁ ...
A source power supply circuit that supplies a source voltage to 5 ₀ , 5 ₁ ...

Here, the cell transistors 3 ₀ , 3 _1, ...
-, 4 _0, 4 ₁ ..., 5 _0, 5 ₁ ... are configured to indicate its schematic cross-sectional view in FIG. In the figure, P 12 ^- -type silicon substrate, 13 is a drain made of N ⁺ diffusion layer, the source 14 is composed of N ⁺ diffusion layer, 15 a floating gate, 16 a control gate, V _G is the control gate voltage, V _D Is the drain voltage and V _S is the source voltage.

In such a cell transistor, at the time of writing, for example, V _G = 12 [V], V _D = 6 [V], V _S =
0 [V], electrons are injected from the drain 13 to the floating gate 15, and when reading, for example, V _G =
It is set to 5 [V], V _D = 1 [V], and V _S = 0 [V]. At the time of erasing, for example, V _G = 0 [V], V _D = open,
Since V _S = 12 [V], electrons are extracted from the floating gate 15 to the source 14.

In such a conventional flash memory, the cell transistors 3 ₀ , 3 ₁ of the original block 1 are originally used.
... 4 ₀ , 4 _1, ... And one source line 10 for the cell transistors 5 ₀ , 5 _1, ... Of the block 2 for redundancy.
Are shared, the data of the cell transistors 3 ₀ , 3 ₁ ... 4 ₀ , 4 ₁ ... And the data of the cell transistors 5 ₀ , 5 ₁ ... Will be erased.

[0010]

As described above, the source line 10 common to the original block 1 and the redundant block 2 is provided, and the original block 1 and the redundant block 2 are collectively packaged. According to the configuration of the conventional flash memory which is a unit of erasing, the original block 1 is further divided in response to a user's request, a source line is provided for each divided block, and the divided block is provided. When batch erasing can be performed for each divided block, a redundant block that is not necessarily required for each divided block is provided with a common source line for each divided block. However, there is a problem in that

For example, in the case of a so-called x8 configuration in which the output is 8 bits, eight x1s having common source lines are used.
Although the original block of the configuration is required, according to the configuration of the conventional flash memory, a block for redundancy is provided for each of the 8 original blocks of the x1 configuration, There is a problem that the chip surface cannot be effectively used.

In view of the above points, the present invention can increase the number of erase blocks to be collectively erased without increasing the chip area, and in the case where the number of erase blocks is not increased. Another object of the present invention is to provide a flash memory in which the chip surface can be effectively used and the chip can be miniaturized in the case of a multi-bit configuration.

[0013]

A flash memory according to the present invention is provided with a plurality of erase blocks composed of a plurality of original cell transistors having a common source line, and the plurality of erase blocks are collectively formed. A unit block for erasing, and a redundant block composed of a plurality of redundant cell transistors having a common source line independent of the plurality of erasing blocks is provided commonly to the plurality of erasing blocks. To be done.

[0014]

In the present invention, a plurality of erase blocks composed of a plurality of cell transistors having a common source line are provided. A redundant block having a common source line is provided for each of the plurality of erase blocks. Instead, a redundant block composed of a plurality of redundant cell transistors having a common source line independent of the plurality of erase blocks is provided commonly to the plurality of erase blocks.

Therefore, according to the present invention, it is possible to increase the number of erase blocks in response to a user's request without reducing the number of columns of redundant blocks and increasing the chip area. Even when the number of erase blocks is not increased, the number of columns of redundant blocks can be reduced, the chip surface can be effectively used, and the chip size can be reduced in the case of a multi-bit configuration.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2 by taking a flash memory having a multi-bit output as an example.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. In the figure, 17 is a row decoder to which a row address is input, and 18 is a column decoder to which a column address, a redundant cell selection signal and a test cell selection signal are input.

Further, 19 is a block of x8 configuration in which original cell transistors are arranged, 20 is a redundant block in which redundant cell transistors are arranged, and 21 is a testing cell transistor. This is a test block.

Further, 22 ₀ and 22 _m are the source power supply circuits of the block 19, 23 is the source power supply circuit of the redundancy block 20, and 24 is the source power supply circuit of the test block 21.

FIG. 2 is a circuit diagram showing a part of the original block 19 and the redundant block 20. In FIG. 2, 27 is one of the blocks 19 of the block 19, 28 ₀ , 28 _m is an erase block.

Further, 29 ₀ , 29 ₁ , 30 ₀ , 30 ₁ , 31
₀ , 31 ₁ , 32 ₀ , 32 ₁ are original cell transistors, 33 ₀ , 33 ₁ are redundant cell transistors, 34
₀ and 34 ₁ are word lines for selecting cell transistors,
X ₀ and X ₁ are word line selection signals.

Further, 35 ₀ , 35 _a , 35 _b , and 35 _n are original bit lines, 36 _R is a redundant bit line, and 37 ₀ and 37.
_a , 37 _b , and 37 _n are nMOs that form the original column gates.
S transistor, 38 _R is an nMOS transistor forming a column column for redundancy, Y ₀ and Y _n are original column selection signals, RED is a redundancy column selection signal, 39 is a sense amplifier for amplifying read data, 40 ₀ , 40 _m , 40
_R is the source line.

In this embodiment, the block 27
The, m + 1 having a separate source line 40 ₀ ··· 40 _m
Since the erase blocks 28 ₀ ... 28 _m are sectioned, the erase blocks 28 ₀ ... 28 _m can be collectively erased. In this case, in this embodiment,
The collective erase of the redundant block 20 is performed at the same time as the collective erase of the erase block including the redundant column.

As described above, according to this embodiment, the original block 27 is divided into the erase blocks 28 ₀ ... 28 _m , but these divided erase blocks 28 _{0 are divided.}
... Erase blocks 28 ₀ ... 2 without providing a redundant block having a common source line for each of 28 _m
Since the redundant block 20 having the source line 40 _R independent of 8 _m is provided in common to the erase blocks 28 ₀ ... 28 _m , the number of columns of the redundant block is reduced. One redundant column should be provided,
It is possible to prevent an increase in chip area.

Further, when the structure of this embodiment is applied, even if the number of erase blocks is not increased, in the case of a multi-bit structure, each of the blocks of the original × 1 structure and the redundant block are used. When the source lines are independently provided, the number of columns of the redundant blocks is reduced as compared with the case where the redundant block is provided for each block of the original × 1 configuration. By providing one redundant column, the chip surface can be effectively used and the chip can be miniaturized.

[0026]

As described above, according to the present invention, a plurality of erase blocks including a plurality of cell transistors having a common source line are provided. The source line is provided in each of the plurality of erase blocks. The number of columns of the redundancy block is not provided because a redundancy block having a source line independent of these erase blocks is provided in common to the erase blocks. Is reduced, without increasing the chip area,
The number of erase blocks can be increased, and even when the number of erase blocks is not increased, the number of columns in the redundant block is reduced and the chip surface is effectively used in the case of a multi-bit configuration. It is possible to reduce the size of the chip.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a block of x8 configuration and a block for redundancy.

FIG. 3 is a circuit diagram showing a main part of a conventional flash memory.

FIG. 4 is a schematic cross-sectional view of a cell transistor.

[Explanation of symbols]

19 × 8 configuration block 20 Redundancy block 21 Test block 22 ₀ , 22 _m , 23, 24 Source power supply circuit

Claims (2)

[Claims] 1. A plurality of erase blocks composed of a plurality of original cell transistors having a common source line are provided, each of the plurality of erase blocks is a unit block for collective erase, and the plurality of erase blocks are provided. A flash memory, characterized in that a redundancy block composed of a plurality of redundancy cell transistors having a common source line independent of the block is provided commonly to the plurality of erase blocks. 2. The flash memory according to claim 1, wherein the batch erase of the redundant blocks is performed at the same time as the batch erase of erase blocks including redundant columns.