JP3144002B2 - Flash memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM as a memory cell transistor in a semiconductor memory device.
(Electrically Erasable and Programmable Read Only
Memory) A flash memory having a cell transistor (hereinafter referred to as a cell transistor) and configured to electrically and collectively erase data written in the cell transistor in units of chips or blocks. Regarding memory.

In general, in a semiconductor memory device, since the production yield directly affects the production cost, it is important to improve the production yield. One method for improving the manufacturing yield is a redundancy technique. In flash memory,
Due to the operation, a column redundancy technique (replacement of a defective bit line with a redundant bit line) is generally employed.

[0003]

2. Description of the Related Art Conventionally, as a flash memory, FIG.
There are known those which show the main part. In the figure, 1
Is the original block that is used as it is if there is no defective cell, and 2 is a redundant block that is used in place of the column containing the defective cell when there is a defective cell in block 1.

[0004] 3 _0, 3 _1, 4 _0, 4 ₁ performs intrinsic cell transistors, 5 _0, 5 ₁ cell transistors for redundancy, 6 _0, 6 ₁ selected cell transistors Word lines, X ₀ and X ₁ are word line selection signals output from a row decoder (not shown) for decoding a row address.

Further, 7 ₀ and 7 _n are original bit lines, 7 _R
Is a bit line for redundancy, 8 ₀ and 8 _n are nMOS transistors which form an original column gate, 8 _R is an nMOS transistor which forms a column gate for a redundancy, Y ₀ and Y _n are original column selection signals, RED Is a redundant column selection signal, and 9 is a sense amplifier for amplifying read data.

[0006] Also, reference numeral 10 denotes an original cell of block 1.
Transistor 3 _0, 3 _1, ..., 4 _0, 4 ₁ ..., and the cell transistor 5 ₀ block 2 for redundancy, 5 ₁ source line provided in common to ..., 11 source lines 10 the cell transistor 3 ₀ via a 3 ₁ ..., 4 _0, 4 ₁ ...
- a source power supply circuit for supplying a source voltage to 5 _0, 5 _1,.

Here, the cell transistors 3 ₀ , 3 _1.
, 4 ₀ , 4 _1, ..., 5 ₀ , 5 _1, ... Are configured as shown in FIG. In the figure, P 12 ^- -type silicon substrate, 13 is a drain made of N ⁺ diffusion layer, the source 14 is composed of N ⁺ diffusion layer, 15 a floating gate, 16 a control gate, V _G is the control gate voltage, V _D the drain voltage, V _S is the source voltage.

In such a cell transistor, at the time of writing, for example, V _G = 12 [V], V _D = 6 [V], V _S =
0 [V], electrons are injected from the drain 13 into the floating gate 15, and at the time of reading, for example, V _G =
5 [V], V _D = 1 [V], and V _S = 0 [V]. At the time of erasing, for example, V _G = 0 [V], V _D = open,
V _S = 12 [V], and electrons are extracted from the floating gate 15 to the source 14.

In such a conventional flash memory, the cell transistors 3 ₀ , 3 ₁ of the original block 1 are used.
.., 4 ₀ , 4 ₁ ... And the cell transistors 5 ₀ , 5 _1.
It is configured so as to share the cell transistor 3 _0, 3 _1, ..., 4 _0, 4 ₁ and ... of the data, the data of the cell transistors 5 _0, 5 ₁ ... Bulk Will be erased.

[0010]

As described above, the common source line 10 is provided for the original block 1 and the redundant block 2, and the original block 1 and the redundant block 2 are collectively provided. According to the configuration of the conventional flash memory as a unit of erasing, the original block 1 is further partitioned in response to a user's request, and a source line is provided for each of the partitioned blocks. If batch erasing can be performed for each block, redundant blocks that are not necessarily required for each of the partitioned blocks are provided with a common source line for each of the partitioned blocks, and the chip area is reduced. However, there is a problem that this causes an increase in

Further, for example, in the case of an output of 8 bits, that is, a so-called × 8 configuration, eight × 1
Although the original block of the configuration is necessary, according to the configuration of the conventional flash memory, a redundant block is provided for each of the eight original blocks of the × 1 configuration. There is a problem that the chip surface cannot be used effectively.

In view of the above, the present invention can increase the number of erase blocks to be collectively erased without increasing the chip area. Another object of the present invention is to provide a flash memory which can effectively utilize a chip surface and reduce the size of a chip when a multi-bit configuration is used.

[0013]

SUMMARY OF THE INVENTION A flash memory according to the present invention includes a plurality of erase blocks each including a plurality of original cell transistors having a common source line, and each of the plurality of erase blocks is collectively provided. In addition to a unit block for erasure, a plurality of redundant cell transistors are provided in common with the plurality of erase blocks and a plurality of redundant cell transistors are provided in common with the plurality of erase blocks. Is done.

[0014]

In the present invention, a plurality of erase blocks each including a plurality of cell transistors having a common source line are provided. A redundant block having a common source line is provided for each of the plurality of erase blocks. Instead, a plurality of redundant blocks including a plurality of redundant cell transistors using a common source line independent of the plurality of erase blocks is provided in common for the plurality of erase blocks.

Therefore, according to the present invention, the number of columns of redundant blocks can be reduced, and the number of erase blocks can be increased in response to a user's request without increasing the chip area. Even when the number of erase blocks is not increased, in the case of a multi-bit configuration, the number of columns of redundant blocks can be reduced, the chip surface can be effectively used, and the chip can be downsized.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2, taking a flash memory having a multi-bit output as an example.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. In the figure, reference numeral 17 denotes a row decoder to which a row address is input, and 18 denotes a column decoder to which a column address, a redundant cell selection signal and a test cell selection signal are input.

Reference numeral 19 denotes a × 8 block in which original cell transistors are arranged, reference numeral 20 denotes a redundant block in which redundant cell transistors are arranged, and reference numeral 21 denotes a test cell transistor. This is the tested block.

Reference numerals 22 ₀ and 22 _m denote source power circuits of the block 19, 23 denotes a source power circuit of the redundant block 20, and 24 denotes a source power circuit of the test block 21.

FIG. 2 is a circuit diagram showing a part of the original block 19 and a part of the redundant block 20. In the drawing, reference numeral 27 denotes one of the blocks of the × 1 configuration, 28 ₀ , 28 _m is an erase block.

Also, 29 ₀ , 29 ₁ , 30 ₀ , 30 ₁ , 31
_0, 31 _1, 32 _0, 32 ₁ intrinsic cell transistors, 33 _0, 33 ₁ cell transistors for redundancy, 34
₀ , 34 ₁ are word lines for selecting cell transistors,
X ₀ and X ₁ are word line selection signals.

Also, 35 ₀ , 35 _a , 35 _b , and 35 _n are original bit lines, 36 _R is a redundant bit line, and 37 ₀ , 37
_a, 37 _b, 37 _n forms an inherent column gate nMO
S transistor, 38 _{R an} nMOS transistor serving as a redundant column gate, Y ₀ , Y _n an original column select signal, RED a redundant column select signal, 39 a sense amplifier for amplifying read data, 40 ₀ , 40 _m , 40
_R is a source line.

In this embodiment, the block 27
The, m + 1 having a separate source line 40 ₀ ··· 40 _m
Since the partitioning into individual erase block 28 ₀ ··· 28 _m, it is possible to batch-erase the erase block 28 ₀ ··· 28 _m units. In this case, in this embodiment,
The batch erasure of the redundant block 20 is performed simultaneously with the batch erasure of the erase block including the redundant column.

[0024] Thus, according to the present embodiment, although classified originally block 27 to erase the block 28 ₀ · · · 28 _m, these segmented erase block 28 ₀
.., 28 _m are not provided with redundant blocks using a common source line, and erase blocks 28 _0.
8 Since _m and is provided in common to block 20 for redundancy made with separate independent source line 40 _R in the erase block 28 ₀ · · · 28 _m, reducing the number of column blocks for redundancy, for example, To provide one redundant column,
It is possible to prevent the chip area from increasing.

When the configuration of the present embodiment is applied, even when the number of erase blocks is not increased, each of the original x1 configuration blocks and the redundant When the source line is provided independently, the number of columns of the redundant block is reduced as compared with the case where a redundant block is provided for each of the original x1 configuration blocks. By providing one redundant column, the chip surface can be used effectively and the chip can be reduced in size.

[0026]

As described above, according to the present invention, a plurality of erase blocks including a plurality of cell transistors having a common source line are provided. Each of the plurality of erase blocks has a source line. Is not provided, and a plurality of redundant blocks having a source line independent of the plurality of erase blocks are provided in common for the plurality of erase blocks. And without increasing the chip area,
The number of erase blocks can be increased, and even when the number of erase blocks is not increased, in the case of a multi-bit configuration, the number of columns of redundant blocks is reduced, and the chip surface is effectively used. Thus, the size of the chip can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a block having a × 8 configuration and a redundant block;

FIG. 3 is a circuit diagram showing a main part of a conventional flash memory.

FIG. 4 is a schematic sectional view of a cell transistor.

[Explanation of symbols]

19 × 8 configuration block 20 Redundancy block 21 Test block 22 ₀ , 22 _m , 23, 24 Source power supply circuit

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising a plurality of original cell transistors having a common source line , each of which is a single cell erase unit.
Position a plurality of erase blocks is a block, the plurality of erase blocks and a separate independent cell transistors for a plurality of redundant source line formed by a common Tona
The redundant block commonly provided in the plurality of erase blocks.
A flash memory having redundant blocks , wherein the batch erasing of the redundant blocks includes redundant columns.
A flash memory, which is performed simultaneously with batch erasure of the erase block .