KR19980077451A - Nonvolatile Semiconductor Memory Devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, comprising: a primary array area for storing data, a redundancy array area for replacing defective cells in the main array area, and address mapping and bad sectors associated with the main array area. The main array region and the redundant field array region of the nonvolatile semiconductor memory device having a redundant field array region for storing information are formed on impurity regions separated from each other.

Description

Nonvolatile Semiconductor Memory Device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device capable of rewriting data.

In general, a cell array of flash memory, which is a nonvolatile semiconductor memory device, is, as is well known, largely three regions, that is, a main array and a redundancy array and a redundant field array. The primary array is an area for storing normal data, and the redundant array is disposed in relation to the primary array to serve as a replacement for defective cells in the primary array. As shown in Fig. 1, the main array and the redundancy array correspond to a plurality of memory sectors for storing the main data, that is, the main field array 10. The redundant field array corresponds to each of the memory sectors. Information about, for example, a bad sector, an address for a data format of a corresponding memory device. Mapping an area 12 to store device data, such as (address mapping) information, it is typically provided by a word of 16 bytes per line.

FIG. 2 is a circuit diagram illustrating a circuit of a main array region and a redundant field array region of the cell array region of FIG. 1 according to the prior art.

Referring to FIG. 2, the cell array area 14 includes a plurality of array blocks BLK0 to BLKi and block decoders corresponding to the blocks BLK0 to BLKi. block decoders DEC0 to DECi and a charge pumping circuit 16. The array blocks BLK0 to BLKi have a plurality of strings, a plurality of word lines extending in the row direction, and a plurality of bit lines corresponding to the strings and extending in the column direction, respectively. Each of the strings has a string selection transistor (SST) having a drain connected to a corresponding bit line and a ground selection transistor (GST) having a source connected to ground, and the string selection transistor ( There are a plurality of memory cells MC0 to MCn in which current paths are formed in series between the source of SST and the drain of the ground select transistor GST.

Gates of the string select transistor SST, the memory cells MC0 through MCn, and the ground select transistor GST in the array blocks BLK0 through BLKi are block decoder circuits DEC0. String select line SSL, row select lines S0 through Sn controlled through transfer transistors T0 through Ti connected to block select lines BSL0 through BSLi connected to DECi. ) And ground select line (GSL), respectively. As shown in FIG. 2, the main array region 10 and redundant field array region 12 of FIG. 1 are formed on the same substrate. The charge pump circuit 16 is for applying an erase voltage to a substrate on which the main array region 10 and the redundant field array region 12 are formed during an erase operation.

FIG. 3 is a cross-sectional view of the cell array region of FIG. 2 cut in a 3a-3b direction. FIG.

As described above, the conventional NAND type flash memory erase operation of a predetermined size of the array block consisting of the main array region 10 and the redundant field array region 12 of a predetermined size (hereinafter, Block erasure). Assume that the block BLK0 is selected among the array blocks BLK0 to BLKi of FIG. 2 and the remaining array blocks BLK1 to BLKi are not selected. When the block erase operation is started, a predetermined erase voltage (for example, 20 volts) is applied to the substrates of the memory cells, and the string select line SSL and the row select lines S0 to Sn and the ground select line are applied. Apply 0V on each (GSL). Under these conditions, the block selection lines BSL1 to BSLLi connected to the unselected array blocks BLK1 to BLKi are memory in the unselected array blocks BLK1 to BLKi because 0V is applied. The voltages of the gates of the cells are in a floating state and are coupled up by the erase voltage applied to the substrate.

Thus, the memory cells of the unselected blocks BLK1 to BLKi do not generate electron emission from its floating gate to the substrate and remain in the previous state. On the other hand, since the selected array block BLK0 is supplied with a power supply voltage from the associated block decoder DEC0 to the block select line BSL0, 0V is applied to the gates of the memory cells of the selected array block BLK0. As a result, electron emission occurs from the floating gates of the memory cells to the substrate, resulting in an erased state where their threshold voltage is negative. However, a problem arises in that all the information such as sector and address mapping related to the main array region 10 stored in the redundant field array region 12 formed on the same substrate as the main array region 10 is erased.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of retaining information stored in a redundant field array area when data stored in the main array area is erased during a block erase operation.

1 is a schematic diagram of a cell array region of a nonvolatile semiconductor memory device;

FIG. 2 is a circuit diagram showing circuitry of the primary array region and redundant field array region of FIG. 1 according to the prior art; FIG.

FIG. 3 is a cross-sectional view of the cell array region of FIG. 2 cut in a 3a-3b direction; FIG.

4 is a circuit diagram showing a circuit of a main array region and a redundant field array region according to the present invention;

FIG. 5 is a cross-sectional view of the cell array region of FIG. 4 cut in a 5a-5b direction; FIG.

FIG. 6 is a cross-sectional view of the cell array region of FIG. 4 taken in the direction of 6a-6b; FIG.

* Explanation of symbols on the main parts of the drawings

10: main array area 12: redundant field array area

14: cell array area

According to one aspect of the present invention for achieving the above object, a main array area for storing data, a redundancy array area for replacing defective cells in the main array area, and associated with the main array area A nonvolatile semiconductor memory device having a redundant field array region for storing information such as address mapping and bad sectors, wherein the main array region and the redundant field array region are formed on impurity regions separated from each other. It is done.

In this embodiment, during the erase operation related to the data stored in the main array region, an erase voltage of a predetermined level is applied to the impurity region corresponding to the main array region and the impurity region corresponding to the redundant field array region is floated. It features.

By such an apparatus, the main array region and the redundant field array region can be formed on different substrates.

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 6 according to an embodiment of the present invention.

Referring to FIG. 4, a novel nonvolatile semiconductor memory device according to an embodiment of the present invention includes a main array region 10 for storing data, address mapping information and bad sector information related to the main array region 10, and the like. Redundant field array regions 12 were formed on different impurity regions, that is, separate well regions. As a result, data stored in the redundant field array area 12 corresponding to the main array area 10 may be prevented from being erased during a block erase operation for erasing data in the main array area 10.

4 is a circuit diagram of a main array region and a redundant field array region according to a preferred embodiment of the present invention.

Referring to FIG. 4, a nonvolatile semiconductor memory device, that is, a NAND flash memory device according to the present invention, has a main array region 10 for storing data and a redundancy for storing information related to the main array region 10. Field array area 12. The main array region 10 and the redundant field array region 12 are divided into a plurality of blocks BLK0 to BLKi in the column direction, and the main array region 10 and the redundant field array region ( 12 is formed on separate substrates, that is, separate well regions. The main array region 10, the redundant field array region 12, and the block decoder circuits DEC0 to DECi are the same as those in FIG. Therefore, in order to avoid duplication of description, detailed description thereof is omitted here.

In order to supply erase voltages to the substrates of the main array region 10 and the redundant field array region 12 respectively in a block erase operation, the regions 10 and 12 are charged with a charge pump circuit 16. Switch pump circuits 18A and 18B, respectively, for applying the high voltage supplied from the corresponding substrates. As a result, an erase voltage of about 20 volts is applied to the substrate corresponding to the main array region 10 during the block erase operation, and the substrate of the redundant field array region 12 is kept in a floating state. Thus, when erasing data in the main array region 10 during the block erase operation, it is possible to prevent the corresponding redundant field array region 12 from being erased.

FIG. 5 is a cross-sectional view of one of the strings in the cell array region of FIG. 4 in the 5a-5b direction, between the P-type semiconductor substrate and the well regions A-WELL and B-WELL. An N-WELL region is formed. The well region A-WELL represents the substrate of the main array region 10 of FIG. 4, and the well region B-WELL represents the substrate of the redundant field array region 12 of FIG. 4. Each string formed on the well regions A-WELL and B-WELL includes the string select transistor SST, the memory cells MC0 to MCn, and the ground select transistor GST as described above. It consists of. The drain region of the string select transistor SST is connected to the bit line BL and the impurity regions are sequentially formed in series at a predetermined interval between the source region of the transistor SST and the drain region of the ground select transistor GST. (Source region or drain region) are formed, and each source and drain region is commonly used by adjacent transistors.

FIG. 6 is a cutout of one of the word lines of the array blocks of FIG. 4 in the direction of 6a-6b, wherein the substrate corresponding to the main array region 10, that is, the well A-WELL and the redundant field array region 12 is shown in FIG. The substrate corresponding to the (), that is, the well (B-WELL) is a field oxide film (OX) for separating the two regions 10 and 12 on the N-well region formed on the P-type semiconductor substrate It is formed with). Memory cells connected on the same word line are formed on the well regions A-WELL and B-WELL with the oxide layer OX interposed therebetween.

As described above, the main array to which the erase voltage is applied during the block erase operation by separating the main array region 10 having the memory cells representing the density of the device and the substrates of the redundant field array region 12 which are redundantly supported. By driving the substrate of the region 10 and the redundant field array region 12 differently from each other, it is possible to prevent unnecessary erase operations of the redundant field array region 12 from being performed.

As described above, by forming a main array area for storing data and a redundant field array area for storing information related to the main array area on a separate substrate, information of the redundant field array area is erased during a block erase operation. Can be prevented.

Claims (2)

A main array area for storing data, a redundancy array area for replacing defective cells in the main array area, and a redundant field array area for storing information such as address mapping and bad sectors related to the main array area; A nonvolatile semiconductor memory device having a And the main array region and the redundant field array region are formed on impurity regions separated from each other. The method of claim 1, A nonvolatile semiconductor, wherein an erase voltage having a predetermined level is applied to an impurity region corresponding to the main array region and an impurity region corresponding to the redundant field array region is floated during an erase operation relating to data stored in the main array region Memory device.