JPH11251462A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the cost reduction per memory capacity by providing nonvolatile memory cells between bit lines and source lines and conductive gates via an oxide film on the source lines to reduce the area per bit. SOLUTION: P-type well regions 11 are formed on an n-type semiconductor substrate 10, and an NAND cell composed of eight memory cells is disposed on the p-type well region 11. Each memory cell constitutes a laminate structure of a floating gate 15, a second gate insulation film 16 and control gate 17 through a first insulation film (tunnel oxide film) 14, adjacent cells of the series arranged memory cells commonly have an n-type diffused layer as source-drains, the control gate 17 functions as a common word line in the row direction, and a drain side selective gate 18D is disposed at one end of the NAND cell via an n-type diffused layer. At the other end a source region 13T exists, and a conductive gate 22 is disposed on the source region 13T.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art NAND type E, a kind of EEPROM, is used.
The EPROM has a cell structure in which a diffusion layer between a plurality of memory cells is shared by each adjacent memory cell, and a cell array (hereinafter, referred to as a NAND cell) directly connected is provided at both ends of the NAND cell via the diffusion layer. And a select gate transistor.

The above structure is shown in FIG. 4 and FIG. FIG. 4 shows a conventional NAND-type EEPROM.
FIG. 5A is a plan view and FIG.
4A is a cross-sectional view taken along the line AA of FIG. 4 and FIG.

Each of the memory cells (MS1 to MS8) is an FET comprising a stack of a floating gate (charge storage layer) and a control gate.
It has a MOS structure and is formed, for example, on a p-type well region 11 formed on an n-type semiconductor substrate 10. The source / drain of each cell is shared by the n-type diffusion layer 13M between adjacent memory cells. The NAND cell is connected to the bit line 20 via a drain-side selection gate 18D, and connected to an n-type source diffusion layer 13S (hereinafter referred to as a source line) which is a common potential wiring via a source-line-side selection gate 18S. You.

Since the source line 13S and the drain diffusion layer 13D are conductive as described above, the electrical isolation between these diffusion layers and the NAND cells is made by the source side select gates 18S, respectively.
And the drain side select gate 18D is controlled.

Hereinafter, a NAND type EEPROM having the above structure will be described.
4 will be described with reference to an example of the applied bias in each operation shown in FIG. 6 in addition to FIGS. The data erasing operation is performed in units of one block: (memory cells connected to a word line connected to the control gate 17) × (one NAND cell)
Is performed in the row × column area of the memory cells connected in series in (1) or in a chip unit. The control gate 17 of the memory cell is set to 0 V, and the selection gates (18D, 18S),
A high voltage (Vee: about 20 V) is applied to the bit line 20, the source line 13S, the p-type well region 11, and the n-type semiconductor substrate 10. Then, the charge of the floating gate 15 is released to the substrate, and the threshold value shifts in the negative direction.

In a data write operation, first, a high voltage (Vpp: 20) is applied to the control gate 17 of the selected memory cell.
V) and the intermediate potential (V) is applied to the control gate 17 and the drain-side selection gate 18D of the other memory cells.
m: about 10 V). In this state, bit line 2
When 0 V is applied to 0, charges are injected from the semiconductor substrate into the floating gate 15 of the selected memory cell.
Therefore, the threshold value of this cell shifts in the positive direction (here, this state is set to “0”). Also, the bit line 20
When the intermediate potential is applied, no charge injection occurs, so that the threshold value does not change (here, this state is set to "1").

In the data reading operation, the control gate 17 of the selected memory cell is set to 0 V and the selection gate (18
D, 18S) and control gate 1 of unselected memory cell
7 is set to, for example, a power supply voltage (Vcc: 5 V), thereby detecting whether or not a current flows in the selected memory cell array.

The role of the two select gates disposed at both ends of the NAND cell is to prevent erroneous writing and erroneous reading. That is, the source-side selection gate 18S is set to 0 V at the time of writing, the drain portion (0 V for the selected NAND cell, the intermediate potential Vm for the non-selected NAND cell),
The source part (0 V) is electrically separated. At the time of reading, it is necessary to apply, for example, a power supply voltage (Vcc: 5 V) to the drain-side selection gate 18D and the source-side selection gate 18S to keep the bit line portion and the source line portion conductive.

As described above, the conventional NAND type EEPROM is used.
In the M cell structure, select gates are provided on both sides of each cell array, and electric control between each cell array and the diffusion layer is performed by a voltage applied to the select gate. Since the two source line side select gates 18S sandwiching the source line 13S are the same node, they have the same potential setting.

[0011]

As described above, the conventional NA
The cell structure of the ND type EEPROM can reduce the number of contacts per cell as compared with a conventional NOR type memory in which a bit line contact is provided for every two cells, for example. Specifically, for example, in a NAND cell in which eight memory cells (8 bits) are connected in series, the number of contacts is one for 16 bits. Therefore, there is an advantage that the area per bit can be reduced. However, when the number of NAND cells connected in series is large, the area occupied by the select gates decreases in relative area occupancy, but when the number of NAND cells is small, the area of the select gates per cell increases, and Was hindered.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the area per bit and reducing the cost per memory capacity in order to solve the above problems.

[0013]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has the following configuration. That is, the nonvolatile semiconductor memory device according to claim 1 has a nonvolatile memory cell provided between a bit line and a source line, and a conductive gate provided on the source line via an oxide film. It is.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device, the source line is used as a conductive layer by applying a voltage to the conductive gate. In the nonvolatile semiconductor memory device according to claim 3, the memory cell includes: a control gate provided on a semiconductor substrate;
The semiconductor device comprises a charge storage layer provided between the control gate and the semiconductor substrate, and electrical rewriting is performed by transferring charges between the charge storage layer and the semiconductor substrate.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
3 will be described. FIGS. 1 (a) and 1 (b) show the NA in a NAND type EEPROM according to an embodiment of the present invention.
1 is a plan view and an equivalent circuit diagram of the ND cell portion, and FIG. 2 is a cross-sectional view taken along lines AA, BB, and CC in FIG. In each case, only one NAND cell portion is shown. In this example,
A p-type well region 11 is formed in an n-type semiconductor substrate 10, and an N memory cell including eight memory cells is formed in the p-type well region 11.
An AND cell is provided. Each memory cell has a first
It has a laminated structure of a floating gate 15, a second gate insulating film 16, and a control gate 17 via a gate insulating film (tunnel oxide film). The memory cells (MS1 to MS8) arranged in series share an n-type diffusion layer as a source / drain between adjacent ones. The control gate functions as a common word line in the row direction. A drain-side select gate 18D is provided at one end of the NAND cell via an n-type diffusion layer, and a source region 13T exists at the other end of the NAND cell.
A conductive gate 22 is disposed on T. These two
One gate is the control gate 17 of the memory cell in this example.
And at the same time, each gate and the semiconductor substrate 1
The third gate insulating film 21 existing between the first gate insulating film 21 and the 0 surface is formed simultaneously with the first gate insulating film 14 of the memory cell.

An n-type diffusion layer 13M is formed between the conductive gate 22 and the control gates 17 provided on both sides of the conductive gate 22, and the source region 1 under the conductive gate 22 is formed.
No diffusion layer is formed in 3T. Source region 13T
Is inverted when a voltage is applied to the conductive gate 22, and becomes a conductive layer by the applied voltage. When no voltage is applied, the source region and the NAND cell portion are insulated.

A bit line 20 is provided between these elements and the interlayer insulating film 19. The bit line 20 is in contact with the drain diffusion layer 13D located between two adjacent drain-side select gates 18D.

Next, a NAND type EEPROM having the above structure is described.
3 will be described with reference to an example of the applied bias in each operation shown in FIG. 3 in addition to FIGS. The data erasing operation is performed by setting the control gate 17 of the memory cell to 0 V, selecting the select gate (18D), the bit line 20, and the conductive gate 2.
2. A high voltage (about 20 V) is applied to the p-type well region 11 and the n-type semiconductor substrate 10. Then, floating gate 1
The charge of No. 5 is released to the substrate, and the threshold value shifts in the negative direction, thereby converting the data into "1" (depletion).

In the data writing operation, the conductive gate 22 is set to 0 V (GND), first, a high voltage (Vpp: about 20 V) is applied to the control gate 17 of the selected memory cell, and the other memory cells are An intermediate potential (Vm: about 10 V) is applied to the control gate 17 and the drain-side selection gate 18D. In this state, when 0 V is applied to the bit line 20, charges are injected from the semiconductor substrate into the floating gate 15 of the memory cell selected by the potential difference from Vpp. Therefore, the threshold value of this cell shifts in the positive direction (here, this state is set to “0”). When an intermediate potential is applied to the bit line 20, the electric field applied to the tunnel oxide film is relaxed and no charge injection occurs, so that the threshold value does not change (here, this state is set to "1"). .

In the data reading operation, the control gate 17 of the selected memory cell is set to 0 V, and the control gate 17, the conductive gate 22, and the drain-side selection gate (18D) of the unselected memory cell are set to, for example, the power supply voltage (Vcc). : 5
V), the detection is performed by detecting whether or not a current flows in the selected memory cell array. That is, current flows when the memory cell is depleted, and does not flow when the threshold value is positive.

In each of the above operations, the source region 13T
By controlling the voltage applied to the conductive gate 22 formed above via the third gate insulating film, both the function of the conductive source diffusion layer and the function of the source side select gate in the prior art are controlled. Cover. As a result, the source-side selection gate 18S can be omitted.

In the above embodiment, the conductive gate is formed in the same structure as the memory cell and the drain side select gate. However, the present invention is not limited to this. Is also good.

Further, various structures, materials, impurity concentrations, voltage setting values, and the like can be changed within the scope of the present invention. For example, in the above-described embodiment, the gate insulating film below the select gate or the conductive gate may be made thicker than that of the memory cell portion, or the ONO film (a stacked layer of a silicon oxide film and a silicon nitride film) may be used. The application of a film such as an insulating film) can be arbitrarily selected individually. Further, for example, the semiconductor substrate and each diffusion layer are not limited to the above-described combination of the p-type and the n-type, and other conductive types can be set.

[0024]

As described above, according to the present invention, two source line-side select gates adjacent to a source line, which have been conventionally required, are replaced with one conductive gate on the source region. Therefore, the required occupation area is reduced. As a result, the area per bit can be reduced, and the cost per memory capacity can be reduced.

[Brief description of the drawings]

FIG. 1 shows a NAND-type EEPROM according to an embodiment of the present invention.
2A and 2B are a plan view and an equivalent circuit diagram of a NAND cell unit in the OM.

FIG. 2 is a sectional view taken along lines AA, BB, and CC of FIG. 1;

FIG. 3 shows an applied bias at each operation in a NAND-type EEPROM according to a conventional example.

FIG. 4 is a plan view and an equivalent circuit diagram of a NAND cell section in a NAND type EEPROM according to a conventional example.

FIG. 5 is a sectional view taken along line AA and BB of FIG. 4;

FIG. 6 shows an applied bias at each operation in the NAND type EEPROM according to the present invention.

[Explanation of symbols]

 10: semiconductor substrate 11: p-type well region 12: element isolation oxide film (field oxide film) 13M: diffusion layer 13D: drain diffusion layer 13S: source diffusion layer (source line) 13T: source region 14: first gate oxide film (Tunnel oxide film) 15: Floating gate (charge storage layer) 16: Second gate oxide film 17: Control gate 18D: Drain side select gate 18S: Source side select gate 19: Interlayer insulating film 20: Bit line 21: Third Gate oxide film 22: Conductive gate

Claims (3)

[Claims] 1. A nonvolatile semiconductor memory device comprising: a nonvolatile memory cell provided between a bit line and a source line; and a conductive gate provided on the source line via an oxide film. . 2. The nonvolatile semiconductor memory device according to claim 1, wherein a voltage is applied to said conductive gate to make said source line a conductive layer. 3. The memory cell comprises: a control gate provided on a semiconductor substrate; and a charge storage layer provided between the control gate and the semiconductor substrate. 3. The non-volatile semiconductor memory device according to claim 1, wherein electrical rewriting is performed by transfer of electric charge during the period.