JP2573271B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a charge storage layer and a control gate.

(Prior Art) In the field of EPROM, an ultraviolet erasing nonvolatile memory device using a memory cell having a MOSFET structure having a floating gate as a charge storage layer is widely known. A component which enables an electrical erasure in EPROM is known as E ² PROM. A memory array of this type of EPROM is configured by arranging a memory cell at each intersection of a row line and a column line that cross each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

On the other hand, recently, an EPROM has been proposed in which memory cells are connected in series to constitute a NAND cell as a cell unit, and the number of contacts can be significantly reduced.

As a configuration of such a NAND cell, a configuration in which a first selection MOS transistor is disposed on the drain side of the NAND cell and a second selection NOS transistor is disposed on the source side of the NAND cell and connected to the bit line and the ground potential is adopted. It is common to take.

(Problems to be Solved by the Invention) However, in order to increase the capacity, higher integration is desired.

An object of the present invention is to provide a nonvolatile semiconductor memory device which solves such a problem.

[Configuration of the invention]

(Means for Solving the Problems) According to the present invention, in the first and second select gate transistors of the NAND cell described above, the channel length of the second transistor on the source side is changed by the channel length of the first transistor on the drain side. It is characterized by being shorter than the channel length.

(Operation) In the present invention, since the channel length of the source-side second transistor can be reduced, the area of the memory cell region can be reduced, and the chip area can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

NAND cells are arranged in a matrix as shown in FIG. As for one of the NAND cells along the bit line BL _1, the drain of the memory cell M ₁ at one end of the therein is selected
It is connected via the MOS transistor SD to the bit line BL _1, the source of the memory cell M ₄ of the other end connected to the ground potential via the selection MOS transistor SS. The same applies to other bit lines. Control lines CG ₁ , CG ₂ ,... Commonly connecting the control gates of the memory cells in a direction orthogonal to the bit lines are provided as word lines WL ₁ , WL ₂ ,. Rows are commonly applied to adjacent NAND cells and blocks with contacts in the bit line direction. Output lines RD1 to RD4 are provided from the decoder. Further, block select lines SD1 and SD2 are provided. These are turned on and off by the PRO. First
FIG. 1A is a cross-sectional view of one NAND cell cut in the channel direction. Each memory cell has a source on a P-type Si substrate 1,
The adjacent n ⁺ type layer 2 serving as a drain is shared between adjacent ones,
The floating gate 3 and the control gate 4 are laminated by a two-layer polycrystalline silicon film in a self-aligned manner with a FAMOS structure. That is, the floating gate 3 is formed on the substrate 1 via the first gate insulating film made of a thermal oxide film, and the control gate 4 is formed thereon via the second gate insulating film. FIG. 1B is a cross-sectional view of the memory cell portion viewed in a direction orthogonal to the channel direction, and the floating gate 3 extends to above the element isolation region. Thereby, the floating gate 3 and the substrate 1
The coupling capacitance between the floating gate 3 and the control gate 4 is set to be larger than the coupling capacitance between the floating gate 3 and the control gate 4, so that writing and erasing can be performed only by exchange of electrons by the tunnel effect between the floating gate 3 and the substrate 1.

Select gates SS and SD are formed by the first and second-layer polycrystalline silicon films. The first-layer and second-layer polycrystalline silicon films of the select gates SS and SD are connected to each other at predetermined intervals in the arrangement direction by through holes (not shown). The first gate insulating film of the memory cell portion is 100A, the select gate portion SS,
The first gate insulating film of the SD is a thermal oxide film having a thickness of 400A.
On the other hand, the second gate insulating film of the memory cell portion, the select gate portion
The second gate insulating films of SS and SD each have a silicon oxide film / silicon nitride film / silicon oxide film having a thickness of 250 A, that is, an OMO structure. Erasing operation Bit line potential (Vp) source potential Vs of the low potential (OV), "H" level gate SD1, SD2 of the select transistors SD, word lines _{(WL 1 ~WL 4) "H} " to the level Is carried out collectively by tunneling and injecting electrons from the substrate side through the gate insulating film 3 into the floating gate. The “H” level is, for example, 20V. Substrate potential is O
V. Gates SS1 and SS2 are OV. Next, the write operation is sequentially performed from a cell farther from the contact with the bit line, that is, a memory cell closer to the source. From the cell of M ₄
M ₃ , M ₂ , and M ₁ are sequentially written. First writing to the memory cell M _4, drain Vp = "H" of the select transistor SD or "L"
Level, gate SD1 = "H" level, SD2 = "L" level,
"H" level is applied to word lines WL ₁ , WL ₂ , WL ₃ . Gate SS
1, SS2 is "L" level, that is, OV. “H” level is, for example, 2
0V. At this time, Vp is transmitted to the drain region of the memory cell M ₄ through the channel of the selection transistor SD, memory cells _{M 1, M 2, M 3} . Since the word line WL ₄ connected to the gate of the memory cell M ₄ is at "L" level = OV, this time, the control gate in the memory M ₄ and large electric field between the substrates is applied. Coupling capacitance C ₁ between the floating gate 3 and the substrate 1, because the coupling capacitance C ₂ between the floating gate 3 control gate 4 is C _2> C _1, tunneling electrons in the floating gate 3 via a gate insulating film Is released to the substrate 1. In the memory cells M ₁ , M ₂ , and M ₃ , such a high voltage is applied to the control gate and the substrate, so that such electron emission does not occur. Thus, the threshold voltage of the memory cell M ₄ is negative, the data is written. Continue SD
1 and WL ₁ WL ₂ is maintained at “H” level and SD ₂ is maintained at “L” level.
₃ is set to the "L" level, data writing in the memory cell M ₃ is carried out on the same principle. Hereinafter, data writing of M ₂ and M ₁ is performed in the same manner. Since the gate SS1 source side is turned off, it never bit line and the source are short-circuited by even SS1 become write by becoming the threshold in the negative on-state of M _4. The read operation sets SD1 to “H” (= 5
V), ie, ON, SD2 is set to “L” (= OV), ie, OFF. The selected word lines WL _{1 to} WL ₄ are set to “O” = (OV), and 5 V for forcibly turning on the others. That only WL ₁ is, "O" memory cells M ₁ is selected when only the WL ₄ are "O" memory cell M ₄ is selected when the. For example, when WL ₁ is “O” and the memory cell M ₁
When There is selected, because it is _{WL 2 = WL 3 = WL 4} = "1", the memory cell M ₂ ~M ₄ is in the ON state. Memory cells M ₁ is a threshold positive state off, the negative state is on.
The gate SS1 is "H", that is, ON, and the SS2 is "L", that is, OFF.
Therefore, the cell. It determines whether or not current flows through the block. As a result, "1" or "O" is obtained at the Vp terminal.

The factors that determine the channel length of the select gates SD and SS are:
Punch-through pressure resistance.

The worst condition that must be considered for punch-through of the first select gate SD occurs at the next time. That is, a non-selected NAND cell at the time of writing (when electrons are removed from the floating gate) (when not selected, the gate of the first selection gate SD is
OV). At this time, the drain (bit line BL) of the first selection gate is Vpp (for example, 20 V), and the gate SD is O
V, the source (n ⁺ diffusion layer 2 ₁₎ are OV, it becomes the source, the drain side, the channel because it takes a high voltage of Vpp L is short and punch through occurs. When the current flowing through punch-through increases, the potential of the bit line decreases, causing a malfunction. Therefore, the select gate SD needs to have a sufficiently long channel length so as not to cause punch-through.

On the other hand, the second select gate SS has a source. There is no need to apply a high voltage between the drains to worry about punch-through. During collective erasure takes Vpp to the control gate CG ₁ ~CG ₄ (e.g. 20V), the gate SD1 SD and SS, SD2, SS1, but SS2 electrons are injected into the floating gate takes potential of Vpp to a second Selection gate
The source and drain of SS become OV and do not satisfy the condition for punch-through. When writing to the floating gate 3 ₄ to the control gate CG ₄ OV, a CG ₁ ~CG ₃ Vpp + Vth or more (e.g., 22V). At this time, the n ⁺ diffusion layer on the source side of the second select gate becomes Vss floating, and although the potential slightly increases after writing, the source. The potential difference is not so large as to cause punch-through between the drains. Therefore, the channel length of the second selection gate can be reduced.

In this embodiment, the channel length of the first selection gate SD is set to 1.8
μ, the channel length of the second selection gate SS was set to 1.0 μ.

〔The invention's effect〕

As described above, according to the present invention, the channel length of the second selection gate on the ground side of the NAND cell can be made shorter than the channel length of the first selection gate on the bit line side, and the area of the memory cell can be reduced. Can reduce the high density of EE
PROM can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of an EEPROM according to an embodiment of the present invention, and FIG. 2 is a view showing the structure of an array of memory cells. 1 ...... silicon substrate, 2, to 2 ₅ ...... n ⁺ -type layer, 3, and 3 ₄ ...... floating gate, 4 ...... control _{gate, M (M 1, M 2} , ...) ...... memory cell, BL (BL ₁ , BL ₂ …) bit line, WL (WL ₁ , WL ₂ ,…)… word line, CG (CG ₁ , CG ₂ ,…)… control gate terminal, SD… first selection gate , SS ... The second selection gate.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792 (72) Inventor Yoshihisa Iwata 1 Toshiba Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Within the Research Institute (72) Inventor Fujio Masukaoka 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Incorporated Toshiba Research Institute (72) Inventor Masahiko Chiba Komukai Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa 1 Toshiba Research Institute Office (72) Inventor Ryohei Kirisawa 1 Toshiba Research Institute, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Satoshi Inoue 1 Toshiba-cho, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Pref. 72) Inventor Ryozo Nakayama 1 Komukai Toshiba-cho, Saiyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Ltd.

Claims (2)

(57) [Claims] A cell unit in which a charge storage layer and a control gate are stacked on a semiconductor substrate and a plurality of rewritable memory cells are connected in series is arranged in a matrix, and a drain and a source of the cell unit are respectively It is connected to the bit line and the reference potential via the first and second selection MOS transistors, and the channel length of the second selection transistor on the source side is shorter than the channel length of the first selection transistor on the drain side. A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. The nonvolatile semiconductor memory device according to claim 1, wherein writing is performed from a side far from the bit line.