JP2966363B2 - Memory cell array in nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a nonvolatile semiconductor memory device.
Regarding a memory cell array , in particular, in a flash memory cell having a gate electrode of a stack structure, one bit line contact is shared by four unit cells, so that a non-volatile memory can be reduced in chip size . The present invention relates to a memory cell array in a semiconductor memory device .

[0002] Generally, an electrical program (progr) is used.
am) and non-volatile with erasure function
The semiconductor memory device has a peripheral circuit and a memory cell array (Me).
(Money Cell Array).

A memory cell array in the nonvolatile semiconductor memory device includes a plurality of memory cells each selected by a word line signal and a bit line signal.
The information is stored in the memory cell. A program operation for storing information in the memory cell is performed by a floating gate (floating gate) of the memory cell.
The erase operation for erasing the stored information is performed by discharging the electrons injected into the floating gate. Further, the memory cell has a gate electrode having a stacked or split structure.

A memory cell array and a programming method using the same in a nonvolatile semiconductor memory device having memory cells having a gate electrode of a laminated structure will be described as follows with reference to FIGS. 1 and 2. FIG. 1 shows a conventional nonvolatile semiconductor device.
FIG. 2 is a circuit diagram of a memory cell array in a conductor memory device , and FIG. 2 is a layout of a memory cell array in a conventional nonvolatile semiconductor memory device .

The first to Nth bit lines (BL1 to B)
LN) and first to Mth word lines (WL1 to WL)
M) cross each other, and gate electrodes of a plurality of memory cells are connected to each of the first to Mth word lines (WL1 to WLM). Also, drains of two adjacent memory cells are commonly connected to each of the first to Nth bit lines (BL1 to BLN), and the source electrodes of the two memory cells are connected to the first to Nth bit lines (BL1 to BLN). It is configured to be connected to first to Kth source lines (S1 to SLK) parallel to the Nth bit lines (BL1 to BLN). Thus, the conventional nonvolatile semiconductor memory
Since the memory cell array in the device has a configuration in which one bit line contact is shared by two unit cells, there is a limit in reducing the chip size.

[0006] The nonvolatile semiconductor memory constructed as described above.
A programming method using a memory cell array in the device will be described as follows. For example, when programming the memory cell (MCA) shown in FIG. 1, a program bias voltage (bias) is applied to the second word line (WL2), the second bit line (BL2) and the second source line (SL2). voltage) is applied. However, the nonvolatile semiconductor memory device configured as described above
Memory cell array drains of two memory cells are commonly connected at said commonly connected drain is one of the con tact hole (contact hole)
The size of the element is determined by the area size and the contact hole of the contact hole is occupied to be connected to the bit lines was made form a metal (metal) through. In order to reduce the number of the contact holes, as shown in FIG. 2, a common source line formed by using the sources of two memory cells adjacent to the first to Nth bit lines (BL1 to BLN) as diffusion layers. (CSL). However, in this case, a program bias voltage is applied to the second word line (WL2), the second bit line (BL2) and the common source line (CSL) to program the memory cell (MCA) shown in FIG. When the voltage is applied, a drain is commonly connected to the second bit line (BL2), and the memory cell (MCA) and the memory cell (MCB) are programmed together. Therefore, in order to program only the memory cell (MCA), it is necessary to use a select gate transistor (not shown) to selectively apply a bias voltage only to the source of the memory cell (MCA). No. There is a disadvantage in that the area of the device is increased due to the addition of the above-described select gate transistor and a decoder circuit for driving the select gate transistor, so that the device cannot be efficiently used for integration of the device.

Accordingly, the present invention can solve the above-mentioned disadvantage by selectively applying the program bias voltage to the even-numbered and odd-numbered source lines by the first and second decoders . Semiconduct
It is an object to provide a memory cell array in a body memory device .

Another object of the present invention is to provide a memory cell array in a nonvolatile semiconductor memory device in which one bit line contact can be shared by four unit cells to reduce the chip size. It is in.

In order to achieve the above object, a memory cell array in a nonvolatile semiconductor memory device according to the present invention comprises: a number of word lines; a number of bit lines intersecting with the number of word lines; A bias voltage is applied to each of a plurality of source lines located one by one between the plurality of source lines and parallel to the bit line, and to each of the source lines located on the negative side of each of the plurality of bit lines among the plurality of source lines. And a second decoder for applying a bias voltage to each of the source lines located on the other side of each of the plurality of bit lines among the plurality of source lines. It is characterized by becoming.

Further, a memory cell array in the nonvolatile semiconductor memory device of the present invention is a combination of a unit cell composed of a floating gate, a control gate, a source and a drain on a semiconductor substrate, and the above four unit cells. The four unit cells are formed to connect the basic cell group configured to share the drain and a large number of the basic cell groups in the horizontal or vertical direction. A number of word lines, a number of bit lines intersecting with the number of word lines, a number of source lines located one by one between the number of bit lines and parallel to the bit lines, and the number of source lines Of each of the source lines located on the-side with respect to each of the plurality of bit lines. A first decoder for applying a bias voltage to each of the plurality of bit lines, and a second decoder for applying a bias voltage to each of the source lines located on the other side of the plurality of bit lines. Characterized by the following.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 3 shows a nonvolatile semiconductor according to the present invention.
FIG. 3 is a circuit diagram of a memory cell array in the storage device . The first to Nth bit lines (BL1 to BLN) and the first
The Mth to Mth word lines (WL1 to WLM) cross each other, and the first to Mth wordlines (WL1 to WL)
M) The gate electrodes of many memory cells are connected to each. Two adjacent memory cell drains are commonly connected to each of the first to Nth bit lines (BL1 to BLN), and the source electrodes of the two memory cells are respectively connected to the first to Nth bit lines. Line (BL1 to BL
N) are connected to the first to K-th source lines (SL1 to SLK) formed in the bonding layer in parallel. Further, the first, third,..., K-1 source lines (SL1,
SL3,. . . . . SLK-1) (where K is an even number).
ddDecoder; 1). The second, fourth,... K-th source lines (SL2, SL4,.
The same even number SLK) th saw Surain second decoder
(Even Decoder; 2).

[0012] The nonvolatile semiconductor memory configured as described above.
A programming method using a memory cell array in the device will be described as follows. For example, when programming the memory cell (MCC) shown in FIG. 3, a voltage (Vd) greater than 0 volts is applied to the second bit line (BL2).
d) is applied to the second word line (WL2).
A voltage (Vpp) greater than the voltage (Vdd) supplied to the bit line (BL2) and 0 volts are supplied to the second source line (SL2) from the second decoder (2). The output of the first decoder (1) is caused to float.

According to the present invention, there is provided a nonvolatile semiconductor device.
When configuring a memory cell array in a storage device , the word lines are active regions (active regions).
n), the thickness of the field oxide film can be reduced, and the process is simplified.

FIG. 4 shows a nonvolatile semiconductor memory according to the present invention.
FIG. 5 is a layout of a memory cell array in the device , and FIG. 5 is an enlarged view of a basic cell group in the memory cell array in the nonvolatile semiconductor memory device of FIG. 6A and 6B show X1-X1 and X in FIG.
2- Non-volatile semiconductor memory device cut along X2 line
Takes a cross-sectional view of the memory cell array, FIG. 7 is a nonvolatile semiconductor memory device cut in accordance with line X3-X3 of FIG. 5
It is a cross-sectional view of a memory cell array in. 8A and 8B are cross-sectional views of the memory cell array in the nonvolatile semiconductor memory device taken along lines X4-X4 and X5-X5 in FIG. 5, and FIGS. 9A and 9B are Y1 in FIG.
-Non- volatile semiconductor cut along Y1 and Y2-Y2 lines
FIG. 3 is a sectional view of a memory cell array in the storage device ,
FIG. 0 is a nonvolatile half cut along the line Y3-Y3 in FIG.
11A and 11B are cross-sectional views of a memory cell array in a conductor storage device . FIGS. 11A and 11B show a nonvolatile semiconductor storage device cut along lines Y4-Y4 and Y5-Y5 in FIG.
FIG. 2 is a cross-sectional view of a memory cell array in FIG.

In the nonvolatile semiconductor memory device of the present invention, the memory cell array has one bit line contact (2
2) with four unit cells (100, 200, 300 and 4)
00) to share the basic cell group (500)
And a large number of this basic cell group (500)
Connect.

In the basic cell group (500), the first unit cell (100) includes the first floating gate (1).
2A), a first control gate (18A), a first source (14A), and a common drain (13). The second unit cell (200) has a second floating gate (12B) and a second control gate (18B). ), A first source (14A) and a common drain (13). The third unit cell (300) includes a third floating gate (12C) and a first control gate (18).
A), second source (14B) and common drain (13)
And the fourth unit cell (400) includes a fourth floating gate (12D), a second control gate (18B), a second source (14B), and a common drain (13).

In the basic cell group (500), the first floating gate (12A) and the first floating gate (12B) are formed by a second field oxide film (21B).
The third floating gate (12C) and the fourth floating gate (12D) are vertically arranged on both sides of the third field oxide film (21C). Connect the basic cell group (500) in the vertical direction
In this case , the first field oxide film (21) is formed on the first and third floating gates (12A and 12C) to electrically isolate the adjacent basic cell groups (500).
A) is formed, and a fourth field oxide film (21) is formed on the second and fourth floating gates (12B to 12D).
A) is formed, and a fourth field oxide film (21) is formed on the second and fourth floating gates (12B and 12D).
D) is formed.

In the basic cell group (500), first and second floating gates (12A and 12B)
Share the first source (14A), and the third and fourth floating gates (12C and 12D) share the second source (1A).
4B) and the basic cell group (500) is connected in the vertical direction , the first source (14A) is connected to the first source.
The source line (SL1) is formed in the vertical direction, and the second source
The second source line (SL2) is formed by the connection of (14B)
Is done.

Each of the first, second, third and fourth floating gates (12A, 12B, 12C and 12D) is electrically separated from the semiconductor substrate (11) by a gate oxide film (17).

In the basic cell group (500), the first control gate (18A) is connected to the first source (14).
A) Partially, the first floating gate (12A), a part of the common drain (13), the third floating gate (12C) and a part of the second source (14B) are formed in a lateral direction so as to be covered. . The second control gate (18B) is a part of the first source (14A), a part of the second floating gate (12B), a part of the common drain (13), a part of the fourth floating gate (12D) and the second source (14B). It is formed in the lateral direction so that a part is covered. When connecting basic cell groups (500) in the horizontal direction
The first control gate (18A)
The memory cell line (WL1) is formed in the horizontal direction and the second controller
By connecting the roll gate (18B), the second word line (S
L2) is formed.

The first and second control gates (18A
And 18B) each of the first, second, third and fourth floating gates (12A, 12A, 12A) by a dielectric film (16).
B, 12C, and 12D) are electrically separated from each other, and are connected to the common drain (13) by the thermal oxide film (15).
The source (14A) and the second source (14B) are electrically separated from each other.

In the basic cell group (500), an interlayer insulating film (19) is formed on the entire structure including the first and second control gates (18A and 18B), and the common drain (13) is formed by a metal contact process. The wiring (20) is formed in the contact portion of ()). When connecting the basic cell group (500) in the vertical direction, the wiring (2
0) forms a first bit line (BL1),
The first bit line (BL1) electrically connects the common drain (13) of each basic cell group (500).

According to the above-described embodiment of the present invention, the memory cell array in the nonvolatile semiconductor memory device of the present invention has one bit line contact (22) and four unit cells (100, 200, 300 and 400). The basic cell group (500) is configured to be shared, and a large number of the basic cell groups (500) are connected in the horizontal or vertical direction.
It continued, and the first to K source line formed in the longitudinal direction (SL1 to SLK), and first through M word lines formed in the transverse direction (WL1 to WLM), which is formed in the vertical direction first Bit lines 1 to N (BL1 to BL
N). On the other hand, among the many source lines, odd-numbered source lines are connected to the first decoder, and even-numbered source lines are connected to the second decoder.

Therefore, the present invention can simplify the operation of the device by selectively applying the program bias voltage to the even-numbered and odd-numbered source lines by the first and second decoders, There is an effect that the chip size can be reduced by sharing one bit line contact with four unit cells.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory cell array in a conventional nonvolatile semiconductor memory device .

FIG. 2 is a layout of a memory cell array in a conventional nonvolatile semiconductor memory device .

FIG. 3 shows a nonvolatile semiconductor memory device according to the present invention.
Circuit diagram of kicking the memory cell array.

FIG. 4 shows a nonvolatile semiconductor memory device according to the present invention.
Kicking memory cell array layout.

FIG. 5 is an enlarged view of a basic cell group in a memory cell array in the nonvolatile semiconductor memory device of FIG. 4;

[6A] and

FIG. 6B is a cross-sectional view of the memory cell array in the nonvolatile semiconductor memory device cut along the lines X1-X1 and X2-X2 in FIG.

FIG. 7 is a non-volatile figure cut along the line X3-X3 in FIG.
Sectional view of a memory cell array in a semiconductor memory device .

[Eighth A] and

FIG. 8B is a cross-sectional view of the memory cell array in the nonvolatile semiconductor memory device taken along the line X4-X4 and X5-X5 in FIG.

9A and 9B show Y1-Y1 and Y2- in FIG.
Sectional drawing cut | disconnected according to the Y2 line.

[Figure 10] is not cut in accordance line Y3-Y3 of FIG. 5
FIG. 4 is a cross-sectional view of a memory cell array in a volatile semiconductor storage device .

[11A] and

11B is a cross-sectional view of the memory cell array in the nonvolatile semiconductor memory device cut along the lines Y4-Y4 and Y5-Y5 in FIG.

[Explanation of symbols]

1: first decoder 2: second decoder 11: semiconductor substrate 12A, 12B, 12C and 12D: first, second, third
And fourth floating gate 13: common drain 14A and 14B: first and second sources 15: thermal oxide film 16: dielectric film 17: gate oxide films 18 and 18B: first and second control gate 19: interlayer insulation Film 20: Wiring
g) 21A, 21B, 21C and 21D: first, second, third
And fourth field oxide film 22: contacts 100, 200, 300 and 400: first, second, third
And fourth unit cell 500: basic cell group WL1 to WLM: first to Mth word lines SL1 to SLK: first to Kth source lines BL1 to BLN: first to Nth bit lines

Claims (4)

(57) [Claims] In a memory cell array in a nonvolatile semiconductor memory device, a number of word lines, a number of bit lines intersecting with the number of word lines, and a plurality of bit lines are located one by one between the number of bit lines. A plurality of source lines parallel to the bit lines, and a first decoder for applying a bias voltage to each of the plurality of source lines located on the negative side of each of the plurality of bit lines. And a second decoder for applying a bias voltage to each of the source lines located on the other side with respect to each of the multiple bit lines among the multiple source lines. A memory cell array in a semiconductor memory device. 2. A memory cell array in a nonvolatile semiconductor memory device, comprising: a unit cell comprising a floating gate, a control gate, a source and a drain formed on a semiconductor substrate; The four unit cells are formed of a basic cell group configured to share the drain, and a plurality of words formed to connect the basic cell group in a horizontal or vertical direction. A plurality of bit lines intersecting the plurality of word lines, a plurality of source lines located one by one between the plurality of bit lines, and a plurality of source lines parallel to the bit lines; A bias voltage is applied to each of the source lines located on the negative side with respect to each of the multiple bit lines. A first decoder for applying a bias voltage, and a second decoder for applying a bias voltage to each of the source lines located on the other side of each of the multiple bit lines among the multiple source lines. A memory cell array in a nonvolatile semiconductor memory device, characterized by: 3. A basic cell group in a memory cell array in a nonvolatile semiconductor memory device, wherein a first, second, third and fourth unit cell shares one bit line contact. A number of word lines formed so as to connect a plurality of cell groups in the horizontal or vertical direction, a number of bit lines intersecting with the number of word lines, and one for each of the plurality of bit lines. A plurality of source lines located in parallel with the bit lines; and a first for applying a bias voltage to each of the source lines located on the negative side of each of the plurality of bit lines among the plurality of source lines. A decoder; and a source line located on the other side of each of the plurality of bit lines among the plurality of source lines. A memory cell array in the nonvolatile semiconductor memory device characterized by comprising a second decoder for applying a bias voltage to the LES. 4. The unit cell according to claim 3, wherein in the basic cell group, the first unit cell includes a first floating gate, a first control gate, a first source, and a common drain on a semiconductor substrate; Comprises a second floating gate, a second control gate, the first source, and the common drain on the semiconductor substrate, and the third unit cell includes a third floating gate, the first control gate, and the second control gate on the semiconductor substrate. It consists of a source and the common drain, a non-volatile semiconductor in which the fourth unit cell is characterized in that it is constituted on the semiconductor substrate 4 floating gate, the second control gate, by the second source and said common drain In storage
Memory cell array definitive.