KR100643481B1 - Nonvolatile Semiconductor Memory Device_ - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and in particular, a high voltage generator for generating a first high voltage by boosting a power supply voltage to a predetermined level; A decompression unit for outputting the second high voltage received the first high voltage to a bit line during programming at a predetermined level; And a plurality of memory cells each consisting of a selection transistor and a memory transistor, each having a memory cell array arranged in row and column directions corresponding to a plurality of word lines, a plurality of bit lines, and a plurality of sense lines. A specific memory cell is selected from the plurality of memory cells, and the selected memory cell receives the first high voltage and the ground voltage to the word line and the sense line, respectively, and is coupled to the bit line. And is programmed by receiving the second high voltage.

Therefore, in the present invention, the voltage applied to the bit line is lowered by a predetermined level than the voltage applied to the word line during the write operation, thereby reducing the width of the low concentration conductive region present in the drain region of the select transistor, thereby reducing the area of the unit memory cell. When reducing, the burden on the bit line voltage is reduced, thereby obtaining the same writing effect as in the prior art and preventing breakdown at the bit line junction.

Description

Nonvolatile Semiconductor Memory Device {@@@@}

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device that can be electrically programmed and erased.

Generally, electrically erasable programmable read only memory (EEPROM) is an electrically erasable, programmable, non-powered nonvolatile memory device, unlike static memory (SRAM) and dynamic memory (DRAM). In the EEPROM, there is a flash type that constitutes a memory cell with one transistor and a FLOTOX (Floating gate tunnel oxide) type that configures one memory cell with a selection transistor and a memory transistor. Since the flash type constitutes a memory cell with one transistor, the size of the unit memory cell is small, while the reliability thereof is considerably lower than that of the FLOTOX type. Therefore, FLOTOX type EEPROM with high reliability is adopted for smart card integrated circuit products.

1 is a cross-sectional view showing the device structure of a FLOTOX type memory cell of a conventional nonvolatile semiconductor memory device.

As shown in the drawing, the high concentration impurity (n +) ions and the low concentration impurity (n−) ions are implanted into the P-type semiconductor substrate 10 to form the first high concentration conductivity type region 12 and the second high concentration conductivity type region 14. ), A diffusion layer of the low concentration conductive region 16 is formed, and high concentration impurity (n +) ions are implanted into the low concentration conductive region 16 to form a diffusion layer of the third high concentration conductive region 18. The first polysilicon layer 24 is formed on the upper side between the first and second high concentration conductive regions 12 and 14 through the insulating oxide film 20, and the insulating oxide layer is formed on the first polysilicon layer 24. The second polysilicon layer 24 is formed through the second layer 26, and the third polysilicon layer is formed on the upper portion between the second high concentration conductivity type region 14 and the low concentration conductivity type region 16 via an insulating oxide film 30. 32 is formed.

The first high concentration conductive region 12 is a source S region of a memory transistor, and the second high concentration conductive region 14 is a floating junction region, which is a drain D of a memory transistor and a source S of a selection transistor. And the third high concentration conductivity type region 18 is the drain (D) region of the select transistor.

The first polysilicon layer 24 is a floating gate, and a thin film portion 24A is formed on one side thereof. The thin film portion 24A is formed to overlap the second high concentration conductive region 14 for tunneling electrons and holes.

The second polysilicon layer 28 is coupled to the sense line SL as the control gate CG.

FIG. 2 is a circuit diagram illustrating the equivalent circuit of FIG. 1. As shown in the drawing, the drain D is connected to the bit line BL, and the gate is connected to the selection transistor ST connected to the word line WL. And a memory transistor MT having a floating gate FG and a control gate CG and having a drain D connected to the source S of the selection transistor ST.

The operating voltage conditions for writing, erasing, and reading of the memory cell configured as described above are shown in Table 1 below.

In Table 1, V _S is a source voltage applied to the source S, V _SL is a control voltage applied to the sense line SL, V _WL is a voltage applied to the word line WL, V _BL Denotes a bit line voltage applied to the bit line BL, V _SUB denotes a substrate voltage applied to the semiconductor substrate 10, and V _PP denotes a voltage obtained by boosting the power supply voltage Vcc to a predetermined level. The range is 15-20V.

Referring to Table 1, in order to erase the data written in the memory cell, the source S, the bit line BL, and the semiconductor substrate 10 are grounded (GND), respectively, and the control gate CG and the word line. A high voltage Vpp is applied to each of the WLs. Then, the n-type channel is induced in the selection transistor ST, and a high potential difference is generated between the control gate CG and the drain 18 of the selection transistor ST. As a result, electrons move from the drain of the selection transistor ST to the drain side of the memory transistor MT. The strong electric field of the control gate CG tunnels to the floating gate FG, and electrons are charged in the floating gate FG.

When the data is erased as described above, the threshold voltage Vth of the memory transistor MT is increased by about 3 to 7V due to the electrons charged in the floating gate FG.

Next, in order to write data to the memory cell, as shown in Table 1, the source S is floated, the control gate CG and the semiconductor substrate 10 are grounded GND, and the word line WL is respectively. The high voltage Vpp is applied to the and bit lines BL, respectively. Then, an n-type channel is induced in the select transistor ST, and a high potential difference is generated in the opposite direction between the control gate CG and the drain 18 of the select transistor ST in the opposite direction as in the erasing operation. The electrons charged in the tunnel are tunneled to the drain D side of the memory transistor MT and are discharged to the drain D side through the n-channel of the selection transistor ST.

3 is a graph showing a current voltage characteristic curve of a memory cell of a conventional nonvolatile semiconductor memory device. As the control gate voltage V _CG increases, the drain D and the selection transistor ST of the memory transistor MT are increased. This indicates that the current Ids of the source S increases rapidly from the threshold voltage V _TH .

Reference numeral a denotes a voltage-current characteristic curve during a write operation, indicating that the threshold voltage V _TH maintains a negative voltage in the range of -4 to 0V as the charge charged in the floating gate is discharged.

Reference numeral b denotes a voltage-current characteristic curve during the erase operation, indicating that the threshold voltage V _TH maintains a positive voltage in the range of 3 to 7 V as electrons are charged to the floating gate.

Next, in order to read data from the memory cell, as shown in Table 1, the source S and the semiconductor substrate 10 are grounded, and a low voltage in the range of 0 to 2 V is applied to the sense line SL. A power supply voltage Vcc is applied to the word line WL, and a low voltage in the range of 1 to 2 V is applied to the bit line BL, respectively. In this case, the flow of the cell current Ids is determined depending on whether or not electrons are charged in the floating gate.

First, when electrons are charged in the floating gate FG, the n-channel is induced in the select transistor ST by the voltage Vcc applied to the word line, but the voltage applied to the sense line is the threshold of the memory transistor MT. Since it is less than the voltage V _TH , no channel is induced below the floating gate. Accordingly, no cell current flows from the drain D of the selection transistor ST to the source S side of the memory transistor.

Next, when the floating gate FG is not filled with electrons, n-channel is induced in the selection transistor ST by the voltage Vcc applied to the word line, and the threshold voltage V _TH of the memory transistor MT is applied. ) Is a negative voltage sufficiently lower than the voltage applied to the sense line, so that the channel is induced even under the floating gate. As a result, the cell current flows from the drain D of the selection transistor ST to the source S side of the memory transistor.

Since the potential of the bit line changes depending on whether or not the cell current flows, data stored in the memory cell is detected from this potential change.

In the conventional memory cell, as shown in Table 1, since the high voltage (Vpp) is applied to the bit line during programming, the low concentration conduction type 16 has a third high concentration conduction so that the bit line junction can withstand this high voltage. A junction is formed to surround the mold region 18, which increases the cell area by the increasing width of the low concentration conductive region 16.

As described above, in order to improve the problem of increasing the area of the unit cell, the bit line junction area should be reduced. In this case, a junction breakdown occurs due to a high voltage applied during programming, causing a memory cell to be destroyed.

In order to solve the above problems, an object of the present invention is to reduce the burden on the high voltage of the bit line junction region by reducing the bit line voltage applied to the bit line by a predetermined level during a write operation. In providing.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises: a high voltage generator for generating a first high voltage by boosting a power supply voltage to a predetermined level; A decompression unit for outputting the second high voltage received the first high voltage to a bit line during programming at a predetermined level; And a memory cell array in which a plurality of memory cells each comprising a selection transistor and a memory transistor are arranged in row and column directions corresponding to a plurality of word lines, a plurality of bit lines, and a plurality of sense lines,

A specific memory cell is selected from the plurality of memory cells by an external address, and the selected memory cell receives the first high voltage and the ground voltage to the word line and the sense line, respectively. The second high voltage is programmed to the bit line.

Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a nonvolatile semiconductor memory device in accordance with the present invention.

As shown in the drawing, the high voltage generator 100 generates a first high voltage Vpp by boosting the power supply voltage to a predetermined level, and the second high voltage VppV _{TH which} depressurizes the first high voltage Vpp by a predetermined level. ), A pressure reducing unit 200 for outputting a plurality of transistors, and a selection transistor ST and a memory transistor MT, each of which includes a plurality of word lines WL1 through WLn, a plurality of bit lines BL1 through BLn, and a plurality of sense A plurality of memory cells MC-11 to MC-1 n (MC-11 to MC-m1) (MC-1 n to MC-mn) to be coupled corresponding to the lines SL1 to SLn (MC). -m1,-, MC-mn having a memory cell array 300 arranged in the row and column directions, and a plurality of memory cells (MC-11,-, MC-1n) (MC-11) by an external address; A specific memory cell is selected from MC-m1 (MC-1n, MC-mn) and MC-m1 (MC-mn), and is coupled to correspond to the selected memory cell during a write operation. A first high voltage Vpp is applied to the word line and the sense line, and is applied to the selected memory cell. The bit line coupling response, the second high voltage (Vpp -V _TH) is applied. Here, the word line represents a line coupled to the gate of the select transistor, the sense line represents a line coupled to the floating gate of the memory transistor, and the bit line represents a line coupled to the drain of the select transistor.

The pressure reduction unit 200 includes a plurality of diode elements D1 to Dn for receiving the second high voltage Vpp-V _TH and outputting the voltage by reducing the predetermined level.

Referring to the configuration as described above the operation of the nonvolatile semiconductor device according to the present invention.

Referring to FIG. 4, when the data is written to the memory cell, the data written to the memory cell is erased, or the data is read from the memory cell, the high voltage generator 100 operates in each operation mode. A voltage corresponding to the voltage is generated and applied to a specific word line selected by the decompression unit 200 and the external address, respectively, and the decompression unit 200 has a threshold voltage of the diode element having the voltage generated by the high voltage generation unit 100. The voltage is reduced by (V _TH ) and applied to a specific bit line selected by the external address.

First, assuming that the memory cells MC-11 located in one row and one column by the external address are selected, a write operation of writing data into the memory cells according to an embodiment of the present invention will be described. ) Generates a first high voltage Vpp1 corresponding to a voltage range of 15V to 20V, applies the word high voltage Vpp1 to the word line _WL1 as a word line voltage V WL1, and applies the first high voltage Vpp1 to the pressure reducing unit 200. Is applied to the diode element D1.

According to an embodiment of the present invention, since the diode device D1 has a predetermined threshold voltage V _TH , the first high voltage Vpp1 has a threshold voltage V _TH including a preset back-bias effect. After the pressure is reduced by), it is applied to the bit line BL1 as the bit line voltage V _BL1 which is the second high voltage Vpp2. The reduced voltage corresponds to a voltage range of 13V to 17V.

At this time, the semiconductor substrate of the memory transistor MT and the selection transistor ST and the sense line SL1 coupled to the control gate of the memory transistor MT are in a ground state, respectively, and the source of the memory transistor MT is floating. Will be placed in a state.

In this state, the selection transistor ST of the memory cell MC-11 is turned on because the first high voltage Vpp1 is applied through the word line WL1 coupled to the gate. At this time, the second high voltage Vpp2 = Vpp1-V _TH is applied through the bit line BL1 coupled to the drain of the selection transistor ST and the sense line SL1 coupled to the control gate of the memory transistor MT is grounded. Therefore, the charge charged in the floating gate of the memory transistor MT is drawn to the drain side of the selection transistor ST by the electric field formed by the bit line voltage V _BL1 . As a result, data having logic "1" is written into the memory cell MC-11.

In the conventional writing condition, the same voltage Vpp is applied to the word line and the bit line, but a voltage as low as VppV _TH is applied to the conductive region shared by the floating junction, that is, the memory transistor and the selection transistor. Here, V _TH is about 2 to 3 V as the threshold voltage of the selection transistor in consideration of the back bias effect. Using this principle, in one embodiment of the present invention, VppV _TH , the same voltage as the floating junction, is set as the bit line voltage at the time of writing. By doing so, the write failure problem that can be caused by applying a voltage lower than the word line to the bit line can be solved.

Next, in the erase operation for erasing data in the memory cell MC-11 according to an exemplary embodiment of the present invention, the high voltage generator 100 may include a first high voltage corresponding to a voltage range of 15V to 20V. Vpp1) is generated and applied to the word line _WL1 as the word line voltage V _WL1 and to the sense line _SL1 as the sense line voltage V _SL1 , respectively. At this time, the semiconductor substrate and the bit line BL1 of the memory transistor MT and the selection transistor ST are in a ground state, and the source of the memory transistor MT is in a ground or floating state.

In this state, the selection transistor ST of the memory cell MC-11 is turned on because the first high voltage Vpp1 is applied through the word line WL1 coupled to the gate. In this case, since the bit line BL1 coupled to the drain of the selection transistor ST is grounded and the first high voltage Vpp1 is applied to the control gate of the memory transistor MT coupled to the sense line SL1, the selection transistor Electrons on the drain side of ST) are attracted to the floating gate side by the electric field formed by the voltage applied to the control gate, and are charged to the floating gate by tunneling. As a result, data stored in the memory cell MC-11 is erased, and the memory cell MC-11 is in a state of logic " 0 ".

Next, when the read operation of reading data into the memory cell MC-11 according to an embodiment of the present invention, the high voltage generator 100 generates a voltage corresponding to a voltage range of 0V to 2V to sense It is applied to the sense line _SL1 as the line voltage V _SL1 , generates a voltage corresponding to the voltage range of 1V to 2V, and is applied to the bit line BL1 as the bit line voltage V _SL1 , and the power supply voltage Vcc. ) Is applied to the word line WL1 as a word line voltage V _WL1 . At this time, the semiconductor substrate of the memory transistor MT and the selection transistor ST and the source of the memory transistor MT are in a ground state.

In this state, if data is written in the memory cell MC-11, a channel is formed under the floating gate of the memory transistor MT, so that the drain of the selection transistor ST is moved from the drain of the selection transistor ST to the source side of the memory transistor MT. If a current flows and data is erased in the memory cell MC-11, a channel is not formed under the floating gate due to the electrons charged in the floating gate. No current flows to the source side of MT).

As described above, since the potential of the bit line changes depending on whether or not the cell current flows, data stored in the memory cell is detected from this potential change.

Table 2 shows the operating voltage conditions for writing, erasing, and reading of the memory cell according to the present invention as described above.

In another embodiment of the present invention, the high voltage generator 100 reduces the first high voltage Vpp1 boosted by the power supply voltage by a predetermined level, and the reduced voltage is reduced by the decompression unit 100 and the external address during the writing operation. A decompression circuit is applied to each of the selected word lines.

The decompression circuit is configured to decompress and output the first high voltage Vpp1 by a voltage range of 1 to 5V.

Write, erase, and read operations of another embodiment of the present invention are the same as the embodiment of the present invention, and a detailed description thereof will be omitted.

The present invention is not limited to the above-described embodiments and can be practiced in various ways without departing from the spirit of the invention.

As described above, in the present invention, the voltage applied to the bit line during the write operation is lowered by a predetermined level than the voltage applied to the word line, thereby reducing the width of the low concentration conductive region present in the drain region of the selected transistor, thereby reducing the unit memory cell. When reducing the area of the circuit, the burden on the bit line voltage is reduced, thereby obtaining the same writing effect as in the prior art and preventing breakdown at the bit line junction.

1 is a cross-sectional view showing the device structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 2 is a circuit diagram illustrating an equivalent circuit of FIG. 1. FIG.

3 is a graph showing a current voltage characteristic curve of a memory cell of a conventional nonvolatile semiconductor memory device.

4 is a block diagram illustrating a nonvolatile semiconductor memory device according to the present invention;

* Explanation of symbols for the main parts of the drawings

100; High voltage generation units DV1 to DVn; Decompression unit

D1 to Dn; diode

MC-11 to MC-1n, MC-11 to MC-m1, MC-1n to MC-mn, MC-m1 to MC-mn; Memory cell

MA1-MAn; Memory arrays BL1 to BLn; Bitline

WL1-WLn; Word lines SL1 to SLn; Sense Line

ST; Select transistor MT; Memory transistor

Claims (9)

A high voltage generator for generating a first high voltage by boosting the power supply voltage to a predetermined level; A decompression unit for outputting the second high voltage received the first high voltage to a bit line during programming at a predetermined level; And A plurality of memory cells each composed of a selection transistor and a memory transistor includes a memory cell array disposed in row and column directions corresponding to a plurality of word lines, a plurality of bit lines, and a plurality of sense lines, A specific memory cell is selected from the plurality of memory cells by an external address, and the selected memory cell receives the first high voltage and the ground voltage to the word line and the sense line, respectively. And the second high voltage is programmed to the bit line. The method of claim 1, wherein the decompression unit And depressurizing the first high voltage by a voltage range of 1 to 5V to output the first high voltage. The method of claim 1, wherein the decompression unit A nonvolatile semiconductor memory device comprising a plurality of diode elements. The method of claim 1, And the source of the memory transistor is floated, the sense line is grounded, and the semiconductor substrate is grounded in the selected memory cell. The method of claim 1, And wherein the selected memory cell is applied with the first high voltage to a word line and a sense line coupled correspondingly during an erase operation. The method of claim 5, And the bit line, the source of the memory transistor and the semiconductor substrate are grounded during the erase operation. The method of claim 5, The selected memory cell is a non-volatile semiconductor memory device, characterized in that the bit line and the semiconductor substrate is grounded during the erase operation, the source of the memory transistor is floating. The method of claim 1, wherein the first high voltage is Non-volatile semiconductor memory device, characterized in that the voltage range of 15 to 20V. The method of claim 1, wherein the second high voltage is Non-volatile semiconductor memory device, characterized in that the voltage range of 13 to 17V.