JPH02192739A - Hetero junction field effect transistor - Google Patents

Abstract

PURPOSE:To prevent the sattering of electrons of a two-dimensional electron gas channel due to ionized impurity of an electron supply layer by arranging a region into which a conductivity type impurity is introduced, in the vicinity of a two-dimensional carrier gas channel of a semiconductor channel layer. CONSTITUTION:On a semiinsulative GaAs substrate 1, the following are grown in order; a non-doped GaAs layer 2, an Si-doped GaAs layer 3 and a non-doped GaAs layer 4. These layers constitute a semiconductor channel layer 13, and the Si-doped GaAs layer 3 turns to a region into which N-type impurity is introduced. In this constitution, by the effect of positive charge of the Si-doped GaAs layer 3, the two-dimensional electron gas distribution stretches in the direction so as to separate from a hetero junction interface, and electron of the two-dimensional electron gas channel 12 becomes hard to suffer scattering caused by ionized impurity of an Si-doped AlxGa1-xAs layer 6, so that the generation of noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a heterojunction field effect transistor that utilizes a two-dimensional carrier gas at a heterojunction interface.

(b) Conventional technology In a heterojunction in which semiconductor crystals with a forbidden band width larger than that of the substrate crystal are laminated on a semiconductor crystal bale plate, it is known that a two-dimensional carrier bus is formed at the heterojunction interface in a certain case. It's coming. The high electron mobility transistor (HEλIT), which has recently attracted attention as an ultra-high-speed semiconductor device, is a type of heterojunction field effect transistor (HJFET) that utilizes the two-dimensional TF gas at the heterojunction interface.
For example, Jpn, J. Appl, Phys, 19.
I, 225-L227.1980 and Special Publication No. 59-53
(See Publication No. 714).

Figure 3 shows A! 1 is a schematic cross-sectional view of a conventional HEMT using a GaAs/GaAs heterojunction, and the manufacturing method thereof will be explained below with reference to the same figure.

First, on a semi-insulating GaAs substrate (21), molecular beam epitaxy (MBE) technology or organometallic epitaxy (
The non-doped GaAs layer (2
2) was grown to a J7 size of 1 μm, and the non-doped Ga
In the As layer (22), non-doped A' x Ga
+ −n A s layer (23) is grown to a thickness of 0 to 60 nm, and then the non-doped A (, G a ,, A 5
Si-doped A ttG a +−,A on layer (23)
S layer (Si concentration: 0.5-2.OX 10”cm-
') (24) to a thickness of 250 to 450 people,
Furthermore, the Si-doped Al-Ga +-, As layer (24
) on top of S1-doped GaAs layer (Si concentration 20
, 1-5. OX 10”am-”) (25) to 100
- Grow to a thickness of 1500 people. Here AjGaA
The composition X of the S layer is approximately 0.3.

Thereafter, an ohmic metal such as Au-Ge/Ni is vapor-deposited on the heteroepitaxial plate formed in this way, and the metal is left in the source electrode formation part and the drain electrode formation part by a lift-off method, and then one gold The ohmic region is Si-doped with GaAs layer (25).
, Si-doped A' W Ga +, As layer (24)
, the non-doped ALGa, -xAs layer (23), and the non-doped GaAs layer (22) to connect the source to the pole (
26), forming a drain pole (27); A part of the Si-doped GaAs layer (25) between the source electrode (2G) and the drain electrode (27) is removed to form a recess (28), and a gate electrode (29) is formed on this recess (28). )
form. This gate tfi! (29) uses AI or Ti/Pt/, Au, etc. as a source electrode (26
) and the drain electrode (27) by the lift-off method,
Formed by selective deposition.

In the HEMT manufactured by the manufacturing method as described above, non-doped Al, Ga, -, As layers (2
3) and the non-doped GaAs layer (22), a two-dimensional electron gas channel (30) is formed on the non-doped (J a As layer (22) side).Si-doped At.

The Ga + -gAs layer (24) serves as the Schottky barrier φm of the gate electrode (29) and the non-doped GaAs
Layer (22) and non-doped A'*G a 1- a
The A s layer (23) is depleted by the conduction band energy difference ΔEc due to the difference in electron affinity, and negatively charged electrons are induced at the heterojunction interface by the positively ionized impurities, and the two-dimensional electron gas channel (30 ) is formed.

The device shown in FIG. 3 performs a transistor operation as a HEMT by controlling the electrons traveling in the two-dimensional electron gas channel (30) by the electric field effect of the LT electrode (29). Note that Si-doped At.

The surface of the Ga,-,As layer (24) is very active,
Si-do-7GaA
An s layer (25) is provided.

Figure 4 shows the gate electrode (29) of a conventional HEMT.
8i dolphin A t, Ga + - wA S layer (24)
-Non-doped A 1. G a 1-IA s layer (23)
- Conduction band energy diagram across the non-doped GaAs layer (22). In the figure, the B1 region is Si-doped A' x G
a+-g As layer (24), B, region is non-doped ALG a 1-yA s layer (23), B, region is two-dimensional electron gas channel (30), B4 region is non-doped GaAs layer (22), and the forbidden band widths are approximately 1.80 eVB in the B1 and B regions, and 1.43 eV in the B4 region. Also, B.

Region and B, the interface between the region, that is, AjGaAs/GaAs
The conduction band energy difference at the heterojunction interface is approximately 0.32 eV
It is. The non-doped GaAs layer (22) is non-doped and S1-doped At.

Since it is separated from the ionized impurities of the Gap-, As layer (24), there are very few ionized impurities, and the source electrode (
When a voltage is applied between the drain electrode (26) and the drain electrode (27), electrons operate at high speed and with low noise because they are less scattered by ions.

(c) Problems to be Solved by the Invention Si-doped At, Ga + - mA s layer (24
), the positively ionized impurity 70 degrees becomes higher, and the negatively charged electrons in the two-dimensional electron gas channel (30) are transferred to the Si-doped ALGa,−,As layer at the heterojunction interface. (24) Being drawn to the side. That is, the negatively charged electrons in the two-dimensional electron gas channel (30) are easily affected by the ionized impurities in the Si-doped ALGa + -, As layer (24), resulting in increased scattering. Non-doped AtyoGa which is a spacer layer
1-xAs/l? By increasing the thickness of (23), Si
Although the effect of scattering due to ionized impurities in the doped AGa1-HAs layer (24) can be reduced, the two-dimensional electron gas concentration (24) is reduced accordingly, and overall noise reduction cannot be achieved.

(d) Means for Solving the Problems The present invention provides a semi-insulating crystal substrate, a semiconductor channel layer provided on the semi-insulating crystal substrate, and an impurity of one conductivity type provided on the semiconductor channel layer. is introduced into the electron supply layer, an input electrode and an output electrode provided on the electron supply layer F, and a control 9111 provided on the electron supply layer between the input 1 and the output electrode. and
In a heterojunction field effect transistor in which a two-dimensional carrier gas channel is formed on the electron supply layer side of the semiconductor channel layer, an impurity of one conductivity type is introduced in the vicinity of the two-dimensional carrier gas channel of the semiconductor channel layer. A heterojunction field effect transistor characterized by comprising a region.

(e) Effect When the concentration of N-type impurities in the 1tf supply layer is increased, the electric field strength at the heterojunction interface becomes stronger, and the two-dimensional electron gas concentration 11
, becomes larger, while the thickness of the two-dimensional electron gas channel becomes narrower. However, in the present invention, a region into which an N-type impurity is introduced is provided near the two-dimensional electron gas channel in the semiconductor channel layer. Positively ionized impurities in this region act to thicken the two-dimensional electron gas channel.

That is, the two-dimensional t+ gas distribution expands in a direction away from the vicinity of the heterojunction due to the action of positive charges in the region.

(f) Example FIG. 1 is a schematic sectional view of the HEMT according to the present invention, and the manufacturing method thereof will be explained below with reference to the same figure.

First, a semi-insulating GaAs substrate (semi-insulating crystal substrate) (1
), a non-doped GaAs layer (2) is grown to a thickness of 1 μm by MBE technology, and the non-doped GaAs layer (2) is grown to a thickness of 1 μm.
Si-doped GaAs layer (Si concentration I
10 "cffl-') (3) to a thickness of 100 nm, and on the S1 doped GaAs layer (3), grow a non-doped GaAs layer (4) to a thickness of 150 nm;
Non-doped Al on the non-doped GaAs layer (4)
Grow the x Ga +-w As layer (5) to a thickness of 20 nm, and add the undoped Al-Ga +-x A
s layer (5) tl: Si doped A LG a 1. A
S layer (Children's income layer in '1) (Sii agricultural degree 2 x 10
``cm-') (6) to a thickness of 350 people,
The Si-doped Al*Ga + -*As1l(6)h
Si-doped GaAs layer (Si concentration 3 x 10 l'
am-') (7) to grow to a thickness of 500 people a
The AI composition X of the A
) is composed of layers (2)<3)(4), and Si-doped G
The aAs layer (3) becomes a region into which N-type impurities are introduced.

Thereafter, an ohmic metal such as Au-Ge/Ni is vapor-deposited on the heteroepitaxial substrate thus formed, and alloyed by a lift-off method, leaving the metal in the source electrode formation area and the drain electrode formation area. , the ohmic region is formed by S1-doped GaAs layer (7), Si-doped A'tG a 1-xA s layer (6), and non-doped A
A source electrode (input electrode) (8) and a drain electrode (output electrode) (9) are formed by penetrating the 'wGaltAs layer (5) and the non-doped GaAs layer (4). The negative part of the Si-doped GaAs layer (7) is removed between the source electrode (8) and the drain electrode (9).
A gate electrode (control electrode) (11) is formed on this recess (10).

The gate 1 pole (11) is formed by selectively depositing At or Ti-Pt-Au using a lift-off method.

In the HEMT manufactured by the manufacturing method described above, a two-dimensional electron gas channel (two-dimensional carrier gas channel) (12) is formed near the heterojunction interface in the non-doped GaAs layer (4).

Figure 2 shows the gate electrode (11)-5i of the fabricated HEMT.
Dope A 1. Ga,, As layer (6) - non-doped A 1. It is a conductor energy diagram spanning the Ga1-MAs layer (5), the non-doped GaAs layer (4), the 5i-doped GaAs layer (3), and the non-doped GaAs layer (2). In the figure, the A1 region is Si-doped A 1 , Ga
+ -m As In the s layer (6), the A2 region is non-doped A
LG a 1-wA S layer (5), region A is the two-dimensional electron gas channel (12), region A is the non-doped GaAs layer (however, the two-dimensional electron gas channel (12)
2) except <) (4), A, region is Si-doped GaAs
In layer (3), A.

The regions correspond to the non-doped GaAs layer (2), respectively, and the forbidden band widths are A1 and A, and the regions are 1.74 eV, A, and -A.
, the region is 1.43 eV. Furthermore, the conduction band energy difference ΔEc at the heterojunction interface between AI and A3 regions is approximately 0.
．． It is 26eV.

In the conventional HEMT without the Si-doped GaAs layer (3), the thickness of the two-dimensional electron gas channel (12) was approximately 80 mm, but in the present invention, the thickness is approximately 100 mm, which is slightly heterogeneous. It spreads from the bonding interface toward the substrate side. That is, in the present invention, due to the positive charge of the Si-doped GaAs layer (3),
The two-dimensional electron gas distribution spreads away from the heterojunction interface. Therefore, in the HEMT of the present invention, the electrons in the two-dimensional electron gas channel (12) are
, the Ga1-zAs layer (6) is less susceptible to scattering due to ionized impurities, thereby reducing noise. H in this example
In EMT, the minimum noise figure NFm1n is lower than the conventional 1.2 dB.
It was possible to reduce it from 1.0 dB to 1.0 dB.

Furthermore, in the above embodiment, Si-doped At1Cy
a + −+ A b layer (6) is divided into two regions, and the heterojunction yarn i+'j side is S1 doping concentration 3 x l Q ”a
The gate electrode (11) side may have a Si doping concentration of 0.7X IQ "cm-" and a thickness of 350 cm. In this HEMT, the minimum noise figure NFm1
o could be set to 0.8 dB.

The Si-doped GaAs layer (3) serves to expand the two-dimensional electron gas distribution in the direction away from the heterojunction interface, but this Si-doped GaA 8 layer (3)
If the S1 doping) concentration is made extremely high or the thickness is made extremely thick, the minimum noise figure NFm1n deteriorates. This is because the ionized impurity scattering of the Si-doped Ga layer (3) is thicker (or the Si-doped Ga layer is thicker).
This is because problems such as formation of a channel in the As layer (3) occur. Therefore, the Si-doped GaAs layer (
3) is Sl Dove concentration is 5 x 1
0"cm-'-2x1018cm"', thickness is preferably 50-300λ in urban areas.

In this example, Si-doped A1. Ga,,A
Although the non-doped ALGa,-,A s layer (5) was provided to reduce scattering due to ionized impurities in the s layer (6), if the desired characteristics could be achieved without providing the @(5), The nuclear layer (5) is not absolutely necessary.

Furthermore, in this example, Si-doped Ga, As layers (3
) In order to reduce scattering due to ionized impurities, the thickness of the non-doped GaAs layer (.1) was made approximately 50 mm thicker than the thickness of the two-dimensional electron gas channel (12). , it does not necessarily have to be thick.

In addition, in this example, in order to form a good ohmic, a Si-doped GaAs layer (7) was provided, but the core layer (7)
The core layer (7) is not necessarily required if the desired characteristics can be achieved without providing the core layer (7).

Furthermore, in this example, the semiconductor channel layer (13) is made of a non-doped GaAs layer (2), a Si-doped GaAS layer (
3) and a non-doped GaAs layer (4),
The non-doped GaAs layer (2) may also be provided.

Although the MBE method was used to grow each layer in the above-mentioned example, other methods that can form a steep heterojunction interface, such as MO
CVD technology or the like can be used.

Furthermore, it is clear that the present invention can be applied to field effect transistors using InALAs-1nGaAs heterojunctions, InGaAs-1nP heterojunctions, and the like.

Further, although the present invention has been mainly described with respect to a heterojunction field effect transistor using a two-dimensional electron gas, it is clear that the present invention can be applied to a heterojunction field effect transistor using a two-dimensional hole gas.

(g) Effects of invention book 51! As is clear from the above explanation, the electron supply layer is improved by providing a region in which impurities of the same conductivity type as the impurities introduced into the electron supply layer are introduced near the two-dimensional carrier gas channel of the semiconductor channel layer. Since the impurity concentration can be suppressed from being attracted to the two-dimensional canoa gas channel or the heterojunction interface, it is possible to provide a heterojunction field effect transistor with good microwave characteristics.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a heterojunction field effect transistor according to the present invention, FIG. 2 is a conduction band energy diagram of a heterojunction field effect transistor according to the present invention, and FIG. 3 is a conventional heterojunction field effect transistor. A schematic cross-sectional view of a transistor,
FIG. 4 is a conduction band energy diagram of a conventional heterojunction TY effect transistor. (])...Semi-insulating GaAs substrate, (2)...Non-doped GaAs layer, (3)-Si-doped GaAs layer, (4)-3i doped GaAs layer, (5)-...Non-doped A LCr a + - mA s
layer, (6)-S i doped A! , G a +−mA
s layer, (7)=-5i doped GaAs layer, (8)...source electrode, (9)...drain electrode, (l])...gate electrode, (12)...two-dimensional electron Gas channel, (13)・
...Semiconductor channel layer.

Claims (1)

[Claims] 1. A semi-insulating crystal substrate, a semiconductor channel layer provided on the semi-insulating crystal substrate, and an electron supply provided on the semiconductor channel layer into which impurities of one conductivity type are introduced. an input electrode and an output electrode provided on the electron supply layer, and a control electrode provided on the electron supply layer between the input electrode and the output electrode; A heterojunction field effect transistor in which a two-dimensional carrier gas channel is formed on the electron supply layer side, comprising a region in which an impurity of one conductivity type is introduced in the vicinity of the two-dimensional carrier gas channel of the semiconductor channel layer. A heterojunction field effect transistor characterized by: