JP2677808B2 - Field-effect transistor - Google Patents

Description

The present invention relates to a field effect transistor, and more particularly to a miniaturized field effect transistor. [Prior Art] In order to improve the operating speed of a field effect semiconductor device (hereinafter abbreviated as FET), it is effective to shorten the channel length. However, in the case of the conventional FET, no consideration has been given to the problems that occur with the shortening of the channel. Examples of FETs of this type include JP-B-45-12097. As a method of preventing punch-through associated with the shortening of the FET channel, there is a method in which an impurity layer having a thickness of 10 to 200Å is provided inside and on the surface of the semiconductor substrate. An example of this is JP-A-61-111687. [Problems to be Solved by the Invention] In the FET of U.S. Pat. No. 45-12097, a punch-through phenomenon occurs as the channel becomes shorter. This phenomenon deteriorates the drain current-gate voltage characteristics in the subthreshold region. That is, the short-channel FET has an unfavorable characteristic that the punch-through current flows between the source and the drain and the drain current is not completely pinched off as compared with the long-channel FET. Further, in the FET of JP-A-61-116875 mentioned above, the punch-through prevention effect is obtained by using the impurity layer, but it is necessary to control the thickness and concentration of the impurity layer with high precision, and the realization thereof is not possible. It wasn't always easy. An object of the present invention is to provide a FET structure that effectively suppresses the above punch-through current and can be easily manufactured. [Means for Solving Problems] The above-mentioned object is to prevent the spatial spread of the carrier distribution that causes the punch-through current to flow and the spatial spread of the drain depletion layer so that the potential line is easily spread. That is, it is achieved by embedding a Schottky metal near the channel. That is, the present invention has the respective currents (15, 16, 14; 26, 27, 25) of the source, drain and gate as shown in FIG. 1 and FIG.
Semiconductor layers (13; 22,) stacked on the semiconductor substrate (11; 21)
24) In a field effect transistor in which a channel is formed almost parallel to the main plane of a semiconductor substrate, a Schottky metal (1
2; 23) is embedded, and the semiconductor layer has an impurity concentration of 1
It is less than × 10 ¹⁷ cm ³ , the distance between the channel and the Schottky metal is about the width of the depletion layer formed by the Schottky junction, and the Schottky metal has almost the same length as the gate electrode. It adopts a transistor configuration. The Schottky metal is the source and drain of the FET,
It is desirable that it is not electrically coupled to each electrode of the gate. Here, "not electrically coupled" means that no metal portion or a high-concentration impurity layer of about 1 × 10 ¹⁷ cm ^-3 or more is interposed between the Schottky metal and each electrode. As the material of the Schottky metal, it is preferable to use nickel silicide or cobalt silicide when the semiconductor forming the semiconductor layer is silicon, and aluminum or tungsten when the semiconductor is gallium arsenide. The field effect transistor of the present invention has a so-called lateral structure suitable for high integration, that is, a structure in which a channel is formed parallel to the main plane of the substrate. [Operation] A punch-through current flows in a short channel FET. The reason is that the drain depletion layer extends toward the source side and the drain depletion layer and the source depletion layer directly influence each other.
This phenomenon becomes more remarkable as the channel length is shortened, so that a large punch-through current flows. The Schottky metal embedded in the vicinity of the channel functions to prevent the bulge of the equipotential line from extending to the source side, that is, to shield the drain electric field. Therefore, the punch-through effect is suppressed, and a good short channel FET can be provided. [Examples] Hereinafter, the present invention will be described in detail according to Examples. Example 1 As shown in FIG. 1, Ni and Si were simultaneously formed on a P-type (100) Si substrate (11) of low impurity concentration with a specific resistance of about 20 Ωcm at a substrate temperature of 400 ° C. by using a molecular beam epitaxy method. After vapor deposition, patterning is performed using photolithography to form a single crystal NiSi ₂ layer (12). A single crystal P ^- type Si (13) was grown on the above sample by 500Å again using the molecular beam epitaxy method to form a structure in which a single crystal NiSi ₂ layer as a Schottky metal was embedded in the single crystal Si. . Further, a gate metal is vapor-deposited on the entire surface of the single crystal P ⁻ type Si (13), and the gate electrode (14) is patterned by using an electron beam drawing method. By using this gate electrode (14), ion implantation is performed by the self-alignment method,
A drain region was formed, and a source electrode (15) and a drain electrode (16) were formed on the drain region by a usual method. As described above, the gate length is 0.3 μm and the channel length is 0.5 μm.
The MES (M Etal Semiconductor) type FET is completed. The current-voltage characteristics of this MES type FET are shown in FIG. In this way, it became possible to obtain good electrical characteristics without a punch through effect in a short channel MES type FET.
The same effect was obtained when single crystal CoSi ₂ was used as the Schottky metal instead of single crystal NiSi ₂ .
In addition, the effect is the type of field effect transistor, that is, MO
It is effective regardless of S type and MES type. Example 2. Next, an example in the case of being used for a GaAs semiconductor will be described.
As shown in FIG. 3, a non-doped GaAs layer (22) is grown to 2000 Å on a plane-oriented (100) semi-insulating GaAs substrate (21) by the molecular beam epitaxy method. After that, 100 Å of tungsten is grown by the sputtering method and patterned by the photolithography method to form the tungsten layer (23). A non-doped or impurity-doped GaAs layer (24) was grown on the above sample by 500 Å using molecular beam epitaxy to form a structure in which a tungsten layer was embedded in single crystal GaAs. Thereafter, the same method as in Example 1 was used to fabricate a MESFET having a gate length of 0.3 μm and a channel length of 0.5 μm. In this case, tungsten is polycrystalline but Ga
Since As grows so as to enclose polycrystalline tungsten, it is possible to grow a single crystal GaAs layer on tungsten. Therefore, as the semiconductor layer of Example 1,
As in the case of using Si, it was confirmed that tungsten works as a Schottky metal and works as a good punch-through stopper. [Advantages of the Invention] According to the present invention, it is possible to prevent punch-through even in a submicron region having a gate length of 1 μm or less.
FET can be easily realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional structural view of a silicon MES type FET according to a first embodiment of the present invention, FIG. 2 is an operation characteristic diagram of the silicon MES type FET of FIG. 1, and FIG. 3 is a cross-sectional structure diagram of a GaAs MES type FET of Example 2 of FIG. 11 …… P-type (100) silicon substrate, 12 …… single crystal NiSi ₂ layer, 13 …… single crystal P ^- type silicon, 14
...... Gate electrode, 15 …… Source electrode, 16 …… Drain electrode, 21 …… (100) semi-insulating GaAs substrate, 22 …… Non-doped GaAs layer, 23 …… Tungsten layer, 24 …… GaAs layer, 25…
… Gate electrode, 26 …… Source electrode, 27 …… Drain electrode.

   ────────────────────────────────────────────────── ─── Continuation of front page        Panel     Referee Hideo Fujiwara     Referee Tsuneya Sekine     Referee Masahide Kawaguchi                (56) References JP-A-61-116875 (JP, A)                 JP 61-90469 (JP, A)                 JP 58-182880 (JP, A)

Claims (1)

(57) [Claims] With source, drain and gate electrodes, Si
In a field effect transistor in which a channel is formed in a single crystal Si layer laminated on a semiconductor substrate substantially parallel to the main plane of the semiconductor substrate, a Schottky made of single crystal NiSi ₂ or CoSi ₂ near the channel. Metal is embedded, and the single crystal Si layer has an impurity concentration of 1 × 10
Less than ¹⁷ cm ^-3 , the distance between the channel and the Schottky metal is about the width of the depletion layer formed by the Schottky junction, and the Schottky metal has almost the same length as the gate electrode. Field-effect transistor.