JPH021883U - - Google Patents

Info

Publication number
JPH021883U
JPH021883U JP8005488U JP8005488U JPH021883U JP H021883 U JPH021883 U JP H021883U JP 8005488 U JP8005488 U JP 8005488U JP 8005488 U JP8005488 U JP 8005488U JP H021883 U JPH021883 U JP H021883U
Authority
JP
Japan
Prior art keywords
socket
pins
base
rows
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8005488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8005488U priority Critical patent/JPH021883U/ja
Publication of JPH021883U publication Critical patent/JPH021883U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Connecting Device With Holders (AREA)
  • Multi-Conductor Connections (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案一実施例の要部斜視図、第2図
は同上のICを装着した状態を示す斜視図、第3
図は同上のICソケツトを実装したプリント基板
の配線パターンを示す正面図、第4図は他の実施
例の要部斜視図、第5図は同上のICを装着した
状態を示す側面図、第6図は同上のICソケツト
を実装したプリント基板の配線パターンを示す正
面図、第7図はさらに他の実施例の要部斜視図、
第8図は同上の上面図、第9図は従来例のICを
実装した状態を示す斜視図、第10図は同上の斜
視図である。 1,1aはIC、2はピン、3は基台、4a,
4bはソケツトピン、5は凹所である。
Fig. 1 is a perspective view of the main part of an embodiment of the present invention, Fig. 2 is a perspective view showing the state in which the same IC is installed, and Fig. 3
The figure is a front view showing the wiring pattern of the printed circuit board on which the above IC socket is mounted, FIG. 4 is a perspective view of the main part of another embodiment, FIG. FIG. 6 is a front view showing the wiring pattern of a printed circuit board on which the above IC socket is mounted, and FIG. 7 is a perspective view of main parts of another embodiment.
FIG. 8 is a top view of the same as above, FIG. 9 is a perspective view showing a state in which a conventional IC is mounted, and FIG. 10 is a perspective view of same as above. 1, 1a are IC, 2 is pin, 3 is base, 4a,
4b is a socket pin, and 5 is a recess.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デユアルインライン型ICのピンが挿入接続さ
れる所定個数のソケツトピンを基台の両端部にそ
れぞれ列設し、上記基台の両ソケツトピン列の間
に他のICを実装する実装手段を設け、複数のI
Cを積層実装自在にしたことを特徴とするICソ
ケツト。
A predetermined number of socket pins into which the pins of the dual-in-line IC are inserted and connected are arranged in rows at both ends of the base, mounting means for mounting another IC is provided between both rows of socket pins on the base, and a plurality of I
An IC socket characterized in that C can be freely stacked and mounted.
JP8005488U 1988-06-15 1988-06-15 Pending JPH021883U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8005488U JPH021883U (en) 1988-06-15 1988-06-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8005488U JPH021883U (en) 1988-06-15 1988-06-15

Publications (1)

Publication Number Publication Date
JPH021883U true JPH021883U (en) 1990-01-09

Family

ID=31304902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8005488U Pending JPH021883U (en) 1988-06-15 1988-06-15

Country Status (1)

Country Link
JP (1) JPH021883U (en)

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