JPS62160482U - - Google Patents
Info
- Publication number
- JPS62160482U JPS62160482U JP4840886U JP4840886U JPS62160482U JP S62160482 U JPS62160482 U JP S62160482U JP 4840886 U JP4840886 U JP 4840886U JP 4840886 U JP4840886 U JP 4840886U JP S62160482 U JPS62160482 U JP S62160482U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- row
- socket
- pin hole
- pin holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Connecting Device With Holders (AREA)
Description
第１図および第２図はそれぞれこの考案の一実
施例の斜視図および側面図、第３図は一実施例の
ＩＣソケツトの変形例の側面図、第４図および第
５図はそれぞれこの考案の他の実施例の平面図お
よび右側面図、第６図は他の実施例の変形例の右
側面図、第７図は従来のＩＣソケツトの斜視図で
ある。
１……搭載部、２……ピン孔、３……ピン、４
Ａ，４Ｂ，４Ｃ，４Ｄ，４Ｅ……ピン孔列、Ａ，
Ｂ……第１および第２の間隔、５……電気配線。
1 and 2 are respectively a perspective view and a side view of an embodiment of this invention, FIG. 3 is a side view of a modified example of the IC socket of one embodiment, and FIGS. 4 and 5 are respectively a perspective view and a side view of an embodiment of this invention. FIG. 6 is a right side view of a modification of the other embodiment, and FIG. 7 is a perspective view of a conventional IC socket. 1...Mounting part, 2...Pin hole, 3...Pin, 4
A, 4B, 4C, 4D, 4E...pin hole row, A,
B...first and second spacing, 5...electrical wiring.
Claims (1)
て、ＩＣチツプの投載部に、同数のピン孔を一定
ピツチで一列に配設したピン孔列を、第１のＩＣ
チツプの幅に対応する第１の間隔と第２のＩＣチ
ツプの幅に対応する第２の間隔とで少なくとも三
列設けるとともに、第１のＩＣチツプ用のピン孔
列と第２のＩＣチツプ用のピン孔列との各対応す
るピン孔をそれぞれ電気的に接続したことを特徴
とするＩＣソケツト。 In a dual in-line type IC socket, a row of pin holes in which the same number of pin holes are arranged in a row at a constant pitch is placed in the IC chip loading part of the first IC socket.
At least three rows are provided with a first interval corresponding to the width of the chip and a second interval corresponding to the width of the second IC chip, and a pin hole row for the first IC chip and a pin hole row for the second IC chip. An IC socket characterized in that each corresponding pin hole is electrically connected to a row of pin holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4840886U JPS62160482U (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4840886U JPS62160482U (en) | 1986-03-31 | 1986-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62160482U true JPS62160482U (en) | 1987-10-12 |
Family
ID=30869907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4840886U Pending JPS62160482U (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62160482U (en) |
-
1986
- 1986-03-31 JP JP4840886U patent/JPS62160482U/ja active Pending