JPH01123379U - - Google Patents
Info
- Publication number
- JPH01123379U JPH01123379U JP1979788U JP1979788U JPH01123379U JP H01123379 U JPH01123379 U JP H01123379U JP 1979788 U JP1979788 U JP 1979788U JP 1979788 U JP1979788 U JP 1979788U JP H01123379 U JPH01123379 U JP H01123379U
- Authority
- JP
- Japan
- Prior art keywords
- package
- protrusions
- wiring board
- printed wiring
- positioning device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図はこの考案の一実施例を示す一部破断し
て示す側面図、第２図はこの考案に係るＩＣパツ
ケージの底面を示す底面図である。
図中、１はＩＣパツケージ、２はリード、３は
プリント配線基板、４Ａ，４Ｂは突起、５Ａ，５
Ｂは穴である。
FIG. 1 is a partially cutaway side view showing an embodiment of this invention, and FIG. 2 is a bottom view showing the bottom surface of an IC package according to this invention. In the figure, 1 is an IC package, 2 is a lead, 3 is a printed wiring board, 4A, 4B are protrusions, 5A, 5
B is a hole.
Claims (1)
突起と、該突起が挿入されるべき穴が所定位置に
設けられているプリント配線基板とを備え、前記
突起が前記プリント配線基板の穴に挿入されるこ
とによつて、前記ＩＣパツケージが前記プリント
配線基板上に対して適正に位置決めされることを
特徴とするＩＣパツケージの位置決め装置。 (2) 前記突起が少なくとも２個である請求項１
記載のＩＣパツケージの位置決め装置。 (3) 前記突起は前記ＩＣパツケージ底面におけ
るほぼ対角線上に互いに離れて位置されている請
求項２記載のＩＣパツケージの位置決め装置。[Claims for Utility Model Registration] (1) An IC package includes a plurality of protrusions provided on the bottom surface of the IC package cage, and a printed wiring board in which holes into which the protrusions are to be inserted are provided at predetermined positions; A positioning device for an IC package, wherein the IC package is properly positioned on the printed wiring board by being inserted into a hole in the printed wiring board. (2) Claim 1, wherein there are at least two protrusions.
The IC package positioning device described above. (3) The IC package positioning device according to claim 2, wherein the protrusions are located substantially diagonally apart from each other on the bottom surface of the IC package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979788U JPH01123379U (en) | 1988-02-17 | 1988-02-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979788U JPH01123379U (en) | 1988-02-17 | 1988-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123379U true JPH01123379U (en) | 1989-08-22 |
Family
ID=31235621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979788U Pending JPH01123379U (en) | 1988-02-17 | 1988-02-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123379U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013502620A (en) * | 2009-08-24 | 2013-01-24 | グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー | Control of electronic devices using chiplets |
-
1988
- 1988-02-17 JP JP1979788U patent/JPH01123379U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013502620A (en) * | 2009-08-24 | 2013-01-24 | グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー | Control of electronic devices using chiplets |