JPH0218746B2 - - Google Patents

Info

Publication number
JPH0218746B2
JPH0218746B2 JP1487284A JP1487284A JPH0218746B2 JP H0218746 B2 JPH0218746 B2 JP H0218746B2 JP 1487284 A JP1487284 A JP 1487284A JP 1487284 A JP1487284 A JP 1487284A JP H0218746 B2 JPH0218746 B2 JP H0218746B2
Authority
JP
Japan
Prior art keywords
data transfer
instruction
data
program
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1487284A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60159958A (ja
Inventor
Makoto Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP1487284A priority Critical patent/JPS60159958A/ja
Publication of JPS60159958A publication Critical patent/JPS60159958A/ja
Publication of JPH0218746B2 publication Critical patent/JPH0218746B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP1487284A 1984-01-30 1984-01-30 デ−タ転送制御回路 Granted JPS60159958A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1487284A JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1487284A JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Publications (2)

Publication Number Publication Date
JPS60159958A JPS60159958A (ja) 1985-08-21
JPH0218746B2 true JPH0218746B2 (enEXAMPLES) 1990-04-26

Family

ID=11873104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1487284A Granted JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Country Status (1)

Country Link
JP (1) JPS60159958A (enEXAMPLES)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH061460B2 (ja) * 1984-04-13 1994-01-05 沖電気工業株式会社 プロセッサ間通信方式
JPH03156558A (ja) * 1989-11-14 1991-07-04 Nec Home Electron Ltd ホストｃｐｕとコプロセッサとの間の通信方法

Also Published As

Publication number Publication date
JPS60159958A (ja) 1985-08-21

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term