JPH0217847U - - Google Patents
Info
- Publication number
- JPH0217847U JPH0217847U JP9600588U JP9600588U JPH0217847U JP H0217847 U JPH0217847 U JP H0217847U JP 9600588 U JP9600588 U JP 9600588U JP 9600588 U JP9600588 U JP 9600588U JP H0217847 U JPH0217847 U JP H0217847U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- conductor pattern
- substrate
- circuit according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 238000007772 electroless plating Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
Landscapes
- Structure Of Printed Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Wire Bonding (AREA)
- Waveguides (AREA)
Description
第１図及び第２図は本考案の混成集積回路を示
す平面図及び断面図、第３図乃至第５図は他の実
施例を示す平面図及び断面図、第６図は従来例を
示す平面図である。
１……絶縁性金属基板、２……導体パターン、
２′……アース接地ライン、３……半導体素子、
４……接続体、５……ザグリ部。
1 and 2 are a plan view and a sectional view showing a hybrid integrated circuit of the present invention, FIGS. 3 to 5 are a plan view and a sectional view showing other embodiments, and FIG. 6 is a conventional example. FIG. 1... Insulating metal substrate, 2... Conductor pattern,
2'...Earth grounding line, 3...Semiconductor element,
4... Connection body, 5... Counterbore part.
Claims (1)
た所望形状の導体パターンと、前記導体パターン
上に固着され複数の半導体素子から形成された高
周波回路と、前記半導体素子が固着される前記導
体パターンの一端と前記絶縁性金属基板とを少な
くとも一カ所以上で接続せしめる接続体とを備え
たことを特徴とする混成集積回路。 (2) 前記導体パターンにアース接地用ラインを
設け、前記アース接地用ラインと前記基板とを複
数カ所で接続せしめることを特徴とする請求項１
記載の混成集積回路。 (3) 前記アース接地ライン及び前記半導体素子
が固着される前記導体パターン下の前記基板には
その表面を露出させるためのザグリ部が設けられ
たことを特徴とする請求項１及び２記載の混成集
積回路。 (4) 前記接続は前記接続体と前記ザグリ部とで
行われることを特徴とする請求項１及び３記載の
混成集積回路。 (5) 前記接続体はＡｌ線又はＡｕ線のボンデイ
ング線であることを特徴とする請求項１乃至４記
載の混成集積回路。 (6) 前記接続体は導電性ペーストであることを
特徴とする請求項１乃至３記載の混成集積回路。 (7) 前記接続体は無電解メツキによつて行われ
たことを特徴とする請求項１乃至４記載の混成集
積回路。 (8) 前記ザグリ部はドリルあるいはレーザーに
よつて行われることを特徴とする請求項１乃至４
記載の混成集積回路。 (9) 前記絶縁性金属基板は絶縁処理されたアル
ミニウム基板であることを特徴とする請求項１乃
至４記載の混成集積回路。[Claims for Utility Model Registration] (1) An insulating metal substrate, a conductor pattern of a desired shape formed on the substrate, and a high-frequency circuit fixed on the conductor pattern and formed from a plurality of semiconductor elements; A hybrid integrated circuit comprising: a connecting body connecting one end of the conductor pattern to which the semiconductor element is fixed to the insulating metal substrate at at least one place. (2) Claim 1 characterized in that an earth grounding line is provided in the conductor pattern, and the earth grounding line and the substrate are connected at a plurality of locations.
Hybrid integrated circuit as described. (3) The hybrid device according to claim 1 or 2, wherein the substrate under the conductor pattern to which the earth grounding line and the semiconductor element are fixed is provided with a counterbore portion for exposing the surface thereof. integrated circuit. (4) The hybrid integrated circuit according to claim 1 or 3, wherein the connection is made between the connection body and the counterbore. (5) The hybrid integrated circuit according to any one of claims 1 to 4, wherein the connecting body is a bonding wire of an Al wire or an Au wire. (6) The hybrid integrated circuit according to any one of claims 1 to 3, wherein the connecting body is a conductive paste. (7) The hybrid integrated circuit according to any one of claims 1 to 4, wherein the connection body is formed by electroless plating. (8) Claims 1 to 4, wherein the counterboring is performed by a drill or a laser.
Hybrid integrated circuit as described. (9) The hybrid integrated circuit according to any one of claims 1 to 4, wherein the insulating metal substrate is an aluminum substrate treated with insulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096005U JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096005U JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0217847U true JPH0217847U (en) | 1990-02-06 |
| JPH0741161Y2 JPH0741161Y2 (en) | 1995-09-20 |
Family
ID=31320794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988096005U Expired - Lifetime JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0741161Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183422A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Plastic molded type semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6372180A (en) * | 1986-09-12 | 1988-04-01 | ティーディーケイ株式会社 | Electronic component and manufacture of the same |
| JPS6359370U (en) * | 1986-10-06 | 1988-04-20 |
-
1988
- 1988-07-20 JP JP1988096005U patent/JPH0741161Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6372180A (en) * | 1986-09-12 | 1988-04-01 | ティーディーケイ株式会社 | Electronic component and manufacture of the same |
| JPS6359370U (en) * | 1986-10-06 | 1988-04-20 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183422A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Plastic molded type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0741161Y2 (en) | 1995-09-20 |