JPH0195796U - - Google Patents

Info

Publication number
JPH0195796U
JPH0195796U JP19072787U JP19072787U JPH0195796U JP H0195796 U JPH0195796 U JP H0195796U JP 19072787 U JP19072787 U JP 19072787U JP 19072787 U JP19072787 U JP 19072787U JP H0195796 U JPH0195796 U JP H0195796U
Authority
JP
Japan
Prior art keywords
layer
metal foil
conductive paste
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19072787U
Other languages
Japanese (ja)
Other versions
JPH0611595Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987190727U priority Critical patent/JPH0611595Y2/en
Publication of JPH0195796U publication Critical patent/JPH0195796U/ja
Application granted granted Critical
Publication of JPH0611595Y2 publication Critical patent/JPH0611595Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第3図は本考案の代表的実施態様を示
す夫々斜視図、平面図である。また、第2図は従
来の態様を示す断面図である。 1は基板、2は信号パターン部銅箔層、2′は
アースパターン部銅箔層、3はアンダーコート層
、4は銅ペースト層、4′は線条銅ペースト、4
″は散点状銅ペースト及び5はオーバーコート層
である。
1 and 3 are a perspective view and a plan view, respectively, showing typical embodiments of the present invention. Moreover, FIG. 2 is a sectional view showing a conventional aspect. 1 is a substrate, 2 is a signal pattern copper foil layer, 2' is a ground pattern copper foil layer, 3 is an undercoat layer, 4 is a copper paste layer, 4' is a wire copper paste, 4
'' is a dotted copper paste and 5 is an overcoat layer.

Claims (1)

【実用新案登録請求の範囲】 (1) 基板上の金属箔層に信号パターン等が形成
され、該パターン部上に導電性ペースト層が絶縁
層を介して被覆され部分的に導電性ペースト層と
金属箔層とが直接接続されてなるプリント配線板
において、該導電性ペースト層と金属箔層とが直
接接続されてなる部分の接続態様が、該部分内部
において導電性ペースト層と金属箔層とが散線点
状に直接接続され、残部が導電性ペースト層、金
属箔層の両者に接着性の良好な素材からなるアン
ダーコート層を介して導電性ペースト層と金属箔
層とが間接的に接着されてなることを特徴とする
プリント配線板。 (2) 散線点状が散点状、格子状又は複数の線条
状である実用新案登録請求の範囲第1項記載のプ
リント配線板。 (3) 金属箔層が銅箔層である実用新案登録請求
の範囲第1項記載のプリント配線板。 (4) 導電性ペースト層が銅又は銀系のペースト
層である実用新案登録請求の範囲第1項記載のプ
リント配線板。 (5) アンダーコート層がエポキシ樹脂又はフエ
ノール樹脂を主成分とする素材からなるアンダー
コート層である実用新案登録請求の範囲第1項記
載のプリント配線板。
[Claims for Utility Model Registration] (1) A signal pattern, etc. is formed on a metal foil layer on a substrate, and a conductive paste layer is partially covered with an insulating layer on the pattern part. In a printed wiring board in which the conductive paste layer and the metal foil layer are directly connected, the connection mode of the part where the conductive paste layer and the metal foil layer are directly connected is such that the conductive paste layer and the metal foil layer are connected to each other inside the part. are directly connected in the form of scattered dots, and the remaining part is indirectly connected to the conductive paste layer and the metal foil layer through an undercoat layer made of a material with good adhesion to both the conductive paste layer and the metal foil layer. A printed wiring board characterized by being bonded. (2) The printed wiring board according to claim 1, wherein the scattered dots are in the form of dots, a grid, or a plurality of lines. (3) The printed wiring board according to claim 1, wherein the metal foil layer is a copper foil layer. (4) The printed wiring board according to claim 1, wherein the conductive paste layer is a copper- or silver-based paste layer. (5) The printed wiring board according to claim 1, wherein the undercoat layer is made of a material whose main component is epoxy resin or phenolic resin.
JP1987190727U 1987-12-17 1987-12-17 Printed wiring board Expired - Lifetime JPH0611595Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987190727U JPH0611595Y2 (en) 1987-12-17 1987-12-17 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987190727U JPH0611595Y2 (en) 1987-12-17 1987-12-17 Printed wiring board

Publications (2)

Publication Number Publication Date
JPH0195796U true JPH0195796U (en) 1989-06-26
JPH0611595Y2 JPH0611595Y2 (en) 1994-03-23

Family

ID=31481674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987190727U Expired - Lifetime JPH0611595Y2 (en) 1987-12-17 1987-12-17 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH0611595Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013045849A (en) * 2011-08-23 2013-03-04 Dainippon Printing Co Ltd Wiring board with built-in chip inductor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831428U (en) * 1981-08-26 1983-03-01 日本精工株式会社 track guide bearing
JPS5837169U (en) * 1981-09-02 1983-03-10 ソニー株式会社 circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831428U (en) * 1981-08-26 1983-03-01 日本精工株式会社 track guide bearing
JPS5837169U (en) * 1981-09-02 1983-03-10 ソニー株式会社 circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013045849A (en) * 2011-08-23 2013-03-04 Dainippon Printing Co Ltd Wiring board with built-in chip inductor

Also Published As

Publication number Publication date
JPH0611595Y2 (en) 1994-03-23

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