JPH02172320A - Counter circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution and to attain high speed operation by applying logic arithmetic operation based on the output of a prescribed data flip-flop of a pseudo random signal generating circuit using plural data flip-flops and an exclusive OR circuit. CONSTITUTION:A pseudo random signal generating circuit 100 generating a prescribed primitive polynomial using plural data flip-flops (D-F/F) 1-5 and an exclusive OR circuit 6 and a logic arithmetic gate 7 applying the logic arithmetic operation based on an output of a prescribed D-F/F of the pseudo random signal generating circuit 100 are provided. The D-F/F 1-5 causes the state as specified corresponding to the arrival of the clock but it is not a sequential advance by a binary number. However, each one state appears in response to the arrival clock number, the output of the prescribed F/F of the D-F/F 1-5 is extracted by the logical arithmetic gate 7 so as to detect the state and an output representing the completion of the prescribed number is obtained. Thus, the part of the logic arithmetic gate is simplified and high speed operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit for counting a required number.

[Conventional technology]

Conventionally, when configuring a counter circuit, a plurality of data flip-flops (hereinafter referred to as DF/F) are used to continuously represent the state of each DF/F up to a predetermined value in binary numbers. A method was adopted in which connections were made using DF/F and logical operation gates.

For example, the hexadecimal counter is 4 as shown in FIG.
D-FFs 31 to 34 and exclusive OR circuits 35 to 3
7 and AND gates 38 and 39. In this hexadecimal counter, when 0 to 16 clocks are applied to the clock signal line 40, the signals at the output terminals 0UT41 to 414 change as shown in Table 1 below. That is, D-FF3
When 1 to 34 cause 16 state changes, the output represents 0 to 15 in binary.

Table 1 [Problems to be Solved by the Invention] However, in such a conventional counter circuit, since the count value is expressed by a binary number in each ])-F/F state, the number of logical operation gates is large. is -numerically (
In order to realize a 2n-1,) base counter circuit, (2
n-3) pieces are required, resulting in a problem that the configuration is complicated. Furthermore, the input signal line to the AND gate is also (2n-
1) In a base counter circuit, there are (n-1) pieces,
A counter circuit that counts large numbers guarantees high-speed operation.1! -) There was a problem that would disappear.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a counter circuit that can simplify the configuration and ensure high-speed operation even when counting large numbers.

[Problem to be solved by the invention]

A counter circuit according to the present invention includes a pseudo-random signal generation circuit realized by a predetermined primitive polynomial using a plurality of data flip-flops and an exclusive OR circuit, and a predetermined data flip-flop of the pseudo-random signal generation circuit. It is characterized in that it is equipped with a logical operation key 1 for performing logical operations based on the output of the .

[Effect]

Since the counter circuit according to the present invention is configured as described above, the counter circuit includes a pseudo random signal generating circuit or a plurality of ll-F/Fs.
and an exclusive OR circuit, these D-F
/F manifests a predetermined state in response to the arrival of the clock. However, this predetermined state is not a sequential step by binary number.

However, since one state is currently used depending on the number of clocks that arrive, if a logic operation gate is configured to take out the output of a predetermined D'-F/F to detect this state, the counter of the present invention The circuit performs each D during counting.
- Regardless of what state the F/F is in, it is possible to obtain an output indicating that a predetermined number has been counted when a predetermined D-F/F is in the above state.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 shows a hexadecimal counter circuit according to an embodiment of the present invention. The pseudo random signal generation circuit 100 is I)-F/
It is composed of Fl-5 and an exclusive OR circuit (EX-OR) 6. The output of D-F/F3 and D-F/F5 is EX
It is applied to the input terminal of -OR6, and the output of EX□OR6 is applied to the D terminal of 1)-F/Fl. D-F/F
1 to 5 are connected in cascade. In this way, the pseudo-random signal generation circuit 100 of this embodiment uses the primitive polynomial 1+X
24-X4.

D-F/Fl, D-F/F2. I) -F/, the output of F4 is given to a three-man AND gate 7 that performs an AND operation on the negative logic signal (L), and the output of the AND gate 7 becomes H (positive logic signal). When this happens, it is detected that the clock "]5" has arrived.

In other words, it is a hexadecimal counter circuit.

In this counter circuit, before starting measurement (counting), the preset terminals PR of DF/F1 to 5 are connected to the preset terminals shown in FIG.
A preset signal that transitions from H level to L level as shown in a) is given, and DF/Fs 1 to 5 are set to "1". Next, connect the clock terminal CK to the clock terminal CK as shown in Fig. 2(b).
As shown in FIG.
~5 changes the state as shown in Table 2.

Table 2 In the above, when the clock number is 115'', D-
F/F1. , D-F/F2. DF/F4 or rOJ =
Since it goes to L level, the output of AND gate 7 goes to H level for the first time, realizing a hexadecimal counter (see Figure 2).
C)). If the count is continued in this state, as is clear from Table 2, the count will reach "20" and an H level signal will be applied again from the AND gate 7.
In order to prevent this, the preset signal is set to 1 after "15".
) - Set "1" in F/Fl~5, return the clock number to "0" and start operation (see Figure 2 (a)
)). In this way, in this embodiment, it is possible to realize a counter circuit that detects the arrival of clock "15" regardless of the values of each of DF/F1 to 5 during counting.

In the present invention, the primitive polynomials for realizing the pseudorandom signal generation circuit are as shown in Table 3, for example.

Table 3 In general, a pseudorandom signal generation circuit realized by an n-th order primitive polynomial returns to the original state with (2n-1-) clocks, and changes to the (2n-1) state depending on the number of clocks. appear. For example, the above quadratic polynomial 1 +x,
+ x 2, EX-OR44 shown in FIG.
If a pseudo-random signal generation circuit having the following is realized, each of the D-F/F4] to 43 changes as shown in Table 4 in response to the number of arriving clocks.

] O Therefore, when realizing a counter circuit, it is sufficient to take out the output from the necessary F/F corresponding to the desired count value and guide it to a predetermined logic operation gate.

For example, using the pseudo-random signal generation circuit shown in FIG.
When realizing a digital counter circuit, D-F/F41
．． The output of the I>F/F 42 may be led to a two-man powered ant gate, and it may be detected that the output of the ant gate 1 becomes H level.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, as the primitive polynomial, expressions other than those exemplified above may be used. Furthermore, it goes without saying that the logic operation gate is not limited to Antogame 1. In short, the pseudo-random signal generation circuit realized by the n-th order primitive polynomial is (2°-
1) Since there are several states, if one of these states is captured by a logic operation gate, the necessary counter circuit can be realized, and in order to capture this state, all D-F/F Since it is not necessary to detect the pressure of

〔Effect of the invention〕

2. As described in detail, according to the present invention, the pseudo-random signal generation circuit generates a primitive polynomial of order n (2°-1).
Since the following states are expressed, the logical operation part can be simplified by detecting one of these states by performing a logical operation. Furthermore, even when counting large numbers, it is not necessary to use the outputs of all pig flip-flops, so high-speed operation can be guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a counter circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the counter circuit according to an embodiment of the present invention, and FIG.
FIG. 4 is a block diagram of a pseudo-random signal generation circuit, and is a block diagram of a conventional counter circuit. 1 ] ] 2 1-5. 41-43...D EX-OR, 7... Antoge F/F, 6. 44..., 100...pseudo random signal generation circuit. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] A pseudo-random signal generation circuit realized by a predetermined primitive polynomial using a plurality of data flip-flops and an exclusive OR circuit, and an output of a predetermined data flip-flop of this pseudo-random signal generation circuit. A counter circuit comprising a logic operation gate that performs logic operations based on.