JPH0216826A - Auxiliary signal transmission circuit - Google Patents
Auxiliary signal transmission circuitInfo
- Publication number
- JPH0216826A JPH0216826A JP16596488A JP16596488A JPH0216826A JP H0216826 A JPH0216826 A JP H0216826A JP 16596488 A JP16596488 A JP 16596488A JP 16596488 A JP16596488 A JP 16596488A JP H0216826 A JPH0216826 A JP H0216826A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error correction
- auxiliary transmission
- signal
- transmission signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 title claims description 8
- 230000005540 biological transmission Effects 0.000 claims abstract description 44
- 238000006243 chemical reaction Methods 0.000 claims abstract description 28
- 239000000284 extract Substances 0.000 claims abstract description 7
- 238000000926 separation method Methods 0.000 abstract description 5
- 230000001360 synchronised effect Effects 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 abstract 1
- 238000003780 insertion Methods 0.000 abstract 1
- 230000037431 insertion Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は補助信号伝送回路に関し、特にディジタル無線
通信に用いる誤り訂正回路を含んだ補助信号伝送回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an auxiliary signal transmission circuit, and more particularly to an auxiliary signal transmission circuit including an error correction circuit used in digital wireless communication.
第２図に従来の補助信号伝送回路の一例を送信側、受信
側について示す。FIG. 2 shows an example of a conventional auxiliary signal transmission circuit on the transmitting side and the receiving side.
従来の補助信号伝送回路においては、誤り訂正符号を用
いて無線区間で伝送信号の誤り訂正のみを行う誤り訂正
符号化／復号化回路を構成していた。Conventional auxiliary signal transmission circuits constitute error correction encoding/decoding circuits that only perform error correction of transmission signals in the wireless section using error correction codes.
ところで、誤り訂正回路を含む補助信号伝送回路におい
て補助信号の挿入／抽出を行うには送信側、受信側それ
ぞれにおいて速度変換を２度行わなければならない。そ
の為９回路構成が複雑になるうえ１回路規模が大きくな
るという欠点を有していた。By the way, in order to insert/extract an auxiliary signal in an auxiliary signal transmission circuit including an error correction circuit, speed conversion must be performed twice on each of the transmitting side and the receiving side. As a result, the nine-circuit configuration becomes complicated, and the scale of each circuit becomes large.
本発明の補助信号伝送回路は、送信側においては主信号
の差動変換を行う和分論理回路と。The auxiliary signal transmission circuit of the present invention has a summing logic circuit that performs differential conversion of the main signal on the transmission side.
補助伝送信号用タイムスロットと誤り訂正用タイムスロ
ットを作る速度変換回路と、主信号に補助伝送信号を挿
入する同期多重化回路と、前記補助伝送信号に差動変換
を行う補助伝送路用和分論理回路と、誤り訂正を行う為
に伝送信号に冗長ビットを付加する誤り訂正符号化回路
とを有し、受信側においては送信側で付加した冗長ビッ
トを基に誤り訂正を行う誤シ訂正復号化回路と、主信号
に多重化された補助伝送信号を抽出する分離化回路と、
抽出しだ補助伝送信号に対して送信側における前記補助
伝送信号への差動変換の逆変換を行う補助伝送路用差分
論理回路と、補助伝送信号用タイムスロットと誤り訂正
用タイムスロットを除去する速度変換回路と、送信側に
おける前記主信号への差動変換の逆変換を行う差分論理
回路とを有することを特徴とする。A speed conversion circuit that creates time slots for auxiliary transmission signals and time slots for error correction, a synchronous multiplexing circuit that inserts auxiliary transmission signals into the main signal, and an auxiliary transmission path summation circuit that performs differential conversion on the auxiliary transmission signals. It has a logic circuit and an error correction encoding circuit that adds redundant bits to the transmission signal to perform error correction.On the receiving side, error correction decoding performs error correction based on the redundant bits added on the transmitting side. a separation circuit that extracts the auxiliary transmission signal multiplexed with the main signal;
A differential logic circuit for an auxiliary transmission line that performs inverse differential conversion of the extracted auxiliary transmission signal to the auxiliary transmission signal on the transmitting side, and a time slot for the auxiliary transmission signal and a time slot for error correction are removed. It is characterized by comprising a speed conversion circuit and a differential logic circuit that performs inverse conversion of the differential conversion to the main signal on the transmission side.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の実施例を送信側と受信側とに分けて示
したブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention divided into a transmitting side and a receiving side.
送信側においては入力情報信号１−１〜１−Ｍに対し和
分論理回路１０１で差動変換を行い。On the transmitting side, a summation logic circuit 101 performs differential conversion on input information signals 1-1 to 1-M.
情報信号２−１〜２−Ｍを出力する。速度変換回路１０
２では情報信号２−１〜２−Ｍに対して速度変換を行い
、補助伝送信号用タイムスロットと誤り訂正用のタイム
スロットとをつくって情報信号６−１〜３−Ｍを出力す
る。補助伝送路用の和分論理回路１０４では、多重化す
べき補助伝送信号４に対して差動変換を行い、その結果
。Information signals 2-1 to 2-M are output. Speed conversion circuit 10
2 performs speed conversion on the information signals 2-1 to 2-M, creates time slots for auxiliary transmission signals and time slots for error correction, and outputs information signals 6-1 to 3-M. The summing logic circuit 104 for the auxiliary transmission path performs differential conversion on the auxiliary transmission signal 4 to be multiplexed, and the result is shown below.
情報信号５を出力する。同期多重化回路１０３では、こ
の情報信号５を情報信号６−１〜３−Ｍの補助伝送信号
用タイムスロットにそれぞれ多重化し、情報信号６−１
〜６−Ｍを出力する。誤り訂正回路１０５では、情報信
号６−１〜６−Ｍの誤り訂正用タイムスロットにそれぞ
れ誤り訂正を行う為の冗長ビットを付加し、情報信号７
−１〜７−Ｍを送出する。An information signal 5 is output. The synchronous multiplexing circuit 103 multiplexes the information signal 5 into the auxiliary transmission signal time slots of the information signals 6-1 to 3-M, and outputs the information signal 6-1.
~6-M is output. The error correction circuit 105 adds redundant bits for error correction to the error correction time slots of the information signals 6-1 to 6-M, and
-1 to 7-M are sent.
受信側では無線区間で送られた情報信号８−１〜８−Ｍ
に対し、送信側で付加した誤り訂正用の冗長ビットを基
に誤り訂正を行い、その結果。On the receiving side, information signals 8-1 to 8-M sent in the wireless section
Error correction is performed based on redundant bits for error correction added on the transmitting side.
情報信号９−１〜９−Ｍを送出する。分離化回路１０７
では、情報信号９−１〜９−Ｍから補助伝送信号を抽出
し、抽出した補助伝送信号１０を送出する。補助伝送路
用の差分論理回路１０８では、抽出した補助伝送信号１
０に対し、送信側の和分論理回路１０４の差動変換とは
逆の変換を行い伝送信号１１を送出する。Information signals 9-1 to 9-M are sent out. Separation circuit 107
Now, the auxiliary transmission signal is extracted from the information signals 9-1 to 9-M, and the extracted auxiliary transmission signal 10 is sent out. In the differential logic circuit 108 for the auxiliary transmission path, the extracted auxiliary transmission signal 1
0, the summation logic circuit 104 on the transmitting side performs a conversion opposite to the differential conversion and sends out a transmission signal 11.
一方１分離化回路１０７では補助伝送信号１０を抽出し
た情報信号１２−１〜１２−Ｍを出力する。速度変換回
路１０２′でこの情報信号１２−１〜１２−Ｍに対して
速度変換を行い、補助伝送路用タイムスロットと誤り訂
正用タイムスロッ！・とを除去して情報信号１６−１〜
１３−Ｍを送出する。差分論理回路１０９では、この情
報信号１６−１〜１３−Ｍに対して送信側の和分論理回
路１０１の差動変換とは逆の変換を行い情報信号１４−
１〜１４−Ｍを送出する。On the other hand, the one-separation circuit 107 outputs information signals 12-1 to 12-M obtained by extracting the auxiliary transmission signal 10. A speed conversion circuit 102' performs speed conversion on the information signals 12-1 to 12-M, and converts them into auxiliary transmission line time slots and error correction time slots.・By removing and, the information signal 16-1~
13-M is sent. The differential logic circuit 109 performs a conversion on the information signals 16-1 to 13-M that is inverse to the differential conversion of the summation logic circuit 101 on the transmitting side, and converts the information signals 16-1 to 13-M into an information signal 14-
1 to 14-M are sent.
以上の様にして、補助伝送信号の挿入／抽出を比較的た
やすく行う事ができる。In the manner described above, it is possible to insert/extract the auxiliary transmission signal relatively easily.
以上、説明した様に本発明は９通信路で伝送される情報
ビットに対して誤り訂正を行う際に。As described above, the present invention applies error correction to information bits transmitted through nine communication channels.
誤り訂正を行う為に伝送すべき情報に対し付加した情報
ビットに同期して伝送信号を挿入／抽出できる様な回路
構成とする事で回路構成を簡単にし９回路規模を縮小す
る事ができ、低い周波数での伝送信号の挿入／抽出を容
易にする事が可能となる。By configuring the circuit so that the transmission signal can be inserted/extracted in synchronization with the information bits added to the information to be transmitted for error correction, the circuit configuration can be simplified and the circuit scale can be reduced. It becomes possible to easily insert/extract transmission signals at low frequencies.
【図面の簡単な説明】
第１図は本発明の一実施例を送信側と受信側とに分けて
示しだブロック図、第２図は従来例を送信側と受信側と
に分けて示すブロック図である。
１０１・・・和分論理回路、 １０２，１０２°・・
・速度変換回路、１０３・・同期多重化回路、１０４・
・補助伝送路用の和分論理回路、１０５・・・誤り訂正
符号化回路、１０６・・・誤り訂正復号化回路、１０７
分離化回路、１０８・・・補助伝送路用の差分論理回路
、１０９・・・差分論理回路。[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention divided into a transmitting side and a receiving side, and Fig. 2 is a block diagram showing a conventional example divided into a transmitting side and a receiving side. It is a diagram. 101... Summation logic circuit, 102, 102°...
・Speed conversion circuit, 103 ・・Synchronous multiplexing circuit, 104 ・
- Summation logic circuit for auxiliary transmission line, 105...Error correction encoding circuit, 106...Error correction decoding circuit, 107
Separation circuit, 108... Differential logic circuit for auxiliary transmission line, 109... Differential logic circuit.
Claims (1)
回路と、補助伝送信号用タイムスロット及び誤り訂正用
のタイムスロットを作る速度変換回路と、主信号に補助
伝送信号を挿入する同期多重化回路と、誤り訂正を行う
為に伝送信号に冗長ビットを付加する誤り訂正符号化回
路と、補助伝送信号に差動変換を行う補助伝送路用和分
論理回路とを有し、受信側においては送信側で付加した
冗長ビットを基に誤り訂正を行う誤り訂正復号化回路と
、主信号列に多重化された補助伝送信号の抽出を行う分
離化回路と、補助伝送信号用タイムスロット及び誤り訂
正用のタイムスロットを除去する速度変換回路と、主信
号に対し送信側における前記主信号の差動変換と逆の変
換を行う差分論理回路と、抽出した補助伝送信号に対し
送信側における前記補助伝送信号への差動変換の逆変換
を行う補助伝送路用差分論理回路とを有する補助信号伝
送回路。1. On the transmitting side, there is a summation logic circuit that performs differential conversion of the main signal, a speed conversion circuit that creates time slots for auxiliary transmission signals and time slots for error correction, and a synchronization circuit that inserts the auxiliary transmission signal into the main signal. The receiving side includes a multiplexing circuit, an error correction encoding circuit that adds redundant bits to the transmission signal to perform error correction, and an auxiliary transmission path summation logic circuit that performs differential conversion on the auxiliary transmission signal. The system includes an error correction decoding circuit that performs error correction based on redundant bits added on the transmitting side, a demultiplexing circuit that extracts the auxiliary transmission signal multiplexed on the main signal stream, and a time slot and a time slot for the auxiliary transmission signal. a speed conversion circuit that removes time slots for error correction; a differential logic circuit that performs differential conversion of the main signal on the transmission side and inverse conversion; An auxiliary signal transmission circuit having an auxiliary transmission line differential logic circuit that performs inverse conversion of differential conversion to an auxiliary transmission signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16596488A JPH0216826A (en) | 1988-07-05 | 1988-07-05 | Auxiliary signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16596488A JPH0216826A (en) | 1988-07-05 | 1988-07-05 | Auxiliary signal transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216826A true JPH0216826A (en) | 1990-01-19 |
Family
ID=15822356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16596488A Pending JPH0216826A (en) | 1988-07-05 | 1988-07-05 | Auxiliary signal transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216826A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6553008B1 (en) | 1998-01-19 | 2003-04-22 | Nec Corporation | Multidirectional time-division multiplexing wireless data communications system |
| WO2017061413A1 (en) * | 2015-10-05 | 2017-04-13 | 清水建設株式会社 | Rc member joining structure |
-
1988
- 1988-07-05 JP JP16596488A patent/JPH0216826A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6553008B1 (en) | 1998-01-19 | 2003-04-22 | Nec Corporation | Multidirectional time-division multiplexing wireless data communications system |
| WO2017061413A1 (en) * | 2015-10-05 | 2017-04-13 | 清水建設株式会社 | Rc member joining structure |
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