JPH03263946A - Code conversion system for transmission in digital communication - Google Patents

Abstract

PURPOSE:To dispense with the conversion of an AIS signal and to simplify a circuit by providing a phase locked loop(PLL) circuit, performing the code convertion of an all '1' signal by a clock signal from the PLL circuit when a fault occurs in an inputted clock signal, and outputting it as the AIS signal. CONSTITUTION:When no input clock S2 is inputted, the disconnection of the clock signal is detected at a clock signal disconnection detection circuit 8, and the AIS signal S14 is outputted. The AIS signal S14 is synchronized with a toothless clock S11 at a velocity conversion circuit 2, and receives device parity check at a code conversion circuit 3, and is mBnB-converted, and a frame signal S12 and an auxiliary signal S13 are inserted to the signal at an insertion circuit 4, and it is outputted as one output signal S7 from a serialparallel conversion circuit 5. At an opposite station, it is detected whether the fault occurs in a system or outside the system by detecting the AIS signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a code conversion system for transmission of digital communications.

[Conventional technology]

A conventional code conversion method for transmission of digital communication will be explained with reference to the drawings.

FIG. 2 is a block diagram showing a conventional code conversion system for transmission of digital communication.

In FIG. 2, the input signal S1 is input to the serial-parallel converter circuit 1.
It is converted into m parallelized signals S3 (an integer of m21), which undergoes a disparity check in the code conversion circuit 3, and is converted into m bits x n bits (hereinafter mBnB) of 0 (an integer of n≧1) ) is converted into a code-converted signal S5a.

In the speed conversion circuit 2, the mBnB code-converted signal S5a synchronized with the input clock signal S2 is converted into a speed synchronized with the clock signal Sll. The tooth extraction clock signal Sll receives a phase difference signal S9 between the input clock signal S2 and the tooth extraction clock signal Sll, and the oscillator 6
- Output by a phase-locked loop circuit (PLL circuit) 9 composed of a frame counter 7.

The frame signal $12 and the auxiliary signal 313 are inserted into the mBnB speed-converted signal S5a at the insertion time M4. Signal S6 with frame signal S12 and auxiliary signal 313 inserted
is converted into one output signal S7 by the parallel-to-serial conversion circuit 5 and output.

When the input clock signal S2 is not input, the clock signal disconnection detection circuit 8a detects the disconnection of the clock signal S2 and outputs the fixed special pattern signal S15. The fixed special pattern signal S15 is the clock signal S for tooth extraction in the speed conversion circuit 2.
frame signal S12 in the insertion circuit 4.
．． An auxiliary signal 813 is inserted, converted into one output signal S7 by the parallel-to-serial conversion circuit 5, and output.

In a game, a failure is detected by detecting the fixed special pattern signal S15.

[Problem to be solved by the invention]

The conventional code conversion method for transmission of digital communication mentioned above is
As shown in FIG. 2, in order to convert the code into mBnB code in the code conversion circuit 2 and transmit it, "0" and "1" in m bits are
A disparity check is performed to find the difference in the total number of ``, and a state transition is performed to change the conversion code group so that the number of occurrences of ``0'' and ``1'' in the output signal is less biased. Convert the code to an n-bit code.

However, when the input clock signal is cut off, the code conversion circuit 2 that was operating with the input clock S2 stops, and the entire "1°" signal, which is generally used as a fault indication signal, is converted into mBnB.
It has a drawback that it cannot be output as a general-purpose fault indication signal (ATS signal) because it cannot change the state for code conversion.

[Means to solve the problem]

The code conversion method for transmission of digital communication of the present invention uses m consecutive bits (m≧1, an integer) of an information signal as one block, and this l block is made up of n (n''2-1, an integer) bits. In a digital communication transmission code conversion system that converts the signal into a frame signal and inserts a frame signal/auxiliary signal, the system is equipped with a phase-locked loop circuit, and when an input clock signal failure occurs, the clock signal from the phase-locked loop circuit converts the total
It has a signal transmission means that converts the code of the signal and outputs it as a fault indication signal (AIS signal).

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the first example, the present embodiment has the same components and the same signal names as the conventional example shown in FIG. 2, and the same numbers are assigned to them. In this embodiment, after the serial-parallel conversion circuit 1, a speed conversion circuit 2,
A code conversion circuit 3 is connected after the speed conversion circuit 2, and the speed conversion circuit 2 also has a clock disconnection circuit that outputs a fault indication signal (ATS signal) S14 of all "1s" when the input clock signal S2 is disconnected. The detection circuit 8 is connected, and the code conversion circuit 3
The main difference is that it is configured to operate by receiving the PLL output tarlock signal SIO from the oscillator 6 without receiving the input clock signal S2.

Next, the operation of this embodiment will be explained.

The input signal S1 is converted into m parallelized signals S3 by the serial-parallel conversion circuit 1. In the speed conversion circuit 2, the parallelized signal S3 synchronized with the input clock signal S2 is converted into a speed synchronized with the clock signal Sll. Tooth extraction tarok signal Sll is oscillator 6-frame counter 7
The signal is output from the PLL circuit 9 consisting of the following.

The speed-converted signal S4 undergoes a disparity check in the code conversion circuit 3 and is converted into n mBnB code-converted signals S5, and the insertion circuit 4 converts the frame signal S12 into n mBnB code-converted signals S5.
, an auxiliary signal 813 is inserted, and the parallel-to-serial conversion circuit 5 converts it into one output signal S7, which is output.

When the input clock S2 is not input, the clock signal disconnection detection circuit 8 detects the tarok signal disconnection and outputs the AIS signal S1.
4 is output. The AIS signal S14 is synchronized with the clock S11 in the speed conversion circuit 2, and the code conversion circuit 2
is subjected to a disparity check and converted to mBnB,
The insertion circuit 4 inserts the frame signal S12 and the auxiliary signal 313, and the parallel-to-serial conversion circuit 5 outputs one output signal S7.

In a game, by detecting the AIS signal, it is possible to detect whether there is a failure within the system or something else.

〔Effect of the invention〕

As explained above, the present invention provides a phase-locked loop circuit (
PLL circuit), the PL circuit is equipped with a
By having a signal transmission means that converts the code of all "1" signals using the clock signal from the L circuit and outputs them as AIS signals, it performs a disparity check on all "1" signals and changes the state when an input signal disconnection occurs. Since the AIS signal from the method of the present invention is common to the AIS signal in other systems, there is no need to convert the AIS signal in the interface with other systems as in the past. This has the effect of simplifying the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional digital communication transmission code conversion system. 1...Series-parallel conversion circuit, 2...Speed conversion circuit,
3... Code conversion circuit, 4... Insertion circuit, 5... Parallel-serial conversion circuit, 6... Oscillator, 7... Frame counter, 8, 8a... Tallock disconnection detection circuit, 9・
...Phase-locked loop circuit (PLL circuit). Sl...input signal, S2...input clock signal, S
3... Parallelized signal, S4. S4a...Speed converted signal, S5. S5a...m bits/n bits (mBnB>signal converted), S6...signal with frame signal/auxiliary signal inserted, S7...output signal, S8...output clock signal, S9... ...Phase difference signal, S10...PLL output clock signal, Sll...
For tooth extraction, clock signal, S12... frame signal, 81
3... Auxiliary signal, S14... Fault indication signal (AIS
signal), S15...Fixed special pattern signal.

Claims (1)

[Claims] For digital communication transmission, where m consecutive bits (m≧1, an integer) of an information signal are defined as one block, and this one block is converted into n (an integer, n1) bits, and frame signals and auxiliary signals are inserted. In the code conversion method, a signal transmission means is provided with a phase-locked loop circuit, and converts all "1" signals into codes using a clock signal from the phase-locked loop circuit when an input clock signal is disconnected, and outputs the signal as a fault indication signal (AIS signal). A code conversion method for transmission of digital communication characterized by having the following.