JPH09102781A - Frame synchronization code detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit configuration, and to reduce power consumption, and besides, to attain a high speed operation in a frame synchronization detection circuit. SOLUTION: A judging part 2, 3 compares the code pattern of the front position at the time when the frame synchronization code pattern is n-sected (n: integer over '2') with the bit string of a received burst signal, and determines an erroneous bit number, and when the bit number is below a detection judgement threshold, it sends a coincidence signal. In response to the coincidence signal, a timing signal is outputted in a timing generation circuit 4. When the timing signal is received, a detecting part 5, 6, 7, 8, 9 compares the remaining code pattern of the frame synchronization code pattern excluding the code pattern of the front position with the bit string, and when the erroneous bit number of a whole frame synchronization code is below the detection judgement threshold, it outputs a frame synchronization code detection flag.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a frame synchronization code from high speed frame data, and more particularly to a circuit used for detecting a frame synchronization code from high speed frame data sent as serial data from a satellite. Frame synchronization code detection circuit.

[0002]

2. Description of the Related Art Generally, when performing resource management / environmental monitoring on the earth, wide-area exploration (remote sensing) data from satellites is received on the ground. At this time, in order to enable data demodulation on the ground, the remote sensing data is frame data with a frame synchronization code added at the beginning.

In recent years, such remote sensing data has been made highly precise, and as a result, the bit rate of frame data has been further increased, and a frame added to the beginning of frame data in a high speed frame synchronizer. The sync code is detected and demodulated as remote sensing data.

A high-speed frame synchronization device is provided with a frame synchronization detection circuit, and various circuits (systems) are conventionally known as such a frame synchronization detection circuit (frame synchronization system) (for example, Japanese Patent Laid-Open Publication No. Sho. 63-22883
4 and JP-A-5-235924).

Now, with reference to FIG.
The frame synchronization method described in Japanese Patent No. 28834 will be outlined.

In this frame synchronization system, a frame data generator 11 and a data receiver 12 are provided.
When the frame data generation unit 11 receives the data, the transmission frame generation unit 11a generates transmission frame data having a frame synchronization code and information data, and gives it to the CRC calculation frame addition unit 11b. The CRC calculation frame adding unit 11b calculates the CRC based on the transmission frame data.
(Frame error check code) is generated and this CR
C is added to the transmission frame data to create the frame data shown in FIG. Then, this frame data is transmitted from the transmission unit 11c.

When the frame data receiving section 12 receives the frame data shown in FIG. 4, the frame synchronization code detecting section 12a detects the frame synchronization code (coincidence detection). When the frame synchronization code is detected, the frame synchronization code is detected. The unit 12a gives the frame synchronization code match detection flag to the frame synchronization protection unit 12e. The receiving unit 12b holds the frame data. The frame data held by the receiving unit 12b is separated into (frame synchronization code + information data) and CRC data by the receiving frame separating unit 12c, and then C
It is given to the RC calculation unit 12d.

The CRC calculation unit 12d calculates CRC data (reception CRC) based on the frame synchronization code and the information data.
Data) is checked. That is, the CRC calculation unit 12
In d, C based on the frame synchronization code and the information data
Generate RC data (Play this CRC data CRC
If the received CRC data and the reproduced CRC data match, a CRC match detection flag is sent to the frame synchronization protection unit 12e. Further, the CRC calculation unit 12d sends the information data to the reception data generation unit 12f.

The frame synchronization protection unit 12e makes a state transition to frame synchronization establishment based on the frame synchronization code match flag and the CRC match flag, and gives it to the reception data generation unit 12f as a frame synchronization establishment flag. The reception data generation unit 12f generates reception data from the information data according to the frame synchronization establishment flag.

Next, referring to FIG. 5, JP-A-5-235.
The frame synchronization code detection circuit described in No. 924 will be outlined.

When the received burst signal is received, the serial bit string of the received burst signal is converted into parallel data by the data delay circuit 13. The sync pattern comparison memory 14 stores in advance the number of bits that do not match the frame sync code pattern. The sync pattern comparison memory 14 calculates the number of mismatch bits between the parallel data and the frame sync code pattern, and outputs the number of mismatch bits.

The error bit number comparison circuit 15 detects whether or not the number of mismatch bits is less than or equal to the allowable error bit number, and if it is less than or equal to the allowable error bit number, outputs a frame synchronization code detection flag. .

Further, as such a frame detection synchronizing circuit, one shown in FIG. 6 is known.

Referring to FIG. 6, when the reception burst signal is received, the serial bit string of the reception burst signal is converted into parallel data by the serial / parallel conversion circuit 16. The sync pattern comparison circuit 17 compares the parallel data with the frame sync code pattern to calculate the number of mismatch bits, and outputs the number of mismatch bits.

The error bit number comparison circuit 18 performs a comparison detection on whether or not the number of mismatch bits is less than or equal to the allowable error bit number, and if it is less than or equal to the allowable error bit number, outputs a frame synchronization code detection flag. .

In the frame sync detection circuit shown in FIG. 6, a sync pattern comparison circuit 17 is used in place of the sync pattern comparison memory 14 shown in FIG. 5, and this sync pattern comparison circuit 17 is shown in FIG. 7 (a). It has a configuration. That is, the synchronization pattern comparison circuit 17a includes the data comparison unit 17a.
And a mismatch bit number calculation unit 17b, and the mismatch bit number calculation unit 17b operates according to the truth table shown in FIG. 7B.

As is apparent from FIG. 7A, the synchronization pattern comparison circuit 17 includes an exclusive OR circuit and a 3-bit AD.
The DER circuit is used as a basic circuit, and this basic circuit is arranged in a tree shape by the required number of bits.

[0018]

By the way, in the frame synchronization detecting circuit shown in FIG. 4, a frame error check code such as CRC data is added to the frame data to detect the coincidence of the frame error check code and the coincidence of the frame synchronization code. Due to the detection, if the speed of the frame synchronization code detection unit is increased (for example, several tens of Mbps or more), the circuit configuration becomes complicated and power consumption increases.

As described above, the frame sync detection circuit shown in FIG. 5 uses the sync pattern comparison memory in which the number of mismatch bits with the frame sync code pattern is stored in advance. There is a problem that it is extremely difficult to increase the speed (for example, several tens of Mbps or more) because it is defined by the cycle time of the pattern comparison memory.

Further, in the frame synchronization detection circuit shown in FIG. 6, as described above, the synchronization pattern comparison circuit uses the exclusive OR circuit and the 3-bit ADDER circuit as basic circuits, and this basic circuit is provided for the required number of bits. The circuit configuration is arranged in a tree shape. As described above, the frame pattern comparison circuit has a tree (tree) structure, and if the required number of bits increases, the circuit structure becomes complicated and power consumption increases.

It is an object of the present invention to provide a frame synchronization detecting circuit which has a simple circuit configuration and which consumes less power and can be sped up.

[0022]

According to the present invention, a frame sequence of a received burst signal including a frame synchronization code is compared with a frame synchronization code pattern to detect frame synchronization by using an allowable error bit number as a detection determination threshold value. In the frame synchronization code detection circuit, when the number of error bits is equal to or smaller than the detection determination threshold value by comparing the leading code pattern and the bit string when the frame synchronization code pattern is divided into n (n is an integer of 2 or more) A frame sync code detection flag is set when the number of error bits in the entire frame sync code is equal to or less than the detection determination threshold value by comparing the remaining code patterns of the frame sync code pattern excluding the first code pattern with the bit string. And a detection flag generating means for outputting the frame. Code detection circuit is obtained.

Furthermore, according to the present invention, the frame synchronization code is adapted to detect the frame synchronization by comparing the bit string of the received burst signal provided with the frame synchronization code with the frame synchronization code pattern and using the allowable error bit number as the detection judgment threshold value. In the detection circuit, when the frame sync code pattern is divided into n (n is an integer of 2 or more), the leading code pattern is compared with the bit string, and when the number of error bits is equal to or less than the detection determination threshold value, the frame sync code A frame synchronization comprising: a detection means for generating a frame synchronization code detection flag by comparing the pattern with the bit string and detecting that the number of error bits in the entire frame synchronization code is equal to or less than the detection determination threshold value. A code detection circuit is obtained.

[0024]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

Referring to FIG. 1, the illustrated frame synchronization detection circuit includes a serial / parallel conversion circuit 1, and a received burst signal is applied to the serial / parallel conversion circuit 1. This received burst signal has, for example, the frame data format shown in FIG. 2, and a 64-bit frame synchronization code is added to the beginning of the frame.

The serial / parallel conversion circuit 1 converts the bit string of the received burst signal into parallel data. That is, the serial-parallel conversion circuit 1 outputs 8-bit parallel data that shifts in synchronization with the reception clock.

The data pattern comparison circuit 2 divides the frame synchronization code pattern into eight and compares the first (leading) code pattern with the parallel data to calculate the number of mismatch bits. Specifically, the data pattern comparison circuit 2 includes
The leading 8-bit data pattern of the 64-bit frame synchronization code in the frame data shown in FIG. 2 is preset, and the data pattern comparison circuit 2 compares the 8-bit parallel data with the 8-bit data pattern and does not match. Find the number of bits.

The data pattern coincidence judging circuit 3 judges whether or not the number of non-coincidence bits is less than or equal to the data pattern allowable error bit number, and outputs the coincidence detection pulse if it is less than or equal to the data pattern allowable error bit number. In response to the coincidence detection pulse, that is, after the coincidence detection pulse is generated, the timing generation circuit 4 generates a timing signal for comparing the 8-byte (64-bit) frame synchronization code pattern in byte units.

In accordance with the timing signal, the data pattern holding circuit 5 holds the 8-byte frame synchronization code one byte at a time (in byte units) and outputs it as a 1-byte frame synchronization code. That is, the data pattern holding circuit 5 holds the 8-byte (64-bit) frame synchronization code one byte after the match detection pulse is generated. On the other hand, the frame synchronization pattern generation circuit 6 generates an 8-byte frame synchronization pattern one byte at a time according to the timing signal (that is, the frame synchronization pattern generation circuit 6 generates an 8-byte frame synchronization pattern after detection of a match pulse). 1 byte at a time).

Specifically, since the data pattern holding circuit 5 holds the frame data synchronization code in accordance with the timing signal, the data pattern holding circuit 5 holds the first byte (8 bits) from the next 1 byte in byte units. It will be. In this case, the frame synchronization pattern generation circuit 6 generates the remaining frame synchronization patterns except the first byte.

On the other hand, if the data pattern holding circuit 5 is provided with a delay circuit (not shown) for 1 byte, the data pattern holding circuit 5 will add an 8-byte frame synchronization code to the first byte in accordance with the timing signal. They are held one by one (in byte units) and output as a 1-byte frame synchronization code. In this case, the frame synchronization pattern generation circuit 6 generates an 8-byte frame synchronization pattern byte by byte from the beginning.

The frame synchronization code comparison circuit 7 compares the 1-byte frame synchronization code with the 1-byte frame synchronization pattern, and determines the number of unmatched bits for each byte (in units of bytes) (hereinafter referred to as 1-byte unmatched bit number). calculate.

Upon receiving the 1-byte mismatch bit number, the error bit number integration circuit 8 integrates the mismatch bit number by 8 bytes (64 bits) and outputs the integrated error bit number. In the error bit number comparison circuit 9, the accumulated error bit number (that is,
The total number of error bits of the frame synchronization code) is compared with the allowable number of error bits, and if the number of allowable error bits is less than or equal to
The frame synchronization code detection flag is output (note that the configuration of the error bit number comparison circuit 9 is the same as in FIG. 7A,
The operation (operation of the mismatch bit calculation unit) is shown in FIG.
It is represented by the truth table shown in).

In the above example, the first 8-bit data pattern of the frame synchronization code is compared and the coincidence detection pulse is output, but the present invention is not limited to this example, and the number of bits used for coincidence detection is the frame. It is appropriately set depending on the number of bits of the synchronization code and the bit rate. Further, the unit and the number of comparison bits after the output of the coincidence detection pulse are similarly set according to the number of bits and the bit rate of the frame synchronization code.

As is apparent from the above description, the data pattern holding circuit 5, the frame synchronization pattern generating circuit 6,
The frame synchronization code comparison circuit 7, the error bit number integration circuit 8, and the error bit number comparison circuit 9 are 1 / of the bit rate.
The operating speed is 8. Therefore, a constituent element (circuit) that has conventionally required to operate at high speed can be configured by a circuit operating at low speed. As a result, even when the frame synchronization code is detected from the frame data of high speed, the circuit configuration can be simplified and the power consumption can be reduced.

[0036]

As described above, according to the present invention, when detecting a frame synchronization code from high-speed frame data, a component (circuit) which has been required to perform a high-speed operation is configured by a low-speed operation circuit. As a result, there is an effect that the circuit configuration can be simplified and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a frame synchronization code detection circuit according to the present invention.

FIG. 2 is a diagram showing an example of a frame data format used in the frame synchronization code detection circuit shown in FIG.

FIG. 3 is a block diagram for explaining a conventional frame synchronization method.

FIG. 4 is a diagram showing a frame data format used in FIG.

FIG. 5 is a block diagram showing an example of a conventional frame synchronization code detection circuit.

FIG. 6 is a block diagram showing another example of a conventional frame synchronization code detection circuit.

7A and 7B are diagrams for explaining the frame synchronization code comparison circuit shown in FIG. 1 and the synchronization pattern comparison circuit shown in FIG. 7, where FIG. 7A is a diagram showing the logic circuit thereof, and FIG. 3] is a diagram showing a truth table of a mismatch bit number calculation unit shown in FIG.

[Explanation of symbols]

 1, 16 serial-parallel conversion circuit 2 data pattern comparison circuit 3 data pattern coincidence determination circuit 4 timing generation circuit 5 data pattern holding circuit 6 frame synchronization pattern generation circuit 7 frame synchronization code comparison circuit 8 error bit number integration circuit 9, 18 error bits Number comparison circuit 11 Frame data generation unit 12 Frame data reception unit 13 Data delay circuit 14 Synchronization pattern comparison memory 15 Error bit number comparison circuit 17 Synchronization pattern comparison circuit

Claims (5)

[Claims] 1. A frame synchronization code detection circuit for detecting a frame synchronization by comparing a bit string of a received burst signal having a frame synchronization code with a frame synchronization code pattern and using an allowable error bit number as a detection determination threshold value. The synchronization code pattern is n (n is 2
(The above integer) When the number of error bits is less than or equal to the detection determination threshold value by comparing the leading code pattern when divided and the bit string, the remaining code patterns other than the leading code pattern in the frame synchronization code pattern A frame synchronization comprising: a detection flag generating means for comparing the bit string and outputting a frame synchronization code detection flag when the number of error bits in the entire frame synchronization code is equal to or less than the detection determination threshold value. Code detection circuit. 2. The frame synchronization code detecting circuit according to claim 1, wherein the detection flag generating means compares the leading code pattern with the bit string to obtain the error bit number, and the error bit number is Determination means for transmitting a coincidence signal when the detection determination threshold value or less, output timing generation means for outputting a timing signal in response to the coincidence signal,
When the timing signal is received, the remaining code patterns of the frame sync code pattern excluding the leading code pattern are compared with the bit string, and if the number of error bits is equal to or less than the detection determination threshold, the frame sync code is detected. A frame synchronization code detection circuit, comprising: a detection unit that outputs a flag. 3. The frame synchronization code detecting circuit according to claim 2, wherein the detecting means holds the bit string as a holding data pattern for each predetermined bit length in response to the timing signal, An error is generated for each predetermined bit length by comparing the holding data pattern and the specific code pattern with a generation means for generating the remaining code pattern as the specific code pattern by the predetermined bit length in response to the timing signal. First comparing means for obtaining the number of bits as a specific error bit number, integrating means for integrating the specific error bit numbers to obtain an integrated error bit number, and the frame when the integrated bit number is less than or equal to the detection determination threshold value. A frame synchronization code detection circuit comprising: a second comparison means for outputting a synchronization code detection flag. 4. A frame synchronization code detection circuit for detecting a frame synchronization by comparing a bit string of a received burst signal including a frame synchronization code with a frame synchronization code pattern and using an allowable error bit number as a detection determination threshold value. The synchronization code pattern is n (n is 2
(The above integer) When the code pattern at the beginning of the division is compared with the bit string, and the number of error bits is equal to or less than the detection determination threshold value, the frame synchronization code pattern is compared with the bit string to detect the entire frame synchronization code. A frame synchronization code detection circuit, comprising: a detection flag generation means for outputting a frame synchronization code detection flag when the number of error bits is equal to or less than the detection determination threshold value. 5. The frame synchronization code detection circuit according to claim 4, wherein the detection flag generation means compares the leading code pattern with the bit string to obtain the error bit number, and the error bit number is Determination means for transmitting a coincidence signal when the detection determination threshold value or less, output timing generation means for outputting a timing signal in response to the coincidence signal,
When the timing signal is received, the frame synchronization code pattern and the bit string are compared with each other, and a detection unit that outputs the frame synchronization code detection flag when the number of error bits in the entire frame synchronization code is equal to or less than the detection determination threshold value. A frame synchronization code detection circuit having.