JPH0795190A - Dsi clock phase fluctuation suppression circuit - Google Patents

Abstract

PURPOSE:To reduce a phase fluctuation when a synchronization clock is switched from an extracted clock on the occurrence of a fault in a LINE signal by controlling a phase and a frequency of the synchronization clock held in a hold-over circuit as an output DIS clock source so as to be the same as those of an output synchronization clock of a 1/N frequency divider. CONSTITUTION:A fault detection circuit 107 generates a fault detection signal 120 when the circuit 107 discriminates a LINE signal 11 is not suitable for clock extraction and gives the fault detection signal 120 to a hold-over circuit 108, a selector 104, and an AIS addition circuit 106. A 1/M frequency divider circuit 103 and the hold-over circuit 108 are operated by using frequencies f3, f1 almost the same, and a Load signal 110 is given to the hold-over circuit 108 to control the phase synchronization thereby approaching the phase of synchronization clocks f4, f2 generated by the 1/M frequency divider 103 and the hold-over circuit 108 close to the phase of the DIS signal within one clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extracted DS1 clock phase fluctuation suppression circuit, and more particularly to LINE in a transmission device.
The present invention relates to suppression of phase fluctuation of a timing extraction clock.

[0002]

2. Description of the Related Art A conventional DS1 clock extraction circuit is shown in FIG.
As shown in FIG. 3, an optical / electrical signal converter 101, an N frequency divider 102 that divides the converted electric signal, an M frequency divider 103, and a failure detection circuit 107 that detects an optical signal failure and an optical signal failure And the selector 104 that selects the extracted clock 13 and the oscillator clock 24 when the extracted clock 13 becomes inappropriate and the extracted clock 13 becomes inappropriate. Next, the operation will be described.

LINE signal transmitted from the opposite device
The optical signal 11 is converted from an optical signal into an electric signal by the optical / electrical signal converter 101, and is divided by the N frequency divider 102 and the M frequency divider 103 to a clock rate suitable for processing. When the failure detection circuit 107 determines that the LINE signal 11 is not suitable for clock extraction, it sends a control signal for selecting the clock 24 of the oscillator 208 by the selector 104. At the same time, it controls the AIS addition circuit 106 to output the DS1 clock 12 to the AIS (Alarm In circuit circuit).
Signal) is added.

[0004]

In this conventional DS1 clock extraction circuit, when a failure occurs in the LINE signal and it becomes unsuitable for clock extraction, the source of the output DS1 clock becomes the oscillator clock, and this clock is used. Continue to output the DS1 clock to the outside.

In this system, the clock of the oscillator is L
There is a problem that a large phase variation occurs in the output DS1 clock when the extraction clock of the LINE signal is switched to the oscillator clock because the oscillation frequency varies asynchronously with the INE signal.

[0006]

The gist of means for solving such a problem is that, in conformity with the SONET communication method, a local optical transmission / reception device for transmitting / receiving an optical signal to / from a synchronous optical transmission communication device of a remote station. In the synchronous optical transmission communication device of the station, the DS1 clock phase fluctuation suppressing circuit for executing synchronous clock processing converts the optical signal transmitted from the synchronous optical transmission communication device of the remote station into an electric signal. And an optical / electrical signal converter for extracting a synchronous clock f5 from the electric signal, an N divider for dividing the synchronous clock f5 to generate a synchronous clock f3, and an output of the N divider. A sampling oscillator for generating an independent synchronization clock f1 having the same frequency as that of the synchronization clock f3 to be generated, and the synchronization clock f3 of the N frequency divider, and further dividing the frequency. It generates a period clock f4, a timing signal synchronized with the synchronizing clock f3 Loa
A failure that detects a failure of the synchronization clock generated in the optical signal by using the M frequency divider that generates the d signal and the synchronization clock f5 that is extracted from the electrical signal, and further generates a failure detection signal at this time. A detection circuit and a failure detection signal that is generated when a failure occurs in the Load signal and the optical signal and the extraction clock becomes improper, and is synchronized based on the synchronization clock f1 generated by the sampling oscillator. A holdover circuit that generates a substitute clock f2 that is synchronized with the clock f3, and the synchronization clock f that is the output of the M divider in response to the fault detection signal.
Selector for switching 4 to the substitute clock f2 which is the output of the holdover circuit, and A for adding AIS to the DS1 interface in response to the failure detection signal.
The IS addition circuit and the AIS are added to the synchronous clock f2 or f4 input from the selector, and the output DS
DS1 comprising a DS1 interface circuit for sending one clock to the remote station
It exists in the clock phase fluctuation suppression circuit.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 shows the extracted DS of the first embodiment of the present invention.
This is a one-clock phase fluctuation suppression circuit. Note that fn (n =
0, 1, 2, 3, 4, 5) is the frequency of each synchronous clock.

LIN sent from the remote station
The E signal (synchronous clock rate f0) 11 is converted from an optical signal to an electrical signal (synchronous clock rate f0) by the optical / electrical converter 101.
5), and further divided by N divider 102 and M divider 10
At 3, the frequency is divided into clock rates f3 and f4 suitable for processing.

The N divider 102 divides f5 by 1/24 to generate f3.

In the M divider 103, 1.544 / 6.
It is divided by 48 to generate f4. Load signal 11
The synchronous clock rate of 0 is f4.

The fault detection circuit 107 uses the LINE signal 11
When it is determined that the failure detection signal 120 is not suitable for clock extraction, the failure detection signal 120 is generated and the failure detection signal 1 is supplied to the holdover circuit 108, the selector 104 and the AIS addition circuit 106.
Tell 20 This allows the selector 104 to send a control signal for selecting the synchronous clock 12 held by the holdover circuit.

M-minute cycle 102 and holdover circuit 1
08 is operated by using substantially the same frequencies f3 and f1, and further, the load signal 110 is given to the holdover circuit 108 to perform phase synchronization control, thereby generating the M minute period 102 and the holdover circuit 108. The synchronization clocks f4 and f2 can be close to the same phase within one clock of the DS1 signal.

At the same time, the AIS addition circuit 106 is controlled to control the AIS (Alarm Indicate Sign).
al) is added to DS1.

The DS1 interface circuit 105 adds a frame or AIS to the input clock and sends the output DS1 clock 12 to the outside.

[0016]

As described above, the present invention is LINE
When the signal fails and is no longer suitable for clock extraction, the synchronous clock f2 held by the holdover circuit can be used as the output DS1 clock source.

Therefore, since the synchronous clock f2 has substantially the same phase and frequency as the N-divider output synchronous clock f3, the output DS1 clock source is switched from the extracted clock to the synchronous clock even when the LINE signal has a failure. It is possible to reduce the amount of phase fluctuation when

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 101 Optical / Electrical Signal Converter 102 N Divider 103 M Divider 104 Selector 105 DS1 Interface Circuit 106 AIS Additional Circuit 107 Fault Detection Circuit 108 Holdover Circuit 109 Sampling Oscillator 110 Load Signal 120 Fault Detection Signal 130 AIS 208 Oscillator 11 LINE signal 12 Output DS1 clock 13 Extracted clock 14 Synchronous clock 24 Oscillator clock

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[Procedure amendment]

[Submission date] October 26, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

LINE signal transmitted from the opposite device
The optical signal 11 is converted from an optical signal into an electric signal by the optical / electrical signal converter 101, and is divided by the N frequency divider 102 and the M frequency divider 103 to a clock rate suitable for processing. When the failure detection circuit 107 determines that the LINE signal 11 is not suitable for clock extraction, it sends a control signal for selecting the clock 24 of the oscillator 208 by the selector 104. At the same time, the AIS addition circuit 106 is controlled to output the DS1 clock 12 to the AIS (Alarm Indicate).
Signal) is added.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

In order to solve the above problems, the present invention provides the following means. In accordance with the SONET communication system, a DS1 clock installed in a synchronous optical transmission communication device of a local station for transmitting and receiving an optical signal to and from a synchronous optical transmission communication device of a remote station and for executing synchronous clock processing An optical / electrical signal converter for converting the optical signal transmitted from the synchronous optical transmission communication device of the remote station into an electric signal and further extracting a synchronous clock f5 from the electric signal in the phase fluctuation suppressing circuit; The synchronization clock f5 is divided to obtain a synchronization clock f
3 and generates a Load signal which is a timing signal synchronized with the periodic clock f3;
A sampling oscillator that generates an independent synchronization clock f1 having the same frequency as the synchronization clock f3 included in the output of the frequency divider, and the synchronization clock f of the N frequency divider.
M which receives 3 and further divides it to generate a synchronous clock f4
A frequency divider and a failure detection circuit that detects a failure of the synchronization clock generated in the optical signal by using the synchronization clock f5 extracted from the electric signal and further generates a failure detection signal at this time, and the load. Substitute in synchronization with the synchronization clock f3 based on the synchronization clock f1 generated by the sampling oscillator in response to the fault detection signal generated when a failure occurs in the signal and the optical signal and the extraction clock becomes improper A holdover circuit that generates a clock f2; a selector that receives the fault detection signal and switches the synchronous clock f4 that is the output of the M divider to the substitute clock f2 that is the output of the holdover circuit; An AIS addition circuit for generating an AIS in response to a failure detection signal, and the synchronous clock f input from the selector Or the AIS added to f4,
DS1 for sending output DS1 clock to the remote station
A DS1 clock phase fluctuation suppressing circuit comprising an interface circuit. Provided in a synchronous optical transmission communication device for receiving a LINE signal sent from an optical transmission line, and when the LINE signal is normal, outputs a LINE synchronization clock f4 generated by dividing a clock f3 extracted from the LINE signal. In addition, when a failure occurs in the LINE signal,
The local synchronization clock f2 generated based on the clock f1 output from the oscillator oscillating independently of the LINE signal is output, and the LINE synchronization clock f4 is also output.
In the DSI phase fluctuation suppression circuit configured to suppress the phase difference between the local synchronization clock f2 and the local synchronization clock f2, the clock f3
Receiving the Load signal synchronized with the clock and the clock f1
The phase of the clock f1 is set to 1 from the phase of the Load signal.
A holdover circuit that outputs the clock generated by controlling within the clock cycle as the local synchronization clock f2 and the LINE synchronization clock f4 when the LINE signal is normal, and the LINE signal has a failure And a selecting means for selecting the local synchronous clock f2.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

The fault detection circuit 107 uses the LINE signal 11
When it is determined that the failure detection signal 120 is not suitable for clock extraction, the failure detection signal 120 is generated and the failure detection signal 1 is supplied to the holdover circuit 108, the selector 104 and the AIS addition circuit 106.
Tell 20 As a result, the synchronous clock f2 held by the holdover circuit 108 in the selector 104
It is possible to send a control signal for selecting.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

The M divider 103 and the holdover circuit 108 are operated using substantially the same frequencies f3 and f1, and the Load signal 110 is applied to the holdover circuit 108 to perform phase synchronization control. M
The synchronous clocks f4 and f2 generated by the frequency divider 103 and the holdover circuit 108 can be close to the same phase within one clock of the DS1 signal.

Claims (1)

[Claims] According to the SONET communication system, a synchronous clock processing is provided in a synchronous optical transmission communication device of a local station for transmitting and receiving an optical signal to and from the synchronous optical transmission communication device of a remote station. In the DS1 clock phase fluctuation suppressing circuit for executing the optical / electrical conversion, the optical signal transmitted from the synchronous optical transmission communication device of the remote station is converted into an electric signal, and the synchronous clock f5 is extracted from the electric signal. A signal converter, an N divider that divides the synchronization clock f5 to generate a synchronization clock f3, and an independent synchronization clock f1 that has the same frequency as the synchronization clock f3 included in the output of the N divider. The sampling oscillator that is generated and the synchronization clock f3 of the N frequency divider are received and further divided to generate a synchronization clock f4, and the synchronization clock f3 is generated.
A frequency divider for generating a Load signal, which is a timing signal synchronized with, and a synchronization clock f5 extracted from the electrical signal are used to detect a failure of the synchronization clock generated in the optical signal. A failure detection circuit that generates a failure detection signal, and a failure detection signal that is generated when a failure occurs in the Load signal and the optical signal and the extraction clock becomes improper, and the sampling oscillator generates the failure detection signal. A holdover circuit that generates a substitute clock f2 that is based on the synchronization clock f1 and that is synchronized with the synchronization clock f3; and a synchronization clock f4 that is the output of the M frequency divider in response to the failure detection signal. A selector that switches to the substitute clock f2 that is an output and an AIS that receives the fault detection signal and switches the AIS to a DS1 interface. And a DS1 interface circuit for adding the AIS to the synchronous clock f2 or f4 input from the selector and sending an output DS1 clock to the remote station. A DS1 clock phase fluctuation suppressing circuit that does.