JPS62219831A - Time division multiplex communication equipment - Google Patents

Abstract

PURPOSE:To simplify a time division multiplex transmitter by incorporating a time division multiplexer and a transmission line code converter and sending superimposingly a clock signal of a speed a half of the transmission signal speed with a transmission line code so as to eliminate the block synchronizing circuit or the like at the reception side. CONSTITUTION:Channel signals CH1, CH2 are subjected to waveform shaping by flip-flops 10, 11 and bit multiplexed by using a clock f(b)/2 from a 1/2 frequency division circuit 12 by a multiplexer 13 and the result is inputted to a coding circuit 15. The circuit 15 applies partial spectrum is zero at the frequency f(b)/2. The clock f(b)/2 of the 1/2 frequency division circuit 12 is synthesized by adjusting the synthesis ratio by a level adjusting circuit 14, since the signal spectrum of PR(1, 1) is superimposed on the frequency f(b)/2 being zero, then no effect is imposed on the signals CH1, CH2. Further, a reception circuit 2 uses a band pass filter 24 via an amplifier 20 to extract the clock f(b)/2 component, which is led to a 2 multiplier circuit 26 via an amplifier limiter circuit 25, the result is decoded by a decoding circuit 21 as the clock f(b) and the result is separated multiplexedly into the PCM signal of the original signals CH1, CH2 by flip-flops 22, 23.

Description

[Detailed description of the invention] [Summary] 2 using a partial response code etc. as a transmission code
A time division multiplex communication device for channel digital signals,
On the transmitting side, a clock with a frequency where the frequency component of the signal is "O" is phase-synchronized and superimposed on the digital signal of one channel, and on the receiving side, the phase of this clock is detected to demultiplex and demultiplex both channels. conduct.

Field of Application in CM Industry] The present invention relates to a time division multiplex communication device, and particularly to a two-channel high-speed digital communication device.

In high-speed digital communications, such as high-speed PCM communication systems, it is desired to further increase the bit rate with a simpler circuit configuration.

[Conventional technology]

Conventionally, when time-division multiplexing two-channel PCM signals, as shown in FIG.
It has a word structure in which a synchronization signal SYN is added to the two data signals, and on the receiving side, word synchronization is achieved using this synchronization signal, thereby time-division multiplexing and demultiplexing the two-channel signals.

[Problem that the invention seeks to solve]

In the conventional method, if the number of bits of channel signals CH1 and CH2 and synchronization signal SYN is the same, the number of bits of the synchronization signal increases by 50% compared to the number of bits of the channel signal, and therefore the same amount of data is sent. In this case, the signal speed required for the transmission line is increased by 50% compared to the case where the synchronization signal SYN is not added. On the contrary,
At the same signal speed, the amount of data that can be transmitted will decrease by the amount of the synchronization signal.

In order to reduce the loss due to this synchronization signal, there is a method of reducing the ratio of the synchronization signal to the channel signal by setting the number of bits of the channel signals CH1 and CH2 to several tens of bits and setting the synchronization signal SYN to one bit. However, in this case, the configuration of multiplexing and demultiplexing circuits becomes complicated, and
Since it is not easy to identify the bit synchronization signal, a complicated identification circuit is required. In particular, when the signal speed increases, a complex high-speed logic processing circuit is required, which is difficult to implement.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, the transmitting side includes a multiplexing section 101 that multiplexes two channels of digital signals CH1 and CH2, an encoding circuit 102 that encodes the output of the multiplexing section 101, and a clock that adds the output of the encoding circuit 102 and a clock. It is configured to include an adder 104. Also, on the receiving side, a decoding circuit 105 decodes the received signal, and the output of the decoding circuit 105 is converted into two digital signals C) I1,
It is configured to include a demultiplexer 106 that demultiplexes CH2, and a filter 107 that extracts the divided clock frequency from the received signal.

In the time division multiplex communication device of the present invention shown in FIG.
Channel digital signal C) When time-division multiplexing and transmitting I1 and CH2, the transmitting side adds a clock CLK/2 having a frequency where the frequency spectrum of the transmission code is "O" to this transmission code as the digital signal of one channel. Superimpose it in phase synchronization with the signal.

On the other hand, on the receiving side, the superimposed clock CLK/2 is detected, and the phase of the clock is used to identify and demultiplex the two channels of digital signals CH1 and CH2.

[For production]

For example, the partial response code is -f b (n is an integer r f
The signal spectrum component becomes zero at a frequency represented by b (transmission signal frequency). Therefore, the clock CLK/2, which serves as a synchronizing signal to identify the two channels, is superimposed on one of these frequency bands in phase synchronization with the digital signal of one channel and sent to the receiving side. do.

In this case, the clock does not interfere with the digital signal because the frequency ranges of the digital signal and the clock are different.

That is, the digital signals CH1 and CH2 are multiplexed by the multiplexer 1.
After multiplexing with 01 and encoding with encoding circuit 102, it is sent to adder 104. The clock CLK is added to the output of the encoding circuit 102 by an adder 104 and sent to the receiving side.

The receiving side detects this clock CLK, uses its phase to identify the two channels of digital signals CHI and CI2, performs time division multiplexing and demultiplexing, and thereby removes the synchronization signal from the transmitted signal.

That is, after the received signal is decoded by the decoding circuit 105,
filter 1 from the received signal to the demultiplexer 106
07, the clock CLK is extracted, and using this, the demultiplexer 106 identifies and demultiplexes the digital signals CHI and CH2.

In addition, as shown in the spectrum diagrams in Figures 2 to 3, the conventionally used transmission line codes such as NRZ are based on the transmission signal frequency f.
In (b) and 2 f (b), the signal spectrum component is zero, so a clock having this frequency component is added.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing a time division multiplexing apparatus as an embodiment of the present invention. In the figure, ■ is a transmitting circuit, and 2 is a receiving circuit. In the transmitting circuit 1, channel signals CH1,
CH2 is a PCM signal, and its signal speed is clock C
It is half of the frequency f(b) of K. In this example, f
(b) is chosen as IMHz.

Channel signals CH1 and CH2 are sent to a multiplexer 13 via waveform shaping flip-flops 10 and 11, respectively.
is input.

Clock CK is guided to a % frequency divider circuit 12 and an encoding circuit 15. The output signal of the A frequency dividing circuit 12 is sent to the clock terminal CL of the flip-flop 10.11 and the multiplexer 13.
and is also guided to the adder 16 via the level adjustment circuit 14. Further, the inverted output signal of the A frequency dividing circuit 2 is guided to the multiplexer 13.

The multiplexer 13 has three NOR circuits 131 to 133.
It performs time division multiplexing of channel signals CH1 and CH2. The output signal of multiplexer 13 is input to encoding circuit 15 .

The encoding circuit 15 uses a transmission line code whose signal spectrum becomes zero at a frequency of 2 of the transmission signal speed (frequency f(b)) as shown in the signal spectrum diagram of FIG. 4, in this example, for example, a partial response PR ( L1), that is, a duobinary code encoding circuit. The output signal of the encoding circuit 15 is superimposed with clocks of each frequency from the level adjustment circuit 14 in an adder 16, and then transmitted to the receiving circuit 2 via the transmission line 3.

In the receiving circuit 2, the input signal from the transmission line 3 is amplified by an amplifier 20 and then guided to a decoding circuit 21.

The output signal of the decoding circuit 21 is input to flip-flops 22 and 23 for demultiplexing. The output signal of the amplifier 20 is also guided to an amplification/limiter circuit 25 via a bandpass filter 24 with a pass frequency band f (bl/2).The output signal of the amplification/limiter circuit 25 is decoded via a doubling circuit 26. It is guided to the circuit 21 and also to the clock terminal CK of the flip-flop 22.The inverted output signal of the amplification/limiter circuit 25 is also guided to the clock terminal CK of the flip-flop 23.Flip-flop 22.2
The demultiplexed channel signal CH is output from each output terminal of 3.
1 and CH2 are output, respectively.

The operation of the apparatus shown in FIG. 3 will be explained below.

Channel signals CH1 and CH2 are sent to flip-flops 10.
After the waveform is shaped in step 11, it is input to the multiplexer 13, where it is bit multiplexed using the clock f(b)/2 from the A frequency divider circuit 12 as shown in FIG. 15 is input. The encoding circuit 15 converts the bit-multiplexed channel signal into a partial response PR (
1,1) and sends it to the adder 16. As shown in FIG. 4, the signal spectrum of this encoded signal becomes zero at frequency f(b)/2.

In the adder 16, as shown in FIG.
The clock f(b)/2 of the frequency divider circuit 12 via the level adjustment circuit 14 is synthesized with the output signal of the channel signal CHI so that, for example, its rising edge is phase-locked with the channel signal CHI.

The synthesis ratio is adjusted by the level adjustment circuit 14.

When synthesized in this way, the signal spectrum of the clock f (bl/2) is superimposed on the frequency f(b)/2 where the signal spectrum of the partial response PR(1,1) is zero, as shown in Figure 2. Therefore, the clock f(
bl/2 does not affect channel signals CH1 and CH2.

On the other hand, in the receiving circuit 2, the transmission signal attenuated in the transmission path 3 is amplified by the amplifier 20, and then the clock f(
b)/2 component is extracted and guided to the doubling circuit 26 via the amplification/limiter circuit 25, where it is doubled and inputted to the decoding circuit 21 as the clock f (b). Thereby, the transmitted signal is decoded by the decoding circuit 21 into the original bit multiplexed signal (signal rate f(bl)).

This bit multiplexed signal is punched out by the flip-flops 22 and 23 at the rising and falling edges of the clock f(b)/2, respectively, and the P of the original channel signals CH1 and CH2 is
It is demultiplexed into CM signals.

Various modifications are possible in carrying out the invention. For example, in the above embodiment, PR (1, 1) is used as the partial response code, but the present invention is not limited to this, and for example, P
Other partial response codes such as R (1, 0, -1) may be used, and the present invention can be applied as long as the signal spectrum is zero at a frequency that is half the transmission signal speed. is possible.

〔Effect of the invention〕

According to the present invention, the time division multiplexing device and the transmission line code conversion device, which were conventionally designed separately, are integrated, and by superimposing and transmitting a clock signal at half the transmission signal speed on the transmission line code, it is possible to This eliminates the need for block synchronization circuits, etc., which were required in the previous method, thereby making it possible to greatly simplify the time division multiplexing transmission device. Furthermore, compared to the conventional block synchronization signal insertion type time division multiplexing system, the transmission speed does not increase even though the same amount of information is sent.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, and Figure 2 is a block diagram of the principle of the present invention.
) is a diagram for explaining the operation of the system in FIG. 1, FIG. 3 is a block diagram of a communication system that performs a time division multiplexing method as an embodiment of the present invention, and FIG. 4 is a diagram for explaining the operation of the partial response PR (1, 1 ), FIG. 5 is a signal timing diagram at the adder of FIG. 3, and FIG. 6 is a diagram showing the word structure of a conventional transmission signal. CH1, CH2...Channel signal 1--Transmitting circuit 2--Receiving circuit 10.11.22.23...Flip-flop 12-
'A frequency dividing circuit 13・-Multiplexer 14-・-
・Level adjustment circuit 15-encoding circuit 16--adder 20...amplifier 21--decoding circuit
24--Band filter 25--Amplification/limiter circuit 26--Double multiplier circuit Principle according to the present invention Figure 1 Figure 1 Spectrum diagram of electronic response code Figure 4 Signal timing diagram in adder Figure 5 Figure 2 Conventional word structure Figure 6 Spectrum diagram of NRZ code (b) Figure 2

Claims (1)

[Claims] A multiplexing unit (101) that multiplexes digital signals (CH1, CH2) on the transmitting side, and encodes the multiplexed signal so that the signal spectrum becomes zero at constant frequency intervals. A coding circuit (102) is provided, and a decoding circuit (105) for decoding the data and a demultiplexing section (106) for demultiplexing the decoded signals are provided on the receiving side to perform time division multiplex transmission. In the time division multiplex communication device, an adder (104) is provided on the transmitting side for adding a clock signal having a frequency at which the signal spectrum becomes zero to the output of the encoding circuit (102), and an adder (104) is provided on the receiving side. , a time division multiplex communication device comprising a filter (107) for extracting the clock signal from the data.