JP4571560B2 - Digital PB receiver for time division multiplex communication - Google Patents

Description

    The present invention relates to a digital PB receiver used for time division multiplex communication such as a time division multiplex electronic switching system.

  A time division multiplexing (TDM) communication method that divides one transmission line (highway: HW) into multiple time slots on the time axis and assigns them sequentially to multiple digital signals is a large-capacity, high-speed communication method Is widely used.

  In such a time division multiplex communication system, an LSI that simultaneously processes a plurality of time division multiplexed data is used like a signal processing LSI in a communication apparatus such as a telephone exchange.

  FIG. 1 is a block diagram showing a schematic configuration of a conventional digital PB receiver (or a digital PB receiver provided in a time division multiplex communication apparatus) 100. The digital PB receiver demultiplexes the time division multiplexed signal from the time division multiplexing transmission path and extracts a digital PB (push button) signal.

  In order to perform demultiplexing of such time division multiplexed signals, a time division time switch LSI is used (for example, see Patent Document 1).

  Referring to FIG. 1, in more detail, the digital PB receiver (PBREC) 100 is a time division multiplexing transmission line (2M-HW) that uses a time division multiplexed signal with a multiplicity of 8 (8 channels) and a 2 MHz clock, for example. Receive from.

  A digital signal processor (DSP) 102 which is an 8-channel serial interface (SI) performs demultiplexing processing of the time-division multiplexed signal (2M-HW: 8CH) and PB (push button) signal extraction processing. With this process, the low group code (L1 to L4) and the high group code (H1 to H4) of the PB signal are output to the output terminals (D0 to D7) for each of the 8-channel multiplexed signals (CH0 to CH7).

  The PB binary codes (L1 to L4, H1 to H4) of the 8-channel multiplexed signals (CH0 to CH7) are held in the answer register (ANS-REG) 104 for each channel.

  The digital signal processor (DSP) 102 outputs the PB binary code to an SP (Signal Present) binary code output terminal (D8) indicating that the answer register (ANS-REG) 104 exists. The SP code is held in the SP code register (SP-REG) 105.

  A reading / analyzing unit (software interface) 112 provided in a control unit CPU of a time division multiplex communication apparatus or the like (not shown) receives a PB binary from the answer register (ANS-REG) 104 when the SP code register is valid. Read the code.

  As described above, in the digital PB receiver, it is necessary to perform demultiplexing processing, PB signal extraction processing, and the like using a digital signal processor (DSP) corresponding to the multiplicity of the incoming highway.

  However, even if the highway multiplicity increases with the advancement of the system, if the digital PB receiver can be easily configured using the existing digital signal processor LSI, the flexibility of manufacturing the digital PB receiver can be improved. The benefits are great because it contributes to the ability to reduce the cost, delivery time, and cost.

However, when using an LSI for processing a signal with a multiplicity smaller than the multiplicity of the incoming highway, for example, when using an LSI for four channels (two) instead of an LSI for eight channels, Since the interface on the input side (highway interface) and the output side (software interface) are different, there is a problem that it cannot be simply replaced.
JP-A-7-336735 (page 3, FIG. 1)

  The present invention has been made in view of the above points, and an object of the present invention is to be easily configured using an LSI for processing a signal having a multiplicity smaller than that of the incoming highway. It is possible to provide a digital PB receiver that is possible and has excellent design flexibility and flexibility.

  The digital PB receiver according to the present invention performs demultiplexing of an incoming highway signal carrying a time division multiplexed signal in which a predetermined number of channels are multiplexed, and extracts a PB code representing the digital PB signal included in the time division multiplexed signal. A digital PB receiver that divides the incoming highway signal into a plurality of divided highway signals, each provided corresponding to the plurality of divided highway signals, and corresponding divided highway signals A plurality of digital signal processors that extract PB binary codes by performing demultiplexing according to the degree of multiplicity, and a plurality of PB binary codes that hold each PB binary code extracted by each of the plurality of digital signal processors PB code register and a read valid binary code indicating the read valid timing of each of the PB binary codes. It is characterized by having a reading code combining unit for generating a binary code bit sequence corresponding to the channel of the upper fill highway bonded to the.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, substantially the same or equivalent components and parts are denoted by the same reference numerals.

  FIG. 2 is a block diagram schematically showing the configuration of the digital PB receiver 10 according to the present invention. The digital PB receiver 10 can be provided in a time division multiplex communication device, a line tester, a PB (push button) number reception confirmation device, a PB number analysis device, a pseudo terminal device, and other communication test devices. .

  The configuration and operation of the digital PB receiver 10 will be described in detail with reference to FIG. In the following, the digital PB receiver 10 receives a time division multiplexed signal with a multiplicity of 8 (ie, 8 channels) and a 2 MHz clock via a time division multiplexed transmission path (2M highway: 2M-HW). Will be described as an example.

  The digital PB receiver 10 is provided with a highway converter 11, and a 2M highway (8 channels) signal that is an incoming highway signal is supplied to the highway converter 11.

  As shown in FIG. 3, in the present embodiment, a processor control unit 11A is provided in the highway converter 11 to extract a clock signal CLK from the incoming highway signal and to generate a processing control signal to generate a digital signal processor (DSP). # 0) 12A and the digital signal processor (DSP # 1) 12B.

  That is, the processor control unit 11A controls the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B by a processing control signal, and a plurality of incoming highways (2M-HW: 8CH) (this embodiment). In FIG. 2, the division processing is performed as two channel groups. Then, a PB binary code is extracted for each of the plurality of channel groups.

  In this embodiment, the case where the incoming highway (2M-HW: 8CH) is divided into two channel groups # 0 and # 1 (CH0 to CH3 and CH4 to CH7) each having four channels will be described as an example. To do. However, it is understood that the number of divisions and the number of channels in each channel group are merely examples, and can be appropriately set according to the multiplicity of incoming highways, the number of channels that can be processed by the LSI (DSP) to be used, and the like. Should.

  In the present embodiment, the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B are 4-channel serial interfaces (SI), and the two channel groups (# 0, # 1). It is provided corresponding to each channel group. Then, each performs demultiplexing according to the multiplicity of the corresponding channel group to extract the PB binary code of the channel group.

  For ease of explanation and ease of understanding, both the highway and signals transmitted through the highway will be described using the same symbol 2M-HW or the like.

  Hereinafter, processing by the processor control unit 11A, the digital signal processor (DSP # 0) 12A, and the digital signal processor (DSP # 1) 12B will be described in detail with reference to FIGS.

  A 2M highway (8 channels) signal which is an incoming highway signal is input to both the processor control unit 11A, the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B.

  As shown in FIG. 3, the processor control unit 11A receives a clock signal 2M-CLK (2.048 MHz) and a processing control signal CNTL (EN # 0, EN # 1) for controlling the digital signal processor. (DSP # 0) 12A and digital signal processor (DSP # 1) 12B.

  More specifically, as shown in the time chart of FIG. 4, the processor control unit 11 </ b> A has a period corresponding to 32 bits (8 bits × 4 CH) of the 2M clock signal CLK (2.048 MHz) 15.625 μs ( Enable signals # 0, # 1 (EN # 0, EN # 1) for enabling (operating) the digital signal processor (DSP # 0) 12A or the digital signal processor (DSP # 1) 12B alternately every microsecond) Are supplied to the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B as control signals (CNTL). That is, the enable signals # 0 and # 1 (EN # 0 and EN # 1) are input timings of the PB signal in the channel group to the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B. Is a processing control signal synchronized with the. Also, the enable signals # 0, # 1 (EN # 0, EN # 1) are transmitted at a predetermined sampling rate determined by a communication standard, device specification, etc. in which the digital PB receiver 10 is used, for example, a period of 8 kHz (frame period). : 125 μs) to enable the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B.

  In a period in which the enable signal # 0 (EN # 0) is at the “Low” level, the 4-channel digital signal processor (DSP # 0) 12A operates on the first channel group # 0 (CH0 to CH3) including four channels. Demultiplex processing and signal processing such as PB signal extraction are performed for each channel. Then, the digital signal processor (DSP # 0) 12A outputs the low group code (L1 to L4) and the high group code (H1 to H4) of the PB signal to the output terminals (D0 to D7) as 8-bit PB binary codes. Output. During a period when the digital signal processor (DSP # 0) 12A is enabled, the enable signal # 1 (EN # 1) of the digital signal processor (DSP # 1) 12B is set to the “High” level and is disabled. Yes.

  Next, the enable signal # 1 (EN # 1) is set to the “Low” level, and the 4-channel digital signal processor (DSP # 1) 12B performs demultiplexing processing on the second channel group # 1 (CH4 to CH7). In addition, signal processing such as PB signal extraction is performed for each channel. Then, the digital signal processor (DSP # 1) 12B outputs the low group code (L1 to L4) and the high group code (H1 to H4) of the PB signal to the output terminals (D0 to D7) as 8-bit PB binary codes. Output. During the period when the digital signal processor (DSP # 1) 12B is enabled, the enable signal # 1 (EN # 1) of the digital signal processor (DSP # 0) 12A is set to the “High” level, and is disabled. Yes.

  With this configuration and operation, the incoming highway signal (2M-HW: 8CH) data is equivalently divided into two 4-channel data and processed as 8-channel data by two LSIs (DSP). It becomes possible. In other words, the incoming highway signal is equivalently converted into two divided highway signals (two 2M-HW (4CH)), and the two divided highway signals (channel groups) are multiplexed in accordance with the respective multiplicity. It is possible to extract the PB binary code of each channel by performing separation.

  The PB binary code extraction process of the digital signal processor (DSP # 0) 12A will be described in more detail below with reference to FIGS.

  FIG. 5 is a diagram schematically showing generation and multiplexing of a PB (push button) signal on the calling side. On the calling side, the PB signal is generated by a specific frequency combination. That is, the PB signal for 12 dials “1-9, 0, *, #” can be obtained by combining the low group frequency (697, 770, 852, 941 Hz) and the high group frequency (1209, 1336, 1477, 1633 Hz). Generated. For example, when “5” is dialed on the line CH0, the PB signal is generated by a combination of signals of 770 Hz and 1336 Hz. Of the 16 combinations of the above frequencies, PB signals corresponding to “A, B, C, D” may be assigned to the remaining four combinations.

  The PB signals from the eight pushphones (channels CH0 to CH7) 210 to 217 are encoded / multiplexed by the encoding / multiplexing unit 22 using the above-described predetermined sampling rate (for example, 8 kHz), PCM encoded, and then the highway ( 2M-HW: 8CH) and time-division multiplexed in time slots.

  FIG. 6 is a block diagram schematically showing an example of a detailed configuration of the digital signal processor (DSP # 0) 12A. For the sake of explanation, each function is shown as a hardware configuration, but it is only necessary to have an equivalent function.

  In a state in which the digital signal processor (DSP # 0) 12A is enabled, processing is performed on the divided highway signals 2M-HW # 0 (CH0 to CH3) for four channels. That is, the highway signal 2M-HW # 0 (CH0 to CH3) is decoded and demultiplexed by the decoding / demultiplexing unit 25, and the PB signal of each channel (CH0 to CH3) is extracted. The obtained PB signal is separated into a low group frequency (697, 770, 852, 941 Hz) and a high group frequency (1209, 1336, 1477 Hz) by the digital filter / limiter circuit 26. Therefore, the digital filter / limiter circuit 26 includes a low group frequency filter / limiter circuit 26L and a high group frequency filter / limiter circuit 26H.

  The signals that have passed through the low group and high group frequency filter / limiter circuits 26L and 26H are filtered for each frequency by the band-pass filter (BPF) 27 corresponding to the low group and high group frequencies and supplied to the comparator 28. . The filtered signal is compared with a predetermined threshold level for each frequency in the comparator 28 and output as a binary code corresponding to the PB signal (hereinafter referred to as PB binary code). The PB binary code is composed of 8 bits (L1 to L4, H1 to H4).

  Specifically, for example, the PB signal corresponding to the dial “5” composed of a combination of signals of 770 Hz and 1336 Hz is converted to 770 Hz, low group and high group frequency filter / limiter circuits 26 L and 26 H, respectively. Separated into 1336Hz signal. These signals are supplied to the band pass filter (BPF) 27 and the comparator 28, and the bit (L2 = 770 Hz, H2 = 1336 Hz) corresponding to the signal becomes the “High” level (or “1”), and other bits. Becomes “Low” level (or “0”) (in the case of positive logic), and as shown in FIG. 7, PB binary code “0010010” (= LLHLLLHL) is output. Further, FIG. 7 shows, as an example, PB binary codes of the respective channels when the PB signals of CH1, CH2, and CH3 are “2”, “6”, and “7”, respectively.

  The PB binary code of the 4-channel divided highway signal 2M-HW # 0 (CH0 to CH3) is held in the answer register (ANS-REG # 0) 14A (FIG. 2) for each channel.

  The digital signal processor (DSP # 0) 12A outputs an SP (Signal Present) binary code indicating that the PB binary code exists in the answer register (ANS-REG # 0) 14A to the output terminal (D8). That is, the digital signal processor (DSP # 0) 12A stores the PB binary code in the answer register (ANS-REG # 0) 14A for each channel, and receives the PB binary code from the answer register (ANS-REG # 0) 14A. It is determined whether it is in a readable valid state or invalid, and each bit is output as a 4-bit binary code corresponding to each channel. That is, as shown in FIG. 8, the bit corresponding to the channel in which the valid PB binary code is held in the answer register (ANS-REG # 0) 14A is set to the “High” level (or “1”). FIG. 8 shows an SP code in a state where all PB binary codes of all channels (CH0 to CH3) are valid (all SP bits are “1”). The SP code is held in the SP code register (SP-REG # 0) 15A.

  The configuration and operation of the digital signal processor (DSP # 1) 12B are the same as those of the digital signal processor (DSP # 0) 12A described above, and the digital signal processor (DSP # 1) 12B has another divided highway signal 2M- HW # 1 (CH4 to CH7) demultiplexing processing and PB signal extraction processing are performed.

  That is, the PB binary code of the 4-channel divided highway signal 2M-HW # 1 (CH4 to CH7) is held in the answer register (ANS-REG # 1) 14B for each channel.

  In addition, the digital signal processor (DSP # 1) 12B has a PB binary code stored in the answer register (ANS-REG # 1) 14B, and can read the PB binary code from the answer register (ANS-REG # 1) 14B. Binary data (SP code) indicating whether it is in a state is output for each channel. That is, a 4-bit binary code for CH4 to CH7 is output. Then, the SP code is held in the SP code register (SP-REG # 1) 15B.

  The SP combiner 17 shown in FIG. 2 combines the contents of the SP code register (SP-REG # 0) 15A and the SP code register (SP-REG # 1) 15B, and as shown in FIG. Output as code (SP coupling data) to the data bus. More specifically, the SP coupling unit 17 includes gate circuits 31A and 31B having tristate outputs, and in response to an SP code read signal (SPREG read), an SP code register (SP-REG # 0) 15A. The data of the SP code register (SP-REG # 1) 15B is output to the eight continuous bus lines B24-31.

  The SP coupling unit 17 can be realized by other configurations. For example, as shown in FIG. 10, it can also be configured as a register that holds the SP coupling data. FIG. 10 shows a state in which the PB binary codes of all channels (CH0 to CH7) are valid (all bits are “1”).

  A reading / analysis unit (software interface) 41 provided in the control unit CPU 40 of a communication device, an inspection device or the like provided with the digital PB receiver 10 is an answer register when the SP code from the SP coupling unit 17 is valid. (ANS-REG) Read 8-channel PB binary code from 14A and 14B. That is, with the above-described configuration, data for four channels is processed by two LSIs (DSP # 0, # 1), respectively, but data for eight channels is processed in the same manner as when processing by one LSI (DSP). As a result, the processing result (PB data) can be read. Accordingly, an 8-channel device can be used without changing the interface on the incoming highway (2M-HW) side and the software interface for reading PB data.

  As described above, according to the present invention, a digital PB receiver can be easily configured using a digital signal processor LSI for processing a multiplicity smaller than the multiplicity of the incoming highway. Therefore, even when the highway multiplicity increases with the advancement of the system, a digital PB receiver can be configured using an existing LSI, so that the design flexibility and flexibility are excellent. .

  FIG. 11 is a block diagram schematically illustrating the configuration of the highway converter 11B of the digital PB receiver 10 according to the second embodiment.

  In the present embodiment, the highway converter 11B divides the incoming highway (2M-HW: 8CH) into two channel groups # 0 and # 1 (CH0 to CH3 and CH4 to CH7), thereby dividing the digital signal processor (DSP #). 0) 12A and the digital signal processor (DSP # 1) 12B.

  More specifically, the highway converter 11 extracts the 2M-clock signal CLK from the incoming highway (2M-HW: 8CH), and the digital signal processor (DSP # 0) 12A and the digital signal processor (DSP # 1) 12B. To supply. As shown in the time chart of FIG. 12, the highway converter 11 is based on the clock signal 2M-CLK, during which a signal related to the channel group # 0 (CH0 to CH3) is supplied (that is, the 2M clock signal CLK ( 2.048 MHz) for a period corresponding to 32 bits (8 bits × 4 CH) (15.625 μs)), the output switch SW # 0 is closed and the PB signals of the channel group # 0 (CH0 to CH3) are transmitted. The divided highway signal 2M-HW # 0 (4CH) is supplied to the digital signal processor (DSP # 0) 12A.

  Next, the output switch SW # 1 is closed only during a period in which signals relating to the channel group # 1 (CH4 to CH7) are supplied from the incoming highway (2M-HW: 8CH), and the channel group # 1 (CH4 to CH4) is closed. The PB signal of CH7) is supplied to the digital signal processor (DSP # 1) 12B as the divided highway signal 2M-HW # 1 (4CH).

  By this operation, as in the first embodiment, data for four channels is processed by two LSIs (DSPs # 0 and # 1), respectively, and processing similar to that performed by one LSI (DSP) is performed. It can be performed. Moreover, an 8-channel device can be used without changing the interface on the incoming highway (2M-HW) side and the software interface for reading PB data.

  As described above, according to the present invention, a digital PB receiver can be easily configured using a digital signal processor LSI for processing a multiplicity smaller than the multiplicity of the incoming highway. Therefore, even when the highway multiplicity increases with the advancement of the system, a digital PB receiver can be configured using an existing LSI, so that the design flexibility and flexibility are excellent. .

  It should be noted that the numerical values shown in the above-described embodiments are merely examples. For example, the number of incoming highways, the number of incoming highway divisions (the number of channel groups), the number of channels in each channel group, the frequency, the frame period, etc. are merely examples, and the processing capacity of the applied system and apparatus and the LSI used. It should be understood that the setting can be appropriately made according to the above.

It is a block diagram which shows the outline of a structure of the conventional digital PB receiver. It is a block diagram which shows typically the structure of the digital PB receiver by this invention. FIG. 3 is a block diagram schematically illustrating a configuration of a highway converter, a processor control unit, and digital signal processors (DSP # 0 and DSP # 1) in the first embodiment. 3 is a time chart illustrating processing by a processor control unit and digital signal processors (DSP # 0 and DSP # 1) in the first embodiment. It is a figure which shows typically about the production | generation and multiplexing of the PB (push button) signal in the calling side. It is a block diagram which shows typically an example of the detailed structure of a digital signal processor (DSP # 0). It is a figure which shows an example of the PB binary code of the division | segmentation highway signal 2M-HW # 0 (CH0-CH3) hold | maintained at an answer register (ANS-REG # 0). It is a figure which shows SP code hold | maintained at SP code register (SP-REG # 0) when the PB binary code of channel (CH0-CH3) is effective. It is a figure which shows an example of SP code register (SP-REG # 0, SP-REG # 1) and SP coupling | bond part, and SP coupling | bond part is comprised from the gate circuit which has a tristate output. It is a figure which shows a register value when an SP coupling | bond part is comprised as a register | resistor which hold | maintains SP coupling | bonding data, and PB binary code is effective. 6 is a block diagram schematically showing a configuration of a highway converter of a digital PB receiver that is Embodiment 2. FIG. Operation of the output switches SW # 0 and # 1 in the highway converter shown in FIG. 11, the divided highway signal 2M-HW # 0 (4CH) and # 1 from the highway converter to the digital signal processor (DSP # 0 and # 1) It is a time chart which shows the timing of supply of (4CH) and the process of a digital signal processor (DSP # 0, # 1).

Explanation of main part codes

10 Digital PB Receiver 11 Highway Converter 11A Processor Control Unit 11B Highway Converter 12A, 12B Digital Signal Processor 14A, 14B Answer Register (ANS-REG)
15A, 15B SP code register (SP-REG)
17 SP coupling part

Claims (7)

A digital PB receiver that performs demultiplexing of an incoming highway signal carrying a time-division multiplexed signal in which a predetermined number of channels are multiplexed, and extracts a PB code representing a digital PB signal included in the time-division multiplexed signal,
A highway converter for dividing the incoming highway signal and converting it into a plurality of divided highway signals;
A plurality of digital signal processors each of which is provided corresponding to the plurality of divided highway signals and performs demultiplexing according to the multiplicity of the corresponding divided highway signals to extract a PB binary code;
A plurality of PB code registers holding a divided highway PB binary code extracted by each of the plurality of digital signal processors;
And a read code combining unit that combines read effective binary codes indicating the read effective timing of each of the PB binary codes to generate a binary code having a bit arrangement corresponding to the input highway channel. PB receiver.  2. The digital PB receiver according to claim 1, further comprising a read valid binary code generation unit that determines a read valid timing of each of the PB binary codes and generates the read valid binary code.   The highway conversion unit divides the predetermined number of channels into a plurality of channel groups, generates a processing control signal synchronized with an input timing of each PB signal of the plurality of channel groups, and the plurality of digital signal processors The digital PB receiver according to claim 1 or 2, wherein a PB binary code of a corresponding channel group is extracted based on the processing control signal.   The said processing control signal is an enable signal which enables the digital signal processor corresponding to the said channel group to operate | move over the period when all the PB signals of each channel group are input. Digital PB receiver.  2. The digital PB receiver according to claim 1, wherein the read code combining unit includes a plurality of read code registers for holding read effective binary codes of the PB binary codes. 3.   The digital PB receiver according to claim 1, wherein the read code combination unit is a register that holds the generated binary code.   7. The digital PB receiver according to claim 1, wherein the incoming highway signal is divided into the divided highway signals without changing a transmission rate.

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