JP2708303B2 - FM multiplex broadcast receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM multiplex broadcast receiving circuit.

[0002]

SUMMARY OF THE INVENTION The present invention relates to a receiver circuit for FM multiplex broadcast signals, wherein the bit rate of the multiplex signal and the frequency of the stereo pilot signal have a perfect integer relationship of m: n, and the multiplexing on the receiver side is performed. This is an FM multiplex broadcast receiving circuit that reproduces a signal clock using a pilot signal and enables reliable clock reproduction.

[0003]

2. Description of the Related Art As a conventional technique, for example, an RDS adopting Manchester BPSK in a European standard system.
Also, there is a fixed reception type FM multiplex broadcasting which adopts QPSK in Japan, and in the case of synchronous detection for detecting these, first, a multiplex signal is stripped from a composite signal of the FM multiplex broadcasting signal by a band pass filter (BPF). Carrier regeneration is performed. Multiply this carrier signal and multiplex signal,
The digital signal is passed through a low-pass filter (LPF) to obtain a baseband signal output of the digital signal. The clock signal has been reproduced by the zero crossing point of the baseband signal and the PLL circuit.

In the case of delay detection, a multiplexed signal extracted from a composite signal of an FM multiplex broadcast signal is multiplied by a signal obtained by delaying the multiplexed signal by 1 bit and mutually phase-adjusted to obtain a baseband output of a digital signal. Get. The clock signal is reproduced from the eye pattern of the digital signal in the same manner as in the synchronous detection.

[0005]

In the above-mentioned prior art, when the level of the FM multiplex broadcast signal is low or when the broadcast signal is subject to interference such as multipath or fading, the S / N of the multiplex signal is reduced. It degrades, and the zero point of the eye pattern fluctuates greatly due to noise. As a result, the eye pattern and the clock signal may be out of synchronization.

An object of the present invention is to provide an FM multiplex broadcast receiving circuit capable of stably reproducing a clock signal by using a pilot signal having a large level and being easily reproduced even under such poor conditions. It is in.

[0007]

In order to achieve the above object, the present invention provides an FM multiplex broadcast receiving circuit in which the bit rate of the FM multiplex signal and the frequency of the stereo pilot signal have an integer ratio of m: n. Means for converting the frequency of the received stereo pilot signal and the bit synchronization signal reproduced from the FM multiplex signal into the same frequency,
A phase monitoring means for monitoring a state of coincidence or mismatch between the phases of the two signals after the conversion, and, in accordance with monitoring information from the phase monitoring means, the phase of the signal after frequency conversion of the stereo pilot signal is changed to the bit synchronization signal. And an FM multiplex broadcast receiving circuit comprising a clock signal reproducing circuit comprising a phase lock means for matching the phase of the frequency-converted signal.

[0008]

According to the present invention, in the receiving circuit for FM multiplex broadcast signals having the above structure, the bit rate of the multiplex signal and the frequency of the stereo pilot signal have a perfect integer relationship of m: n. The clock of the multiplex signal on the side is reproduced using the pilot signal.

[0009]

FIG. 1 shows a clock signal reproducing circuit which constitutes a part of an FM multiplex broadcast receiving circuit according to the present invention. Reference numeral 100 denotes a stereo composite signal, and 101 denotes a multiplex signal, which are separated from the reception signal of the FM multiplex broadcast signal. 102 is 19 kHz from the composite signal 100
19 kHz pilot signal extraction circuit for extracting a pilot signal; 103, a 19 kHz pilot signal extracted by the circuit 102; 104, a 1 / n counter for inputting the signal 103;
Hz signal. Reference numeral 107 denotes a gate circuit, and reference numeral 106 denotes a counter set signal from the gate circuit 107. Reference numeral 108 denotes a bit synchronization reproduction circuit including an early-rate circuit for reproducing a bit synchronization signal 109 from the multiplex signal 101;
Is a 1 / m counter for inputting the bit synchronization signal 109, 1
11 is obtained in 1 / m counter 110 output f _c / mk
Hz signal (f _c: Clock Frequency (kHz)), 112
Is a genlock detection circuit, 113 is a 19 / nkHz signal 1
05 and the phase of the phase and f _c / mkHz signal 111 is out control signal representing a (i.e., out of phase) it, 114 and the phase of the signal 111 of the signal 105 are matched (i.e. 115, a mismatch counter, 116, a match counter, 117, a reset signal indicating that the phase has been out of phase k 'times or more, and 118, indicating that the phase has been locked more than k times in a row. Control signal, 119 is an m-times circuit, 12
0 is a clock signal extracted from the pilot signal, 121
Is a gate circuit, and 122 is an output signal of the gate circuit 121 and represents a reproduced clock signal or the like.

Next, the operation of the clock signal reproducing circuit of FIG. 1 will be described. and a relationship of _{f p / f c = n /} m. f _p is a pilot signal frequency, is f _c is a multiple clock signal frequency. A pilot signal extraction circuit 102 extracts a 19 kHz pilot signal 103 from the stereo composite signal 100. f _c / 19 = m / n
, The 1 / n counter 104 determines that
/ NkHz signal 105 is generated. On the multiplexed signal side, the bit synchronization signal 109 is reproduced from the multiplexed signal 101 by the bit synchronization reproduction circuit 108 in a usual manner, and the 1 / m
The counter 110 converts the bit synchronization signal 109 into f _c
/ MkHz signal 111 is generated.

[0011] In search mode the first phase is not correct, since the phase of the 19 / nkHz and f _c / mkHz is not locked, gate circuit 107 is 1 / m counter 1
The set signal 106 based on the signal 111 from
The signal is input to the n counter 104, whereby the 1 / n counter 104 is set to an initial value such that the phases of the signal 105 and the signal 111 match. 112 is the signal 105
A genlock detection circuit for checking the phase of the signal 111 and the signal 111. When the two signals 105 and 111 are out of phase, the control signal 113 indicating the out of phase is sent to the count terminal of the mismatch counter 115 and the reset terminal of the match counter 116. When the phases of the two signals 105 and 111 match, a control signal 114 indicating phase lock is input to the reset terminal of the counter 115 and the count terminal of the counter 116. When the Sachimo over de match counter 116 counts continuously k times the control signal 114 indicating the phase-locked, by outputting a control signal 118 turns off the set signal 106 from the gate circuit 107, and the gate circuit 121, the signal A signal (19 / n) × mkHz signal 120 obtained by multiplying 105 by m by an m-fold circuit 119 is output as a clock signal 122, and the lock mode is set. In the lock mode, for example, multi-pass,
When the reception state changes due to fading or the like and the mismatch counter 115 counts the control signal 113 indicating the phase shift continuously for k ′ times, the match counter 116 is reset by the reset signal 117 output from the mismatch counter 115, The control signal 118 is turned off (k and k 'are arbitrary numbers). As a result, the search mode is set again. In this case, the gate circuit 121 outputs the bit synchronization signal 1 reproduced by the bit synchronization reproduction circuit 108.
09 is output as a normal clock signal. The gate circuit 107 outputs the set signal 106 as described above, and the search mode continues until the control signal 118 is output from the match counter 116. As described above, since the reproduction of the 19-kHz pilot signal having a large level is easy,
A stable clock signal can be reproduced.

Since the 1 / n counter 104 shown in FIG. 1 is set or reset at the timing of the set signal 106, there is a possibility that an error in the clock width of the 19 kHz pilot signal 103 may occur.
The circuit of FIG. 2 can be further added to the circuit of FIG. 2, the signal from the output terminal a of the 1 / n counter 104 is input to the input terminal b of the genlock detection circuit 112 in FIG.
, But instead, a circuit as shown in FIG. 2 is interposed between a and b. That is, the signal from the output terminal a of the 1 / n counter 104 is input to the phase detector 200. The phase detector 200 detects and outputs a phase difference between a signal from the output terminal a of the 1 / n counter 104 and a signal 111 from the 1 / m counter 110. 201 is a low-pass filter (L) that inputs a signal from the phase detector 200.
PF) and 202 are a voltage controlled oscillator (VCO) driven by the signal voltage from the LPF 201, and 203 is a VCO 202
1 / m counter for inputting a signal from the genlock detection circuit 112, and an output signal thereof is input to an input terminal b of the genlock detection circuit 112. The output signal of the VCO 202 is (m / n ) × 19 kHz
That is, since the signal corresponds to the clock signal extracted from the pilot signal, the signal can be directly input to the gate circuit 121 without the m-multiplying circuit 119 in FIG.

When the modulation system is QPSK or MSK, two sets of the same circuits as those in FIG. 1 are prepared and supplied for I and Q at the time of synchronous detection or 1-bit delay and 2-bit delay at the time of delay detection. Alternatively, the bit synchronous reproduction circuit 108 can supply the respective clock signals by setting the clock to be the same as the bit rate and reducing the clock rate to １ ／. The determination of I and Q can be made based on a specific pattern, for example, a framing code.

FIG. 3 shows a clock signal generating circuit on the transmitting side of the FM multiplex signal. Reference numeral 301 denotes a 1 / n counter for setting the 19 kHz pilot signal frequency of 300 to 1 / n;
Is a m-fold circuit to the output frequency of the 1 / n counter 301 to m times to output a clock signal f _c by _{f c = (m / n)} f p.

[0015]

According to the present invention, stable clock synchronization can be achieved even in a poor transmission path.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a clock signal reproducing circuit which is a part of an FM multiplex receiving circuit of the present invention.

FIG. 2 is a block diagram illustrating another example of a genlock circuit.

FIG. 3 is a block diagram illustrating a configuration of a transmission-side clock signal generation circuit.

[Explanation of symbols]

 Reference Signs List 102 pilot signal extraction circuit 104 1 / n counter 107 gate circuit 108 bit synchronous reproduction circuit 110 1 / m counter 112 genlock detection circuit 115 mismatch counter 116 match counter 119 m-times circuit 121 gate circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shigeki Moriyama 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tomohiro Saito 1-10-11 Kinuta, Setagaya-ku, Tokyo Within Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Satoshi Yamada 1-1-10 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-63-278430 (JP, A)

Claims (1)

(57) [Claims] An FM multiplex broadcast receiving circuit in which the bit rate of an FM multiplex signal and the frequency of a stereo pilot signal have an integer ratio relationship of m: n is reproduced from the frequency of the received stereo pilot signal and the FM multiplex signal. Means for converting each of the bit synchronization signals into the same frequency, phase monitoring means for monitoring the coincidence or non-coincidence of the phase between the two signals after the conversion, and the stereo pilot according to monitoring information from the phase monitoring means. FM signal comprising a clock signal reproducing circuit comprising: a phase lock means for matching the phase of the signal after frequency conversion of the signal to the phase of the signal after frequency conversion of the bit synchronization signal.
A multiplex broadcast receiving circuit.