JPH02137048U - - Google Patents

Info

Publication number
JPH02137048U
JPH02137048U JP4372789U JP4372789U JPH02137048U JP H02137048 U JPH02137048 U JP H02137048U JP 4372789 U JP4372789 U JP 4372789U JP 4372789 U JP4372789 U JP 4372789U JP H02137048 U JPH02137048 U JP H02137048U
Authority
JP
Japan
Prior art keywords
glass
melting point
ceramic base
chip
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4372789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4372789U priority Critical patent/JPH02137048U/ja
Publication of JPH02137048U publication Critical patent/JPH02137048U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本考案の第1及び
第2の実施例を示す断面図、第3図は従来のサー
デイツプICを示す断面図である。 1……セラミツクベース、2……セラミツクキ
ヤツプ、3……リードフレーム、4……封止硝子
、4a,4b……高融点硝子、5……ICチツプ
、6……接着硝子、6a,6b……中融点硝子、
7……ワイヤ、8……封止硝子、8a,8b……
低融点硝子。
1 and 2 are sectional views showing first and second embodiments of the present invention, respectively, and FIG. 3 is a sectional view showing a conventional circuit deep IC. 1... Ceramic base, 2... Ceramic cap, 3... Lead frame, 4... Sealing glass, 4a, 4b... High melting point glass, 5... IC chip, 6... Adhesive glass, 6a, 6b... ...medium melting point glass,
7... Wire, 8... Sealing glass, 8a, 8b...
Low melting point glass.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ICチツプを非晶質硝子で固着したセラミツク
ベースと、前記ICチツプの電極を外部へ導出す
るためのリードフレームと、前記セラミツクベー
スに被せるセラミツクキヤツプとを非晶質硝子で
気密封止するサーデイツプICにおいて、セラミ
ツクベース側の封止硝子は高融点硝子、セラミツ
クキヤツプ側の封止硝子は低融点硝子、ICチツ
プ固着用の接着硝子は前記二硝子の中間の融点を
有する硝子で構成されていることを特徴とするサ
ーデイツプIC。
This ceramic base IC includes a ceramic base on which an IC chip is fixed with amorphous glass, a lead frame for leading the electrodes of the IC chip to the outside, and a ceramic cap that covers the ceramic base, hermetically sealed with amorphous glass. In the above, the sealing glass on the ceramic base side is made of high melting point glass, the sealing glass on the ceramic cap side is made of low melting point glass, and the adhesive glass for fixing the IC chip is made of glass having a melting point between the above two glasses. A third IC featuring:
JP4372789U 1989-04-14 1989-04-14 Pending JPH02137048U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4372789U JPH02137048U (en) 1989-04-14 1989-04-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4372789U JPH02137048U (en) 1989-04-14 1989-04-14

Publications (1)

Publication Number Publication Date
JPH02137048U true JPH02137048U (en) 1990-11-15

Family

ID=31556384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4372789U Pending JPH02137048U (en) 1989-04-14 1989-04-14

Country Status (1)

Country Link
JP (1) JPH02137048U (en)

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