JPS6237930U - - Google Patents
Info
- Publication number
- JPS6237930U JPS6237930U JP12922885U JP12922885U JPS6237930U JP S6237930 U JPS6237930 U JP S6237930U JP 12922885 U JP12922885 U JP 12922885U JP 12922885 U JP12922885 U JP 12922885U JP S6237930 U JPS6237930 U JP S6237930U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- wire bonding
- glass sealing
- recess
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の実施例につき、第2図、第3
図は従来例につき、それぞれワイヤボンデイング
作業後の状況を示す要部断面図である。
1…リードフレーム、2…ワイヤ、3…パツケ
ージ半体、4…ガラス封止部分、5…半導体素子
、10…リードフレーム(本考案)、11…凹部
。
Figure 1 shows an embodiment of the present invention, Figures 2 and 3
The figures are sectional views of main parts of conventional examples showing the state after wire bonding work. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Wire, 3... Package half body, 4... Glass sealing part, 5... Semiconductor element, 10... Lead frame (this invention), 11... Recessed part.
Claims (1)
、リードフレームの先端部に、ワイヤボンデイン
グ用の凹部を設けたことを特徴とする半導体装置
用リードフレーム。 A lead frame for a semiconductor device, characterized in that the lead frame for a glass sealing case is provided with a recess for wire bonding at the tip of the lead frame.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12922885U JPS6237930U (en) | 1985-08-23 | 1985-08-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12922885U JPS6237930U (en) | 1985-08-23 | 1985-08-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6237930U true JPS6237930U (en) | 1987-03-06 |
Family
ID=31025618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12922885U Pending JPS6237930U (en) | 1985-08-23 | 1985-08-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6237930U (en) |
-
1985
- 1985-08-23 JP JP12922885U patent/JPS6237930U/ja active Pending