JPH0213476B2 - - Google Patents

Info

Publication number
JPH0213476B2
JPH0213476B2 JP55128024A JP12802480A JPH0213476B2 JP H0213476 B2 JPH0213476 B2 JP H0213476B2 JP 55128024 A JP55128024 A JP 55128024A JP 12802480 A JP12802480 A JP 12802480A JP H0213476 B2 JPH0213476 B2 JP H0213476B2
Authority
JP
Japan
Prior art keywords
holes
catalyst
epoxy resin
substrate
electroless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55128024A
Other languages
Japanese (ja)
Other versions
JPS5753999A (en
Inventor
Seiji Honma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi Condenser Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Condenser Co Ltd filed Critical Hitachi Condenser Co Ltd
Priority to JP12802480A priority Critical patent/JPS5753999A/en
Publication of JPS5753999A publication Critical patent/JPS5753999A/en
Publication of JPH0213476B2 publication Critical patent/JPH0213476B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は多層印刷配線板の製造方法に関する。
特には内層基板の上に触媒入りの樹脂を形成し、
この上に外層回路パターンを形成した多層印刷配
線板の製法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing multilayer printed wiring boards.
In particular, a catalyst-containing resin is formed on the inner layer substrate,
The present invention relates to a method for manufacturing a multilayer printed wiring board on which an outer layer circuit pattern is formed.

従来の技術 従来の多層印刷配線板の製造方法を第1図を用
いて説明する。
BACKGROUND ART A conventional method for manufacturing a multilayer printed wiring board will be explained with reference to FIG.

a図は内層用基板1であり、エポキシ樹脂2の
両面に銅箔3が接着されている。b図はこの内層
用基板1の銅箔3をエツチング処理してパターン
4が形成された工程を示し、c図は、多層印刷配
線板とするために、内層用基板1を中心部にお
き、両面にプリグレグ5をのせ、更にその外層と
して銅箔3が接着されたエポキシ樹脂2からなる
外層基板6を積層し、加熱加圧することによつて
一体化する工程を示し、d図はこの一体化した多
層積層板7の所定箇所にスルーホールの孔明け8
を行う工程を示し、e図で化学めつき処理におけ
る活性化のためのシーダ9処理を行い、f図で薄
い化学めつき処理により化学メツキ10が形成さ
れ、g図でめつきレジスト印刷11を行い、h図
で銅めつき12が施され、i図でめつきレジスト
11を除去し、j図でエツチング処理を行うと回
路パターン13とスルーホール14が形成され
る。従来は以上の工程を経て多層印刷配線板15
が製作されていた。
Figure a shows an inner layer substrate 1 in which copper foil 3 is bonded to both surfaces of an epoxy resin 2. Figure b shows a step in which the copper foil 3 of this inner layer substrate 1 is etched to form a pattern 4, and Figure c shows a process in which the inner layer substrate 1 is placed in the center in order to form a multilayer printed wiring board. Figure d shows the process of placing pregregs 5 on both sides, and then laminating an outer layer substrate 6 made of epoxy resin 2 to which copper foil 3 is bonded as an outer layer, and integrating by heating and pressurizing. Drill through holes 8 at predetermined locations on the multilayer laminate 7.
In figure e, seeder 9 treatment is performed for activation in chemical plating process, in figure f chemical plating 10 is formed by thin chemical plating process, and in figure g the plating resist printing 11 is performed. Then, copper plating 12 is applied as shown in Figure H, the plating resist 11 is removed as shown in Figure I, and etching is performed as shown in Figure J to form circuit patterns 13 and through holes 14. Conventionally, the multilayer printed wiring board 15 is manufactured through the above steps.
was being produced.

また、特公昭50−1424号において触媒入り基板
を用いた多層配線板が提案されているが、2枚の
基板を用い加熱加圧して製作されている。
Further, in Japanese Patent Publication No. 50-1424, a multilayer wiring board using a catalyst-containing substrate is proposed, but it is manufactured by heating and pressing two substrates.

発明が解決しようとする課題 従来の多層印刷配線は上記の如く工程数が多
く、特にプリグレグを用い一体化する際の加熱加
圧工程の作業が大がかりで面倒であつた。また、
スルーホールのための孔明け工程において、ドリ
ルでの切削時に発生する400℃以上の熱によつて
エポキシ樹脂2が溶解し、その一部が銅箔3の表
面を汚しスルーホールの遮電性を低下させること
があつた。
Problems to be Solved by the Invention Conventional multilayer printed wiring requires a large number of steps as described above, and in particular, the heating and pressing step when integrating using pre-regs is large-scale and troublesome. Also,
During the drilling process for through-holes, the epoxy resin 2 melts due to the heat of over 400°C generated during cutting with a drill, and some of it stains the surface of the copper foil 3, impairing the electrical insulation properties of the through-holes. There were times when it was lowered.

本発明はかゝる加熱加圧工程を行わずに多層印
刷配線板を製造する製造方法を提供する。
The present invention provides a manufacturing method for manufacturing a multilayer printed wiring board without performing such a heating and pressing step.

課題を解決するための手段 本発明の多層印刷配線板の製法は、基材として
触媒入りの絶縁板を用い、この基材の両面に触媒
入りの接着剤を塗布した内層基材を用い、先ずス
ルーホール用の孔明けを行い、めつきレジスト層
を形成し、無電解めつき浴に基板を浸漬して内層
回路パターンを形成し、触媒入りのエポキシ樹脂
を塗布し、再び外層のめつきレジスト層を形成
し、再度無電解めつき浴に基板を浸漬して外層回
路パターン及びスルーホールを形成するものであ
る。
Means for Solving the Problems The method for manufacturing a multilayer printed wiring board of the present invention uses an insulating board containing a catalyst as a base material, and an inner layer base material coated with an adhesive containing a catalyst on both sides of this base material. Drill holes for through holes, form a plating resist layer, immerse the board in an electroless plating bath to form an inner layer circuit pattern, apply catalyst-containing epoxy resin, and apply the outer layer plating resist again. After forming a layer, the substrate is immersed in an electroless plating bath again to form an outer layer circuit pattern and through holes.

作 用 本発明はプレス作業を伴わず、塗工作業で多層
印刷配線板を製造することができる製法であるか
ら、従来の製法に対し、工程が簡素化され、作業
能率が向上する。
Function The present invention is a manufacturing method that can manufacture a multilayer printed wiring board by coating without any press work, so the process is simplified and work efficiency is improved compared to conventional manufacturing methods.

実施例 本発明の実施例を第2図に基づき説明する。Example An embodiment of the present invention will be described based on FIG.

21は無電解めつき浴に対して触媒性を有する
ガラスエポキシ樹脂基材である。この基材21は
ガラス布又は紙を芯材にジシアンアミド、イミダ
ゾール化合物を硬化剤とし、ビスフエノールA型
エポキシ、フエノールノボラツク型エポキシを主
剤とするエポキシ樹脂ワニスを含浸させてガラス
布を製作し、このガラス布(又は紙)を複数枚積
層した後加熱加圧して絶縁板を製作する。
21 is a glass epoxy resin base material having catalytic properties in an electroless plating bath. The base material 21 is made by impregnating a glass cloth or paper with an epoxy resin varnish containing a bisphenol A type epoxy or a phenol novolak type epoxy as a main ingredient, using a dicyanamide or imidazole compound as a hardening agent, using a glass cloth or paper as a core material. A plurality of sheets of glass cloth (or paper) are laminated and then heated and pressed to produce an insulating plate.

この基材21の片面又は両面に触媒入りの接着
剤22を塗布したものを内層基板23として用
い、下記の工程で製作する(a図)。
This base material 21 coated with catalyst-containing adhesive 22 on one or both sides is used as the inner layer substrate 23, and is manufactured by the following steps (Figure a).

(a) この内層基板23の所定箇所に電子部品を挿
入するスルーホール用の貫通孔24を穿設する
孔明け工程(b図)。
(a) A drilling step (Figure b) of drilling a through hole 24 for a through hole into which an electronic component is inserted at a predetermined location of this inner layer substrate 23.

(b) この基板23の片面又は両面に、回路パター
ンを設けない箇所を、無電解金属めつき浴に対
して触媒性を有しないエポキシ樹脂25でめつ
きレジストを行う逆パターンめつきレジスト塗
布工程(c図)。
(b) A reverse pattern plating resist application step in which areas on one or both sides of this substrate 23 where no circuit pattern is provided are coated with an epoxy resin 25 that does not have catalytic properties in an electroless metal plating bath. (Figure c).

この触媒性を有しないエポキシ樹脂は、パラ
ジウムを含まない材料であつて、ジシアンジア
ミド、イミダゾール化合物を硬化剤とし、ビス
フエノールA型エポキシ、フエノールノボラツ
ク型エポキシを取材とするエポキシ樹脂を用い
る。
This non-catalytic epoxy resin is a material that does not contain palladium, uses a dicyandiamide or imidazole compound as a curing agent, and uses a bisphenol A type epoxy or a phenol novolac type epoxy as a material.

(c) この基板を公知の無電解金属めつき浴に浸漬
し、前記逆パターンめつきレジスト25が施さ
れていない内層回路パターン及び基板に穿設し
たスルーホール用の内壁部26に無電解銅めつ
き27を析出形成する無電解銅めつき工程(d
図)。
(c) This board is immersed in a known electroless metal plating bath, and electroless copper is applied to the inner layer circuit pattern on which the reverse pattern plating resist 25 is not applied and the inner wall portion 26 for the through hole formed in the board. Electroless copper plating step (d) in which plating 27 is formed by precipitation
figure).

(d) この無電解銅めつき27が形成された基板の
スルーホール26の近傍を除いて、その他の全
面に触媒入りエポキシ樹脂28で基板の表面を
被覆する触媒入りエポキシ樹脂の塗布工程(e
図)。
(d) A catalyst-containing epoxy resin application step (e
figure).

この触媒入りエポキシ樹脂28は、ジシアン
ジアミド、イミダゾール化合物を硬化剤とし、
ビスフエノールA型エポキシ、フエノールノボ
ラツク型エポキシを主剤とするエポキシ樹脂ワ
ニスの中に微細粒の無機質充填剤(アルミナ、
珪酸アルミニウム)にパラジウムを吸着したも
のを用いる。
This catalyst-containing epoxy resin 28 uses dicyandiamide and imidazole compounds as a curing agent,
Fine grained inorganic fillers (alumina,
Palladium is adsorbed onto aluminum silicate.

(e) このエポキシ樹脂28層の上に、再び触媒性
を有しないエポキシ樹脂29でめつきレジスト
層を設けるための印刷を行う逆パターンめつき
レジスト塗布工程(f図)。
(e) A reverse pattern plating resist application step (Figure f) in which printing is performed to form a plating resist layer again using a non-catalytic epoxy resin 29 on the epoxy resin 28 layer.

(f) 再び、この基板を無電解銅めつき浴に浸漬
し、前記の逆パターンめつきレジストが塗布さ
れていない外層パターン回路30及びスルーホ
ール31を形成する無電解銅めつき工程(g
図)。
(f) An electroless copper plating step (g
figure).

以上の工程を経て本発明の多層印刷配線板は製
作される。前記の製法においては、3層又は4層
の回路パターンが形成されたが、さらに(4)〜
(6)項の工程を繰返すことによつて、もつと多
層化した印刷配線板をうることができる。
The multilayer printed wiring board of the present invention is manufactured through the above steps. In the above manufacturing method, a three-layer or four-layer circuit pattern was formed, but in addition (4) to
By repeating the step (6), it is possible to obtain a multilayered printed wiring board.

発明の効果 本発明は以上に述べた多層印刷配線板の製法で
あつて、従来スルーホールの孔明けは多層に積層
した後に行うので、ドリルを用いて穿設しなけれ
ばならず、従つて孔明け時の熱によるエポキシ樹
脂が溶解した際の汚れを除去しなければならなか
つたが、本発明の製法の場合にはスルーホールの
部分に金属部が露出していないから、かゝる問題
は発生せず、しかも内層基板に最初の工程で孔明
けを行うので、ドリルを用いずパンチで孔明けが
できるから、プレスを用い一動作で孔明けを完了
でき能率的である。また、従来の多層印刷配線板
の製造方法と対比して工程が短縮化されているか
ら不良率も低減し、生産性が飛躍的に向上した。
Effects of the Invention The present invention is a method for manufacturing a multilayer printed wiring board as described above, and conventionally, the through-holes are formed after laminating multiple layers, so a drill must be used to make the holes. It was necessary to remove the dirt caused by the epoxy resin melting due to the heat at dawn, but in the case of the manufacturing method of the present invention, no metal part is exposed in the through-hole area, so this problem is avoided. This does not occur, and since the holes are made in the first step in the inner layer substrate, the holes can be made with a punch without using a drill, so the holes can be completed in one operation using a press, which is efficient. Additionally, since the process is shorter than in conventional multilayer printed wiring board manufacturing methods, the defect rate is also reduced and productivity is dramatically improved.

さらに、プレス方式(ラミネート方式)と異な
り、塗工方式を採用しているので、内層回路パタ
ーンに空洞部が発生せず、また加工歪による配線
板の変性も生じることがないので、電気特性に優
れ、信頼性が高い多層印刷配線板をうることがで
きる。
Furthermore, unlike the press method (laminate method), since a coating method is used, there are no cavities in the inner layer circuit pattern, and there is no deterioration of the wiring board due to processing distortion, so the electrical properties are improved. An excellent and highly reliable multilayer printed wiring board can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来製造法の工程を示す断面図であつ
て、a図は内層基板の断面図、b図はエツチング
処理を行つた断面図、c図は積層一体化した断面
図、d図は孔明け加工を示す断面図、e図はシー
ダ処理を行い内部を省略した断面図、f図は化学
メツキ処理を行つた断面図、g図はメツキレジス
ト処理した断面図、h図は電気銅メツキ処理した
断面図、i図はメツキレジストを除去した断面
図、j図はエツチング処理した断面図、第2図は
本発明の製法を説明するための断面図であり、a
図は内層基板の断面図、b図は孔明け加工を行つ
た断面図、c図は逆パターン印刷処理を行つた断
面図、d図は無電解銅メツキ処理した断面図、e
図は触媒入り樹脂をコートした断面図、f図は逆
パターン印刷処理を行つた断面図、g図は無電解
銅メツキ処理した断面図である。 図において、21は絶縁基板、22は触媒入り
接着剤、23は内層用基板、24は孔、25は逆
パターンマスク印刷、26はスルーホール内壁、
27は無電解銅メツキ、28は触媒入りエポキシ
樹脂、29は触媒性を有しない樹脂、30は回路
パターン、31はスルーホール。
Figure 1 is a cross-sectional view showing the steps of a conventional manufacturing method, in which figure a is a cross-sectional view of the inner layer substrate, figure b is a cross-sectional view after etching, figure c is a cross-sectional view of the integrated lamination, and figure d is a cross-sectional view of the inner layer substrate. A cross-sectional view showing the hole drilling process, figure e is a cross-sectional view after seeder treatment and the inside is omitted, figure f is a cross-sectional view after chemical plating treatment, figure g is a cross-sectional view after plating resist treatment, figure h is a cross-sectional view after electrolytic copper plating. Figure i is a cross-sectional view after the plating resist has been removed, Figure J is a cross-sectional view after the etching process, Figure 2 is a cross-sectional view for explaining the manufacturing method of the present invention,
The figure is a cross-sectional view of the inner layer substrate, figure b is a cross-sectional view after hole-drilling processing, figure c is a cross-sectional view after reverse pattern printing process, figure d is a cross-sectional view after electroless copper plating process, and figure e
The figure is a cross-sectional view after coating with catalyst-containing resin, the figure f is a cross-sectional view after reverse pattern printing, and the figure g is a cross-sectional view after electroless copper plating. In the figure, 21 is an insulating substrate, 22 is a catalyst-containing adhesive, 23 is an inner layer substrate, 24 is a hole, 25 is reverse pattern mask printing, 26 is an inner wall of a through hole,
27 is electroless copper plating, 28 is a catalyst-containing epoxy resin, 29 is a non-catalytic resin, 30 is a circuit pattern, and 31 is a through hole.

Claims (1)

【特許請求の範囲】 1 無電解金属めつき浴に対し触媒性を有する触
媒入り絶縁板を基材とし、この基材の片面又は両
面に触媒入りの接着剤が塗布されたものを内層基
板として用い、以下の工程を経て製作されること
を特徴とする多層印刷配線板の製法。 (a) この内層基板の所定箇所にスルーホール用の
孔を穿設する孔明け工程。 (b) この内層基板の片面又は両面に、回路パター
ンを設けない箇所を、無電解金属めつき浴に対
して触媒性を有しない材料でめつきレジストを
行う逆パターンめつきレジスト塗布工程。 (c) この基板を無電解金属めつき浴に浸漬し、前
記逆パターンめつきレジストが塗布されていな
い箇所及び孔明けされたスルーホールの内壁部
に無電解金属めつきを析出形成する無電解めつ
き工程。 (d) スルーホールの周辺を除く前面に触媒入りの
エポキシ樹脂を塗布する触媒入りエポキシ樹脂
塗布工程。 (e) 触媒入りエポキシ樹脂の表面に、再び回路パ
ターンを設けない箇所を、無電解金属めつき浴
に対して触媒性を有しない材料でめつきレジス
トを行う逆パターンめつきレジスト塗布工程。 (f) この基板を再度無電解金属めつき浴に浸漬
し、前記の逆パターンめつきレジストが塗布さ
れていない箇所及びスルーホールの部分に無電
解金属銅が析出形成される無電解銅めつき工
程。
[Scope of Claims] 1. An inner substrate having an insulating plate containing a catalyst that has catalytic properties in an electroless metal plating bath as a base material, and an adhesive containing a catalyst coated on one or both sides of this base material. A method for manufacturing a multilayer printed wiring board, characterized in that it is manufactured using the following steps. (a) A hole-drilling process in which holes for through-holes are drilled at predetermined locations on this inner layer substrate. (b) A reverse pattern plating resist application step in which areas on one or both sides of this inner layer substrate where no circuit pattern is provided are coated with a material that does not have catalytic properties in an electroless metal plating bath. (c) This substrate is immersed in an electroless metal plating bath, and electroless metal plating is deposited and formed on the areas where the reverse pattern plating resist is not applied and on the inner walls of the drilled through holes. Plating process. (d) Catalyst-containing epoxy resin application process in which catalyst-containing epoxy resin is applied to the front surface except around the through-holes. (e) A reverse pattern plating resist application process in which areas on the surface of the catalyst-containing epoxy resin where no circuit pattern is to be provided are coated with a material that does not have catalytic properties in an electroless metal plating bath. (f) Electroless copper plating in which this substrate is immersed in an electroless metal plating bath again, and electroless metallic copper is deposited and formed in the areas where the reverse pattern plating resist is not applied and in the through holes. Process.
JP12802480A 1980-09-17 1980-09-17 TASOINSATSUHAISENBANNOSEIHO Granted JPS5753999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12802480A JPS5753999A (en) 1980-09-17 1980-09-17 TASOINSATSUHAISENBANNOSEIHO

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12802480A JPS5753999A (en) 1980-09-17 1980-09-17 TASOINSATSUHAISENBANNOSEIHO

Publications (2)

Publication Number Publication Date
JPS5753999A JPS5753999A (en) 1982-03-31
JPH0213476B2 true JPH0213476B2 (en) 1990-04-04

Family

ID=14974596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12802480A Granted JPS5753999A (en) 1980-09-17 1980-09-17 TASOINSATSUHAISENBANNOSEIHO

Country Status (1)

Country Link
JP (1) JPS5753999A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501424A (en) * 1973-03-14 1975-01-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501424A (en) * 1973-03-14 1975-01-09

Also Published As

Publication number Publication date
JPS5753999A (en) 1982-03-31

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