JPS5939096A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS5939096A
JPS5939096A JP14967082A JP14967082A JPS5939096A JP S5939096 A JPS5939096 A JP S5939096A JP 14967082 A JP14967082 A JP 14967082A JP 14967082 A JP14967082 A JP 14967082A JP S5939096 A JPS5939096 A JP S5939096A
Authority
JP
Japan
Prior art keywords
laminate
plating
adhesive layer
conductor
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14967082A
Other languages
Japanese (ja)
Inventor
坂田 寛
一博 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14967082A priority Critical patent/JPS5939096A/en
Publication of JPS5939096A publication Critical patent/JPS5939096A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 関するものである。[Detailed description of the invention] Industrial applications It is related to

従来例の構成とその問題点 従来より多層印刷配線板はコンピュータ機器の発達に伴
いその需要が著しく伸長してきており、電子機器の機能
アップにより、今後、さらにその需要の伸びが期待され
るものである。しかし、その製造方法が複雑でしかも高
価な材料を使用しているだめにどうしてもコストアップ
になり、ユーザーの要望に応え得るものでなかった。そ
こで、捷ず従来の製造方法を下記に説明する。
Conventional configurations and problems The demand for multilayer printed wiring boards has been increasing significantly with the development of computer equipment, and further growth in demand is expected in the future as the functionality of electronic equipment improves. be. However, since the manufacturing method is complicated and expensive materials are used, the cost inevitably increases, and it has not been possible to meet the demands of users. Therefore, the conventional manufacturing method will be explained below.

捷ず、銅張したガラス布基材エポキシ樹脂の内層積層板
をエツチングして、所望の回路を形成し内層基板とし、
この内層基板の表裏にガラス布基材エポキシ樹脂積層板
からなる未硬化の接着剤層であるプリプレグを介して、
両面銅張ガラス布基材エポキシ樹脂積層板を加熱加圧し
、一体化した後、ドリル加工等で透孔を穿設する。次に
前記透孔に無電解銅めっきを析出するだめの、活性化処
理を行いその後無電解銅めっきを行いさらに電気銅めっ
きを行い、透孔壁にスルホール接続を確実に行い得るだ
けの銅め・き厚(例えば358を施していた。その後、
基板の表面にドライフィルムレジスト例えばリストン(
米国テユポン社の商標)を用いて、テンティングと呼ば
れる方式でエツチングレジスト層を形成し、エツチング
して第1図に示すように、所望の外層導体回路1、およ
びスルホールめっき2、内層回路3を有する多層印刷配
線板を得ていた。
Without cutting, the inner layer laminate of the copper-clad glass cloth base epoxy resin was etched to form the desired circuit and serve as the inner layer board.
Through prepreg, which is an uncured adhesive layer made of glass cloth base epoxy resin laminate, on the front and back of this inner layer substrate,
After heating and pressurizing the double-sided copper-clad glass cloth base epoxy resin laminate to integrate it, through holes are made by drilling or the like. Next, an activation treatment is performed to deposit electroless copper plating in the through hole, followed by electroless copper plating and further electrolytic copper plating, so that the copper plating is sufficient to ensure through-hole connection to the through hole wall.・Thickness (for example, 358 was applied. After that,
Apply a dry film resist to the surface of the substrate, such as Liston (
Using a method called tenting, an etching resist layer is formed using a method called tenting (trademark of Teyupon Co., Ltd., USA), and the desired outer layer conductor circuit 1, through-hole plating 2, and inner layer circuit 3 are etched as shown in FIG. A multilayer printed wiring board was obtained.

しかしながら、この製造方法では無電解銅めっきと電気
銅めっきが併用になるという欠点があるほか、電気銅め
っきで所望とする導体厚さを形成する厚付けを行うだめ
に基板表裏のめっき厚がばらつき、導体中CL20 m
m以下になると均一エツチングしても、厚さのバラツキ
により均一な導体l〕が得られないという問題があった
However, this manufacturing method has the disadvantage that electroless copper plating and electrolytic copper plating are used together, and the plating thickness on the front and back of the board is uneven because electrolytic copper plating cannot be used to thicken the conductor to the desired thickness. , conductor medium CL20 m
When the thickness is less than m, there is a problem that even if uniform etching is performed, a uniform conductor cannot be obtained due to variations in thickness.

寸だ、表面銅箔と基材間には、接着剤がなくいわゆる銅
箔とカラス布基材エポキシ樹脂層は、暴利表層のエポキ
シ樹脂を接着剤層に活用しているために完成後、半田付
、および使用環境を想定した過酷な熱衝撃試験でスルホ
ールめっきと表面導体、欺よびスルホールめっきと内層
導体間でスルホールクラックと呼ばれるヒビが発生しや
すいという問題があった。
Unfortunately, there is no adhesive between the surface copper foil and the base material, so the so-called copper foil and glass cloth base epoxy resin layer uses the epoxy resin on the surface layer for the adhesive layer, so it is difficult to solder after completion. There was a problem in that cracks called through-hole cracks were likely to occur between the through-hole plating and the surface conductor, and between the through-hole plating and the inner layer conductor during severe thermal shock tests assuming the application and usage environment.

このだめに、熱膨張率の小さいガラス布基材エポキシ樹
脂積層板のみしか実用できないという欠点があり、以上
の理由により設備投資が膨大で、かつ材料コストが高く
つき、完成品の価格が高くなるという問題があった。
This disadvantage has the disadvantage that only glass cloth-based epoxy resin laminates with a small coefficient of thermal expansion can be put to practical use.For the reasons mentioned above, capital investment is enormous, material costs are high, and the price of the finished product is high. There was a problem.

発明の目的 本発明は上記欠点に鑑み、スルーホール接続の信頼性が
優れ、しかも容易にかつ安価に製造できる多層印刷配線
板の製造方法を提供するものである。
OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a multilayer printed wiring board that has excellent through-hole connection reliability and can be manufactured easily and at low cost.

発明の構成 上記目的を達成するために、本発明は、内層積層板に回
路が形成された内層基板の表裏に未硬化の接着剤層を介
して外層積層板を加熱加圧成形し、その外層積層板の表
面にニトリルブタジェンラバー等の接着剤層を形成し、
さらにその表面にめっきレジスト層を形成し所望の位置
に透孔を穿設し、その後無電解銅めっき液に浸漬して銅
導体回路を形成するものである。
Structure of the Invention In order to achieve the above-mentioned object, the present invention heats and press-forms an outer layer laminate with an uncured adhesive layer interposed on the front and back surfaces of an inner layer substrate on which a circuit is formed. An adhesive layer such as nitrile butadiene rubber is formed on the surface of the laminate,
Further, a plating resist layer is formed on the surface, through-holes are bored at desired positions, and the copper conductor circuit is then immersed in an electroless copper plating solution.

無電解銅めっきのみを利用することにより一度に多量の
多層印刷配線板に銅めっきできるだめ安価に製造するこ
とができ、ニトリルブタジェンラバー等の接着剤層を介
して銅めっきされており、その接着剤層が銅めっきへの
衝撃を吸収する働きをし、スルホールクラックが発生し
にくく、スルーホール接続の信頼性が非常1こ優れたも
のである。
By using only electroless copper plating, a large amount of multilayer printed wiring boards can be plated at a low cost, and the copper plating is done through an adhesive layer such as nitrile butadiene rubber. The adhesive layer acts to absorb impact on the copper plating, making through-hole cracks less likely to occur, and the reliability of through-hole connections is extremely high.

実施例の説明 以下本発明の一実施例における多層印刷配線板の製造方
法について図面とともに説明する。
DESCRIPTION OF EMBODIMENTS A method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention will be described below with reference to the drawings.

第2図1こ示すよう1;厚さ35μmの銅箔回路4を張
った厚さ0・2mmの両面鋼張紙基材エポキシ樹脂の内
層積層板5を所望の回路パターンにエツチングし、内層
基板5aとする。
As shown in Fig. 2, 1; an inner layer laminate 5 made of double-sided steel-clad paper base epoxy resin with a thickness of 0.2 mm and covered with a copper foil circuit 4 with a thickness of 35 μm is etched into a desired circuit pattern, and an inner layer board is formed. 5a.

次に第3図に示すよう12内層基板5乙の表裏1;それ
ぞれ厚さ0.2πmの紙基材エポキシ樹脂積層板の一種
であるプリプレグ6および厚さ0.6闘の紙基材エポキ
シ樹脂の外層積層板子を熱プレスを用い、温度180°
C2圧力80kg/cイで1時間加熱加圧成形する。こ
の時、プリプレグ6ば、エポキシ樹脂が完全1こは硬化
していないすなわち硬化反応がり一ステージのものを使
用し、内層基板52Lと外層積層板6との接着剤層とす
る。
Next, as shown in Fig. 3, 12 inner layer substrates 5, front and back 1; prepreg 6, which is a type of paper-based epoxy resin laminate, each having a thickness of 0.2 πm and a paper-based epoxy resin having a thickness of 0.6 πm. Using a heat press, heat the outer layer of the laminated plate at a temperature of 180°.
Heat and pressure mold at a C2 pressure of 80 kg/c for 1 hour. At this time, the prepreg 6 used is one in which the epoxy resin is not completely cured, that is, the curing reaction is at one stage, and is used as the adhesive layer between the inner layer substrate 52L and the outer layer laminate 6.

このよう1′−シて一体成形された内層1′−銅箔回路
4を有する外層積層板子の表面に、第4図に示すように
ニトリルブタジェンラバー8をカーテンコーターで厚さ
3Qμm塗布し硬化させる。その後エボキン系のめっき
レジスト9を逆パターン状にスクリーン印刷し硬化させ
、さらにプレス打抜きにてめっきの必要な透孔10を穿
設する。上述の場合において外層積層板7、内層基板5
aおよびプリプレグ6およびニトリルツクジエンラバー
8中に塩化パラジウムを分散させ無電解銅めっきの核を
前もって形成しておけば、以下の無電解銅めっきの前処
理での活性化処理を省略することが可能で、工程を短縮
することができる。
As shown in FIG. 4, nitrile butadiene rubber 8 is coated to a thickness of 3Q μm with a curtain coater on the surface of the outer layer laminated board having the inner layer 1′ and the copper foil circuit 4 integrally molded in this way and cured. let Thereafter, an Evokin-based plating resist 9 is screen printed in a reverse pattern and cured, and further, through-holes 10 that require plating are punched out by press punching. In the above case, the outer layer laminate 7 and the inner layer substrate 5
If the nuclei for electroless copper plating are formed in advance by dispersing palladium chloride in a, the prepreg 6, and the nitrile rubber 8, it is possible to omit the activation treatment in the pretreatment for electroless copper plating below. possible, and the process can be shortened.

次に前記工程により形成された基板をクロム酸水溶液(
図示しない)に浸漬し、外層積層板7の上のニトリルブ
ダジエンラバ−8の粗化、および透孔10内の銅箔回路
4の端面の洗浄を行った後、無電解銅めっき液(図示し
ない)中に浸漬し、第5図に示すように厚さ36μmの
スルホールめっき導体11、および外層導体12を形成
する。
Next, the substrate formed by the above process was mixed with a chromic acid aqueous solution (
After roughening the nitrile butadiene rubber 8 on the outer layer laminate 7 and cleaning the end face of the copper foil circuit 4 in the through hole 10, the electroless copper plating solution (not shown) is applied. ) to form a through-hole plated conductor 11 with a thickness of 36 μm and an outer layer conductor 12 as shown in FIG.

その後ソルダーレジスト印刷、部品配置図印刷仕上処理
等、通常の印刷配線板に必要とされる後処理を行い多層
配線板を得る。
Thereafter, post-processing required for ordinary printed wiring boards, such as solder resist printing and component layout printing finishing processing, is performed to obtain a multilayer wiring board.

以下本発明の他の実施例における多層配線板の製造方法
について第6図〜第9図の図面とともに説明する。
A method of manufacturing a multilayer wiring board according to another embodiment of the present invention will be described below with reference to the drawings of FIGS. 6 to 9.

前記実施例に記す紙基材エポキシ樹脂積層板に代えて、
それぞれ内層積層板13、プリプレグ14、外層積層板
15にガラス布基材エポキシ樹脂積層板を用いた。
Instead of the paper-based epoxy resin laminate described in the above example,
Glass cloth-based epoxy resin laminates were used for the inner layer laminate 13, the prepreg 14, and the outer layer laminate 15, respectively.

前記実施例と同様の工程で第6図に示すように一体成形
され内層回路を有するガラス布基材エポキシ樹脂の外層
積層板15上に厚さ30μmの二l・リルブダジエンラ
バー8をカーテンコーターで塗布し硬化させた後、スル
ホールめっきの必要な透孔16をドリル加工にて穿設す
る。
As shown in FIG. 6 in the same process as in the previous example, a curtain coater was used to apply a 30 μm thick 2L lilbudadiene rubber 8 on the outer layer laminate 15 of the glass cloth base epoxy resin which was integrally molded and had an inner layer circuit. After coating and curing, through-holes 16 requiring through-hole plating are drilled.

次に第7図に示すように、前記積層板をクロム酸水溶液
(図示し々い)中に浸漬し積層板上のニトリルブタジェ
ンラバー8の表面および透孔16内の銅箔回路4の端面
に付着したドリル加工によるエポキシスミアを溶解除去
し、さらに塩化パラジウム−塩化錫水溶液に浸漬し、無
電解銅めっきを析出させるためのめっき核を析出させた
後、無電解銅めっき液(図示し々い)中に浸漬しスルボ
ール壁面および積層板の外層表面に厚さ35μmの導体
17を形成する。
Next, as shown in FIG. 7, the laminate is immersed in a chromic acid aqueous solution (not shown), and the surface of the nitrile butadiene rubber 8 on the laminate and the end face of the copper foil circuit 4 in the through hole 16 are removed. After dissolving and removing the epoxy smear adhering to the surface by drilling, it is further immersed in a palladium chloride-tin chloride aqueous solution to precipitate plating nuclei for depositing electroless copper plating. (b) A conductor 17 with a thickness of 35 μm is formed on the wall surface of the Surbol and the outer layer surface of the laminate.

次に第8図に示すように、前記全面めっきを施しだ内層
回路を有する積層板表面にエツチングレジスト18を形
成する。この方法としては、孔埋め法と呼ばれるエツチ
ングレジ名トをスルホールめっき孔に充填させ、外層部
分はスクリーン印刷法でエツチングレジストを回路状に
印刷形成する方法が工数が少々く、材料費も安価ですむ
特長があるが、0.1〜0.271[の導体を所望する
場合は、写真印刷法でエツチングレジストを形成しても
よい。
Next, as shown in FIG. 8, an etching resist 18 is formed on the surface of the laminate having the inner layer circuit which has been plated on the entire surface. This method involves filling the through-hole plating holes with an etching resist called the hole-filling method, and printing the etching resist into a circuit shape using screen printing for the outer layer, which requires less man-hours and costs less materials. However, if a conductor of 0.1 to 0.271 is desired, an etching resist may be formed by a photo printing method.

次に前記基板を塩化第二銅液でエツチングし、第9図に
示すように内層に銅箔回路4、スルポールめっき導体1
1、および外層導体12を有する多層印刷配線板を得る
。もちろん前記実施例に示しだソルダーレジスト印刷等
、通常の印刷配線板に必要とされる処理を行うことはい
う寸でもない。
Next, the board is etched with a cupric chloride solution, and as shown in FIG.
1 and an outer layer conductor 12 is obtained. Of course, it is beyond the scope of the invention to perform processes required for ordinary printed wiring boards, such as solder resist printing as shown in the above embodiments.

発明の効果 以上のように本発明は外層積層板と表面導体との間に弾
性のあるニトリルブタジェンラバーが接着剤層として存
在するために、熱衝撃時のダンパーとして働き、スルホ
ールめっき導体と外層導体との接続信頼性が高く、さら
に無電解銅めっきにより厚さの均一々表面導体が得られ
るだめ、高密度回路を形成することも可能で、さらに基
材の材質も用途に応じたものが選択可能なだめ、価格対
応力もあり、量産性も高く、捷だ必要に応じて完全アデ
ィティブ法、および均一な厚さの無電解全面めっきをエ
ツチングして導体回路を形成するエツチング併用法のい
ずれかが選択できるため、その工業的価値は犬なるもの
がある。
Effects of the Invention As described above, in the present invention, since the elastic nitrile butadiene rubber is present as an adhesive layer between the outer layer laminate and the surface conductor, it acts as a damper during thermal shock, and the through-hole plated conductor and outer layer The connection with the conductor is highly reliable, and electroless copper plating provides a surface conductor with a uniform thickness, making it possible to form high-density circuits, and the material of the base material can be selected according to the application. It is possible to choose between a fully additive method, which is highly cost-effective, and highly suitable for mass production, depending on the need for cutting, or a combined method of etching, which forms a conductor circuit by etching electroless full-surface plating with a uniform thickness. Because it can be selected, its industrial value is significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多層印刷配線板の構造を示す断面図、第
2図〜第6図は本発明の一実施例における製造過程を示
す工程図、第6図〜第9図は本発明の他の実施例におけ
る製造過程を示す工程図である。 4・・・・・・銅箔回路、5,13・・・・・・内層積
層板、5a゛゛・・・内層基板、6,14・・・・・・
プリプレグ、7115・・・・・・外層積層板、8・・
・・・・ニトリルブタジェンラバー、9・・・・・・め
っきレジスト、10.16・旧・・透孔、11・・・・
・・スルーホールめっき導体、12・・団・外層導体、
18・・・・・・エツチングレジスト。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第3
図 第4図 第5図 第6図 δ 第7図 図 しくl。 N\ 旨 δ 図
FIG. 1 is a sectional view showing the structure of a conventional multilayer printed wiring board, FIGS. 2 to 6 are process diagrams showing the manufacturing process in an embodiment of the present invention, and FIGS. 6 to 9 are It is a process diagram which shows the manufacturing process in another Example. 4... Copper foil circuit, 5, 13... Inner layer laminate, 5a゛゛... Inner layer board, 6, 14...
Prepreg, 7115... Outer layer laminate, 8...
...Nitrile butadiene rubber, 9...Plating resist, 10.16 Old...Through hole, 11...
...Through-hole plated conductor, 12...Group/outer layer conductor,
18...Etching resist. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4 Figure 5 Figure 6 Figure 6 Figure 7 Figure l. N\ Umami δ Figure

Claims (4)

【特許請求の範囲】[Claims] (1)銅張した内層積層板をエツチングして所望の回路
を形成した内層基板の表裏に未硬化の接着剤層を介して
銅箔の被着していない外層積層板を加熱加圧成形し、一
体化した後、前記外層積層板の表面に二トリルブタジエ
ンラハー等の接着剤層を形成し、さらに所望の回路パタ
ーン以外の表面にめっきレジストを形成し、所望の位置
に透孔を穿設した後、無電解銅めっき液に浸漬して銅導
体回路を形成することを特徴とする多層印刷配線板の製
造方法。
(1) The copper-clad inner laminate is etched to form the desired circuit, and the outer laminate, which is not coated with copper foil, is heated and pressure-molded with an uncured adhesive layer interposed between the front and back sides of the inner layer board. After the integration, an adhesive layer such as nitrile butadiene laher is formed on the surface of the outer laminate, a plating resist is formed on the surface other than the desired circuit pattern, and through holes are drilled at desired positions. 1. A method for manufacturing a multilayer printed wiring board, comprising: forming a copper conductor circuit by immersing it in an electroless copper plating solution.
(2)内層積層板および外層積層板としてガラス布基材
エポキシ樹脂2紙暴利エポキシ樹脂、捷たは紙基材フェ
ノール樹脂を用、いることを特徴とする特許請求の範囲
第1項記載の多層印刷配線板の製造方法。
(2) The multilayer according to claim 1, characterized in that the inner layer laminate and the outer layer laminate are made of glass cloth-based epoxy resin, paper-based epoxy resin, paper-based phenolic resin, or paper-based phenol resin. A method for manufacturing printed wiring boards.
(3)ニトリルブタジェンラバー等の接着剤層、内層基
板および外層積層板中に、塩化パラジウムからなるめっ
き核を分散させることを特徴とする特許請求の範囲第1
項記載の多層印刷配線板の製造方法。
(3) Claim 1, characterized in that plating nuclei made of palladium chloride are dispersed in an adhesive layer such as nitrile butadiene rubber, an inner layer substrate, and an outer layer laminate.
A method for producing a multilayer printed wiring board as described in Section 1.
(4)ニトリルブタジェンラバー等の接着剤層上、およ
び透孔全面に無電解銅めっきで導体を形成した後、所望
の回路状にエツチングレジストを刷配線板の製造方法。
(4) A method for producing a wiring board, in which a conductor is formed on an adhesive layer such as nitrile butadiene rubber and the entire surface of the through hole by electroless copper plating, and then an etching resist is printed in a desired circuit shape.
JP14967082A 1982-08-27 1982-08-27 Method of producing multilayer printed circuit board Pending JPS5939096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14967082A JPS5939096A (en) 1982-08-27 1982-08-27 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14967082A JPS5939096A (en) 1982-08-27 1982-08-27 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS5939096A true JPS5939096A (en) 1984-03-03

Family

ID=15480260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14967082A Pending JPS5939096A (en) 1982-08-27 1982-08-27 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5939096A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525880U (en) * 1978-08-11 1980-02-19
JPS61121496A (en) * 1984-11-19 1986-06-09 東芝ケミカル株式会社 Multilayer printed wiring board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5412457A (en) * 1977-06-30 1979-01-30 Matsushita Electric Works Ltd Multiilayer printed wiring board and method of manufacturing same
JPS5426471A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Method of manufacturing multiilayer printed wiring board
JPS5426472A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Method of manufacturing multiilayer printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5412457A (en) * 1977-06-30 1979-01-30 Matsushita Electric Works Ltd Multiilayer printed wiring board and method of manufacturing same
JPS5426471A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Method of manufacturing multiilayer printed wiring board
JPS5426472A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Method of manufacturing multiilayer printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525880U (en) * 1978-08-11 1980-02-19
JPS5823295Y2 (en) * 1978-08-11 1983-05-18 株式会社飛弾製作所 Head-butt prevention device for bar-shaped cosmetic containers
JPS61121496A (en) * 1984-11-19 1986-06-09 東芝ケミカル株式会社 Multilayer printed wiring board
JPH0510840B2 (en) * 1984-11-19 1993-02-10 Toshiba Chem Prod

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