JPH0212826A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0212826A JPH0212826A JP16287688A JP16287688A JPH0212826A JP H0212826 A JPH0212826 A JP H0212826A JP 16287688 A JP16287688 A JP 16287688A JP 16287688 A JP16287688 A JP 16287688A JP H0212826 A JPH0212826 A JP H0212826A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- wiring material
- taper
- stuck
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 3
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- 150000002736 metal compounds Chemical class 0.000 claims abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明は半導体装置の製造方法に関し、線層の形成方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a line layer.
殊に配
[従来の技術]
従来の技術は、配線材を基板全面に被着させ、該配線材
上に、フォトリングラフイーを用いてレジストをパター
ニングし、該レジストをマスクにエツチングするもので
あった。In particular, prior art technology involves depositing a wiring material over the entire surface of a substrate, patterning a resist on the wiring material using photophosphorography, and etching the resist into a mask. there were.
[発明が解決しようとする課題]
従来技術で配線材を形成し、その上に絶縁膜を堆積した
断面構造を第1図に示す。図かられかるように、配線間
の距離が、微細化により短かくなると、上層の絶縁膜が
埋まりにくくなり、極端な場合には、空孔ができたりす
るようになる。このような空孔は、素子の信頼性上好し
くなく、微細化の制約となっている。最近は、配線材を
エツチングする時、一部ウエツ)エッチを用いて配線材
上部にテーパーを付して防ぐ方法もとられているしかし
この方法は、制御の点で問題があるのと配線材が微細化
されると上部レジストが、エツチング中に飛んでしまう
という間層がある。またドライエツチング法により配線
材にテーパーを付ける方法もあるが、現在の装置では、
不可能といわざるを得ない。本発明はかかる従来技術の
欠点を克服し信頼性の高い構造を与えるものである[課
題を解決するための手段]
本発明は、ドライエツチング法に於いて、金属等の配線
材のテーパーツチングはかなり困難な反面酸化S1膜や
窒化S1膜等は比較的容易にテーバエツチングが可能で
あるという事実を用いる。[Problems to be Solved by the Invention] FIG. 1 shows a cross-sectional structure in which a wiring material is formed using a conventional technique and an insulating film is deposited thereon. As can be seen from the figure, as the distance between interconnects becomes shorter due to miniaturization, it becomes difficult to fill the upper insulating film, and in extreme cases, holes may be formed. Such holes are unfavorable in terms of device reliability and are a constraint on miniaturization. Recently, when etching wiring materials, a method has been used to prevent this by applying a taper to the top of the wiring material using some wet etching. However, this method has problems in terms of control and As the resist becomes finer, there is a problem in which the upper resist is blown off during etching. There is also a method of tapering the wiring material using the dry etching method, but with current equipment,
I have to say it's impossible. The present invention overcomes the drawbacks of the prior art and provides a highly reliable structure. [Means for Solving the Problems] The present invention provides a method for forming a tapered part chisel of wiring materials such as metal in a dry etching method. This is based on the fact that, while it is quite difficult to perform Taber etching on oxidized S1 films and nitrided S1 films, it is relatively easy to perform Taber etching.
また、配線材の上部の絶縁膜の堆積状態を改善するには
、配線材全体にテーパーを付けなくても、配線材上部の
角にのみテーパーを付けることで達成できる事実も用い
る。In addition, the fact that improving the deposition state of the insulating film on the upper part of the wiring material can be achieved by tapering only the upper corner of the wiring material without tapering the entire wiring material is also used.
[実施例コ 本発明の実施例を第3図を用いて説明する。[Example code] An embodiment of the present invention will be described with reference to FIG.
基板上に絶縁膜302.配線材303.絶縁膜ろ04を
堆積し、その上に、フォトリソグラフィーにヨリパター
ニングしたレジスト305ののった断面を(α)に示す
。これを異方性ドライエツチングし、断面図(b)を得
る。次に、絶縁膜に対して等方エツチングをし、絶縁膜
306 ニテーパを付ける。この後レジストを除去する
と断面(C)が得られる。ここで304の絶縁膜として
は、酸化S1膜や窒化S1膜が用いられる。また、該絶
縁膜のテーバエツチングが、ドライエツチングで難しい
時には、通常のウェットエッチを用いることができる。An insulating film 302 is formed on the substrate. Wiring material 303. A cross-section of the insulating film 04 deposited thereon with a resist 305 patterned by photolithography is shown in (α). This is subjected to anisotropic dry etching to obtain the cross-sectional view (b). Next, the insulating film is isotropically etched, and the insulating film 306 is tapered. After this, the resist is removed to obtain cross section (C). Here, as the insulating film 304, an oxide S1 film or a nitride S1 film is used. Further, when it is difficult to perform Taber etching of the insulating film by dry etching, ordinary wet etching can be used.
この時には、酸化S1の例では、フッ化アンモン系の溶
液を用いて下の配線材をエツチングすることのないよう
にする。また絶縁膜30乙に等方エツチングでテーパー
を形成した後503の配線材をエツチングする方法も本
発明に含めることができる。At this time, in the case of oxidation S1, an ammonium fluoride solution is used to avoid etching the underlying wiring material. The present invention may also include a method in which the wiring material 503 is etched after forming a taper in the insulating film 30B by isotropic etching.
[発明の効果]
断面(C)の構造の上に絶縁膜を堆積させた断面を第2
図に示す。205の絶縁膜の堆積状態は第1図の従来例
と較べて、特に配線材間に於いて非常に改善されており
、従来生じていた空孔等は全体く生じない。したがって
高信頼性の素子を提供することができる。[Effect of the invention] The cross section where the insulating film is deposited on the structure of cross section (C) is
As shown in the figure. The state of deposition of the insulating film 205 is greatly improved compared to the conventional example shown in FIG. 1, especially between the wiring materials, and the holes etc. that occur conventionally are completely eliminated. Therefore, a highly reliable element can be provided.
第1図は、従来の製造方法による構造を示す断面図。
第2図は、本発明の製造方法による構造を示す断面図。
第5図(α)〜(C)は本発明の製造方法を示す工程断
面図。FIG. 1 is a sectional view showing a structure according to a conventional manufacturing method. FIG. 2 is a sectional view showing a structure according to the manufacturing method of the present invention. FIGS. 5(α) to (C) are process cross-sectional views showing the manufacturing method of the present invention.
Claims (1)
なる金属又は金属化合物を基板上全面に被着する工程、
絶縁膜を全面に被着する工程、フォトレジストを全面被
着しフォトリソグラフィにより該レジストをパターニン
グする工程、該レジストをマスクに、該絶縁膜及び該配
線材をエッチングする工程、該絶縁膜を等方的にエッチ
ンしテーパを付ける工程、を含むことを特徴とする半導
体装置の製造方法。(1) In the process of forming a wiring layer of a semiconductor device, a process of depositing a metal or a metal compound that will become a wiring layer over the entire surface of the substrate;
A step of depositing an insulating film on the entire surface, a step of depositing a photoresist on the entire surface and patterning the resist by photolithography, a step of etching the insulating film and the wiring material using the resist as a mask, a step of etching the insulating film, etc. 1. A method of manufacturing a semiconductor device, comprising the step of directional etching and tapering.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16287688A JPH0212826A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16287688A JPH0212826A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0212826A true JPH0212826A (en) | 1990-01-17 |
Family
ID=15762948
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16287688A Pending JPH0212826A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0212826A (en) |
-
1988
- 1988-06-30 JP JP16287688A patent/JPH0212826A/en active Pending
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