JPH088261A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the coverage of a passivation film by forming an electrode wiring into a forward tapered shape. CONSTITUTION:A metal wiring material (Al-Si-Cu alloy film 13) is formed on a semiconductor substrate 11, and a photoresist film 14 is formed by ordinary photolithography for the formation of a desired wiring pattern. In subsequent etching by an ordinary RIE technique, etching is continuously performed after the exposure of a base silicon oxide film 12. As a result the photoresist film is first tapered, and the wiring material is etched accordingly, which forms tapered electrode wiring 13b. This improves the coverage of a passivation film 15 when it is formed, which enhances the reliability of the resultant semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming electrode wiring.

[0002]

2. Description of the Related Art A conventional method for forming electrode wiring will be described. First, as shown in FIG. 2A, a silicon oxide film 2 (field oxide film, gate oxide film) having a thickness of 0.2 μm is formed on a semiconductor substrate 1. And / or the interlayer insulating film is shown as a representative example), and an Al-Si-Cu film 3 having a thickness of 0.8 μm is deposited on the insulating film.
As shown in (b), a photoresist film 4 is formed, and an etching technique is used to form a wiring 3a whose side surface is vertical or has an inverse tapered shape as shown in FIG. 2 (c). Next, as shown in FIG. 2D, a silicon nitride film 5 (hereinafter referred to as a plasma nitride film) formed by the plasma CVD method is 1.2 μm thick.
m was grown and a passivation film was formed.

In this method, however, the passivation film becomes overhanging in a place where the wiring interval is narrow, the passivation film on the side wall and the bottom of the electrode wiring becomes thin, and water easily enters, so that the wiring material is corroded. There was a problem in reliability.

Further, as described in Japanese Patent Application Laid-Open No. 63-177559, a method of forming a gate electrode in a forward taper shape is as follows: CVD WSi film / sputtering WSi film / polycrystalline Si film. Then, a multilayer film is formed by growing a film having a high etching rate, and a normal dry etching is performed. Then, since the CVD WSi film on the upper portion has a high etching rate, a gate electrode having an obtuse angle between the upper surface and the side surface (hereinafter referred to as side surface forward taper) can be formed. A single layer film of an aluminum-based alloy is usually used as the electrode wiring other than the gate electrode and is not general. Moreover, since a multilayer film is formed, the process becomes complicated.

[0005]

As described above, in the conventional method for forming the electrode wiring, since the side surface of the electrode wiring has an inverse tapered shape or a vertical shape, when the passivation film is formed, the step coverage is poor and the passivation film is formed. Becomes an overhang, and the passivation film on the side wall and bottom of the electrode wiring becomes thin. Therefore, there is a problem in reliability that moisture easily enters and the wiring material is corroded.
Further, the gate electrode is formed so as to have a sideward tapered shape.
The method started in JP-A-3-177559 is not general and cannot be applied to the formation of electrode wiring other than the gate electrode.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a side surface forward tapered electrode wiring.

[0007]

According to the present invention, a conductive film that covers a predetermined insulating film on a semiconductor substrate is deposited, a resist film that selectively covers the conductive film is formed, and the resist film is masked. As a method for manufacturing a semiconductor device, including the step of forming electrode wiring by removing the conductive film by anisotropic reactive ion etching, the reactive ion etching is continued even after the surface of the insulating film is exposed. Then, the electrode wiring having an obtuse angle between the upper surface and the side surface is formed. In this case, the etching conditions are determined so that the side surface is patterned into a trapezoidal cross section when the surface of the insulating film is exposed.

[0008]

With the progress of etching, the resist film becomes a side surface forward taper (the upper surface and the side surface are obtuse angles) and the shape of the resist film is transferred to the shape of the electrode wiring.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. 1A to 1F are process cross-sectional views for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, for example, P
Al-Si-Cu having a thickness of 0.8 μm by covering a silicon oxide film 12 having a thickness of 0.2 μm on the silicon substrate 11 of the mold.
An alloy film 13 (containing 1% of Si and 0.5% of Cu) is formed. Here, it is assumed that an N-type diffusion layer (not shown) or the like is provided on the surface of the silicon substrate 11, and the silicon oxide film 12 is shown as a representative of a gate oxide film, a field oxide film, an interlayer insulating film, or the like (not shown). .

Next, as shown in FIG. 1B, a novolac photoresist film 14 (thickness 1 μm, width 0.8 μm) for forming a desired wiring pattern is formed by using a normal photolithography technique. Form. Next, in a magnetron discharge plasma etching apparatus, BCl ₃ gas and C
Anisotropic reactive ion etching was carried out using a mixed gas (pressure 0.1 Pa) in which an L ₂ gas was mixed at a ratio of 2: 3, and using the photoresist film 14 as a mask.
As shown in (c), Al is formed in a pattern in which the side surfaces are almost vertical.
-Si-Cu film 13a is formed. The etching time at this time is about 90 seconds, and the etching is performed until the surface of the silicon oxide film 12 is exposed. In the conventional formation of electrode wiring, etching is completed at this stage. At this stage, the photoresist film 1
The shape of 4a is slightly tapered toward the side surface as shown in the figure. This is because the upper edge portion of the photoresist film is easily etched. When the etching is further continued under the same conditions, the photoresist film is gradually tapered toward the side surface, and the peripheral surface of the Al-Si-Cu alloy film 13a is exposed, and the etching of the Al-Si-Cu alloy film proceeds from there. Then, as shown in FIG. 1D, the side surface forward taper (trapezoidal cross section) electrode wiring 13b is formed. This over-etching was performed for 60 seconds.

Next, as shown in FIG. 1 (e), after removing the photoresist film, a plasma nitride film 15 having a thickness of 1.2 μm is formed as a passivation film as shown in FIG. 1 (f). Since the electrode wiring 13b is tapered toward the side surface, the step coverage of the plasma nitride film 15 is improved.

As described above, since the side-surface forward tapered electrode wiring is formed by over-etching, the sectional area is smaller and the wiring resistance is higher than that of the rectangular sectional shape, but the width of the photoresist film is set to a large value in advance. By doing so, an increase in wiring resistance can be avoided.

Although the Al-Si-Cu alloy film has been described as an example of the conductive film, the etching rate is substantially higher than that of a single-layer film of a wiring material used for other semiconductor devices or reactive ion etching. From the above description, it is clear that any multi-layer film having no difference may be used.

[0015]

As described above, according to the present invention, when the conductive film of the wiring material is patterned by anisotropic reactive in-on etching, the etching is continued even after the underlying insulating film is exposed. Since the forward tapered electrode wiring can be formed, the coverage of the passivation film can be improved, and the reliability of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1A is a view for explaining an embodiment of the present invention.
It is a process order sectional view divided and shown in (f).

2A to 2D are sectional views in order of the processes, which are divided into (a) to (d) for explaining a conventional example.

[Explanation of symbols]

1,11 Silicon substrate 2,12 Silicon oxide film 3,13,13a Al-Si-Cu alloy film 3a, 13b, 4,14, 14a, 14b Photoresist film 5,15 Plasma nitride film

Claims (2)

[Claims] 1. A conductive film that covers a predetermined insulating film on a semiconductor substrate is deposited, a resist film that selectively covers the conductive film is formed, and the conductive film is anisotropy using the resist film as a mask. In the method for manufacturing a semiconductor device, including the step of forming an electrode wiring by removing by reactive ion etching, the reactive ion etching is continued even after the surface of the insulating film is exposed to form an obtuse angle between the upper surface and the side surface. A method of manufacturing a semiconductor device, which comprises forming electrode wiring. 2. The conductive film is an Al—Si—Cu alloy film, the resist film is a novolac resin film, and the reactive ion etching gas is a mixed gas of BCl ₃ gas and Cl ₂ gas. Manufacturing method of semiconductor device.