JPH09120954A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine contact hole in a small number of processes by forming a hole with a plurality of side walls of different angles in an insulation film by single reactive ion etching. SOLUTION: A BPSG film 2 is formed on a silicon substrate 1 and a photoresist film 4 with a hole 3 having an almost vertical side wall is formed. Then, etching of low selectivity of the photoresist film 4 and the BPSG film 2 is carried out by a reactive ion etching device. Since the angle to ion is large in an upper edge end part of the hole 3 of the photoresist film 4, a facet 8 is formed in an upper end part and a groove 5A is formed in the BPSG film 2. If etching is further continued and a surface of the substrate 1 is exposed, the thickness of a photoresist film reduces, and a facet is enlarged and extends to an upper end part of the groove 6B. A hole 6B formed of an upper part 6B-2 and a lower part 6B-1 with side walls of different angles is formed and an aluminum wiring 7 is formed in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an opening in an insulating film for making contact between an element formed on a substrate and a wiring or between wirings in a multilayer wiring.

[0002]

2. Description of the Related Art At present, in order to make a contact between an element formed on a substrate and a wiring, or a contact between wirings in a multi-layer wiring, a hole is formed in an insulating film by etching after forming an etching mask.

Referring to FIG. 2, a first conventional example combining wet etching and dry etching will be described. In this method, in order to form the upper layer wiring shape with good coverage, isotropic etching is performed once by wet etching, the upper part of the opening is widened, and then the contact of the desired size is opened by dry etching. Is performed. That is, FIG.
As shown in (a), the BPSG film 2 is formed on the silicon substrate 1.
Is formed, and a photoresist film 4 having an opening 3 is formed. Next, as shown in FIG. 2B, a groove 5 larger in size than the opening 3 is formed on the surface of the BPSG film 2 by isotropic etching. Next, as shown in FIG. 2C, an opening 6 is formed by exposing the surface of the silicon substrate 1 by anisotropic dry etching. Next, the photoresist film 4 is removed. Thus, as shown in FIG. 2D, an opening 6 in which the size of the upper portion 6-1 is larger than the size of the lower portion 6-2 is formed. Next, as shown in FIG. 2E, an aluminum-based wiring 7 is formed.

Further, there is a method (second conventional example) of forming a wiring with good coverage by using a taper contact etch which is inclined from the upper part to the lower part by a resist receding method or the like. That is, as shown in FIG.
A BPSG film is deposited on the silicon substrate 1 to form a photoresist film 4A having an opening 3A. 3 in FIG.
By forming an opening similar to that described above and performing reflow by an appropriate heat treatment, a forward tapered opening 3A can be formed. Next, when the BPSG film 2 is etched under the condition that the selectivity with respect to the photoresist film 4A is about 1, as shown in FIG. 3B, the opening end of the photoresist film is etched while being receded to form a forward tapered shape. Groove 5A is formed. By continuing this etching until the bottom of the groove reaches the silicon substrate 1, a forward tapered opening 6A can be formed in the BPSG film 2 as shown in FIG. Next, the photoresist film is removed as shown in FIG. 3D, and an aluminum-based wiring 7 is formed as shown in FIG.

[0005]

In the above-mentioned first conventional example, two stages of etching, that is, wet etching and dry etching must be combined, and there is a problem that the number of steps is increased.

In the second conventional method using the resist receding method, there is a problem that the contact opening is too large in the upper part, which is not suitable for fine processing.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a fine contact opening can be formed with a small number of steps.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming an insulating film covering a predetermined conductive region on a semiconductor substrate, and applying a resist film having a predetermined thickness to the insulating film. Selectively etching and developing to form an etching mask having substantially vertical side walls and a first opening corresponding to the conductive region; and a low selectivity of the insulating film to the etching mask. While forming a facet at the upper end of the first opening by reactive ion etching, a groove on a side wall closer to the vertical than the facet is formed in the insulating film of the first opening, and the reactive ion etching is continued. Reducing the thickness of the etching mask and enlarging the facet to at least partially extend to the upper end of the groove, whereby the upper portion is lower than the lower portion. A second hole having a different sidewall of and angle spread of the is that a step of forming the insulating film.

Here, the reactive ion etching may be continued until the etching mask is exhausted.

[0010] Also, the resist film and the insulating film are positive photoresist film and the silicon oxide film, respectively, CF ₄
By using a mixed gas of gas and SF ₆ gas, the selectivity can be set to about 1.

Using a single reactive ion etching, a second opening having a plurality of side walls having different angles can be formed as a contact opening.

[0012]

1 (a) to 1 (f) are cross-sectional views in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a silicon substrate 1 (elements not shown, such as MOS transistors, are formed. Therefore, it is assumed that a gate oxide film, a field oxide film, etc., not shown, are formed). An insulating film, for example, a BPSG film 2 having a thickness of 800 nm;
First opening 3 (silicon substrate 1 having substantially vertical side walls)
(Corresponding to a diffusion layer (not shown) formed on the surface of the substrate).
The resist film 4 has a thickness of 800 to 900 nm when a novolak resin is used as the resist material, for example. Next, for example, using a cathode-coupled reactive ion etching apparatus, the frequency is 13.56 MHz, the RF power is 500 W, the pressure is 20 Pa, and the CF ₄ gas flow rate is 10 scc.
Etching is performed under the conditions of m and SF ₆ gas flow rate of 20 sccm. Under this condition, the etching selectivity between the photoresist film 4 and the BPSG film 2 becomes 1. As shown in FIG. 2B, the upper edge of the opening 3 of the photoresist film 4 is formed with a facet 8 at the upper end and a groove is formed in the BPSG film 2 due to a large prospect angle for ions. 5
A (having side walls at about 80 degrees with respect to the substrate plane) is formed. If the etching is continued, the thickness of the photoresist film is reduced and the facets are enlarged. FIG.
(B) shows a state in which the facet 8A has spread in the entire thickness direction of the remaining photoresist film. The difference from the state shown in FIG.
That is, the groove 5B is formed in the SG film. Further, the etching is continued to expose the surface of the silicon substrate 1.
As shown in FIG. 1D, the thickness of the photoresist film is further reduced, and the facet is enlarged so that a part thereof reaches the upper end of the groove 6B. As shown in FIG. 1D, some photoresist film may remain when the surface of the silicon substrate 1 is exposed (etching time is 4 minutes). In that case, the residual resist film is removed by ashing. Or,
When the initial thickness of the photoresist film is appropriately set and the surface of the silicon substrate is exposed, there is no or little residual resist, and if necessary, etching is further continued to perform over-etching (etching time: Ashing is unnecessary if the total time is 4 minutes and 30 seconds). In this manner, as shown in FIG.
A second opening 6B consisting of an upper part 6B-2 having a side wall of 5 ° and a lower part 6B-1 having a side wall of about 80 ° could be formed. Next, as shown in FIG. 1F, an aluminum-based wiring is formed. The step coverage was as good as the first and second conventional examples.

Unlike the first conventional example, the number of steps is small because only a single etching step is required. Unlike the second conventional example, a contact opening having two side walls having different angles can be formed. It can be said that it is suitable for processing.

The case where contact between the element and the wiring is made (the conductive region is a diffusion layer) has been described above, but the present invention is also applied to the case where the contact between the wirings of the multilayer wiring is made (the conductive region is the lower layer wiring). This will be apparent without further elaboration.

[0016]

As described above, according to the present invention, an opening having a plurality of side walls having different angles can be formed in the insulating film by a single reactive ion etching, so that the step coverage of the wiring filling the opening is impaired. Without using a plurality of etchings, the number of steps can be reduced as compared with the first conventional example, and an opening having a smaller size than the second conventional example by the resist receding method can be formed, which is suitable for fine processing. That is, a semiconductor device having good step coverage can be manufactured at a high yield and in a short work period.

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views in the order of steps for explaining an embodiment of the present invention.

FIGS. 2A to 2C are views for explaining a first conventional example.
FIG. 6E is a sectional view in a process order, which is separately illustrated in FIG.

FIGS. 3A to 3C are views for explaining a second conventional example.
FIG. 6E is a sectional view in a process order, which is separately illustrated in FIG.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 BPSG film 3 opening 4 photoresist film 5, 5A, 5B groove 6, 6A, 6B opening 6-1 upper part of opening 6 6-2 lower part of opening 6 6B-1 upper part of opening 6B 6B-2 Lower part of opening 6B 7 Aluminum wiring 8,8A Facet

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/90 CA

Claims (3)

[Claims] 1. A step of forming an insulating film covering a predetermined conductive region on a semiconductor substrate, and a substantially vertical sidewall by applying a resist film of a predetermined thickness to the insulating film, selectively exposing and developing the resist film. Forming an etching mask having a first opening corresponding to the conductive region, and reactive ion etching having a low selection ratio of the insulating film with respect to the etching mask. Forming a facet, forming a groove on a sidewall closer to vertical than the facet in the insulating film of the first opening, and continuing the reactive ion etching to reduce the thickness of the etching mask. And at least a part thereof is applied to the upper end of the groove, whereby a plurality of side walls that are wider at the upper portion than at the lower portion and have different angles are formed. Forming a second opening in the insulating film. 2. The method according to claim 1, wherein the reactive ion etching is continued until the etching mask disappears. 3. The resist film and the insulating film are a positive photoresist film and a silicon oxide film, respectively, and a mixed gas of CF ₄ gas and SF ₆ gas is used, and a selectivity is set to about 1. Or the method of manufacturing a semiconductor device according to 2.