JPH1117108A - Mim capacitor, manufacture thereof, and high-frequency integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reduction in a time period during which a lower wiring of a first insulating film is exposed to RIE(reactive ion etching) in forming a via-hole, prevent intrusion into a dielectric film due to generation of a hole in a lower electrode, and restrain deterioration in insulation property between the lower electrode and an upper electrode. SOLUTION: A first insulating film 2 and a second insulating film 3 are stacked directly below a capacitor. The second insulating film 3 is worked into a recessed shape, and a lower electrode 6 is formed in the recessed portion. At this point, the thickness of the second insulating film 3 and the thickness of the lower electrode 6 are made equal to eliminate any surface step. In addition, etching of a semi-insulating substrate 1 at a step of forming a via-hole 9 is carried out under such conditions that the first insulating film 2 is less likely be etched. When the first insulating film 2 is exposed, etching is interrupted and the etching conditions are changed to etch the first insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIM (Meta
More particularly, the present invention relates to a MIM capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 shows a structure of a conventional capacitor and a manufacturing process thereof. As shown in JP-A-3-102865, first, a photoresist pattern 4 is formed on a semi-insulating substrate 1, and the semi-insulating substrate 1 is etched using the photoresist pattern as a mask to form a groove 5. . Next, the lower electrode 6 is embedded in the semi-insulating substrate 1 so as to be flush with the height of the groove 5. A dielectric film 7 is laminated, an upper electrode 8 is formed, and M
Fabricate an IM capacitor. Next, after thinning the semi-insulating substrate 1 to a thickness of 100 μm from the back surface by lapping and chemical polishing, the substrate is etched from the back surface of the semi-insulating substrate 1 to form via holes 9 to the back surface of the lower electrode 6. Then, the back electrode 10 is laminated thereon.

[0003]

In the case of the prior art, when the back surface of the semi-insulating substrate 1 is thinned by lapping and chemical polishing, the thickness of the semi-insulating substrate 1 may increase or decrease depending on the location. It has a distribution in the substrate plane. For this reason, when forming the via hole 9 from the back surface of the semi-insulating substrate 1, it is necessary to perform over-etching in consideration of the thickness variation. As a result, the lower wiring 6 is exposed to RIE for a long time in the portion where the substrate thickness is reduced. Therefore, in the prior art, the lower electrode 6 is formed thick to prevent a hole from being formed in the lower electrode 6 and further prevent the dielectric film 7 from being attacked. However, etching of the lower electrode 6 is unavoidable. For example, when process variations such as a process of thinning the semi-insulating substrate 1 and etching for forming a via hole increase, the wiring thickness of the lower electrode 6 is increased. However, a hole is formed in the wiring, and the dielectric film 7
, The insulation between the lower electrode 6 and the upper electrode 8 of the MIM capacitor cannot be maintained, and the yield of the high-frequency integrated circuit decreases. Further, in the prior art, the thickness of the lower wiring 6 is required to be 5 μm or more. Substrate 1
When the lower electrode 6 is formed by embedding the lower electrode 6, there is a problem that a step is generated, which leads to dielectric breakdown of the capacitor.

[0004]

In the MIM capacitor structure according to the present invention, a first insulating film is formed on a semi-insulating substrate.
Then, the second insulating film 3 is laminated, and a groove 5 is formed in the second insulating film 3. Here, the lower electrode 6 is buried, and the first insulating film 2 is used as an etching stopper layer when forming the via hole 9 from the back surface of the semi-insulating substrate 1 when the via hole 9 is formed.

According to a first aspect of the present invention, there is provided an MIM capacitor comprising: a semi-insulating substrate; a lower electrode on the semi-insulating substrate; a dielectric film formed on the lower electrode; A first insulating film is formed on a semi-insulating substrate in an MIM capacitor including an upper-layer electrode, and a lower-layer electrode is wired by a via hole reaching a back surface of the semi-insulating substrate formed immediately below the MIM capacitor. A second insulating film and a lower electrode are formed on the first insulating film, and the upper surfaces of the second insulating film and the lower electrode are substantially coplanar.

According to a second aspect of the present invention, there is provided a method of manufacturing an MIM capacitor, comprising the steps of: providing a semi-insulating substrate; a lower electrode on the semi-insulating substrate; a dielectric film formed on the lower electrode; A method of manufacturing an MIM capacitor comprising an upper electrode on a film and a lower electrode wired by a via hole reaching a back surface of the semi-insulating substrate formed immediately below the first electrode. Laminating an insulating film and a second insulating film, forming a concave portion in the second insulating film, and embedding a lower electrode in the concave portion so as to be substantially flush with the surface thereof. It is characterized by the following.

According to a third aspect of the present invention, there is provided a method of manufacturing an MIM capacitor according to the second aspect, wherein the concave portion formed in the second insulating film extends up to near the surface of the first insulating film. It is characterized by the following.

According to a fourth aspect of the present invention, in the method of manufacturing a MIM capacitor according to the second aspect, the first insulating film is selected from one of a Si ₃ N ₄ film and a SiO ₂ film. The second insulating film is different from the first insulating film, and
It is characterized in that it is selected from any one of resins such as a Si ₃ N ₄ film, a SiO ₂ film and a polyimide film.

According to a fifth aspect of the present invention, there is provided the MIM capacitor according to any one of the second to fifth aspects, wherein a via hole is formed from a back surface of the semi-insulating substrate by RIE (Reactive Ion Etching).
In the case of forming by a method, the etching is performed under an etching condition in which the etching rate of the first insulating film is lower than the etching rate of the semi-insulating substrate.

According to a sixth aspect of the present invention, there is provided a high frequency integrated circuit using the MIM capacitor of the first aspect.

The operation of the MIM capacitor of the present invention is as follows. In the MIM capacitor of the present invention, when the via hole 9 is formed, the time that the lower wiring 6 is exposed to the RIE by the first insulating film 2 can be shortened. As a result, the dielectric film 7 is not damaged and the insulation between the lower electrode 6 and the upper electrode 8 of the MIM capacitor is not deteriorated.
Furthermore, the thickness of the lower wiring 6 can be reduced,
Since the variation in the formation of the groove 5 for embedding the lower electrode 6 and the variation in the film formation of the lower electrode 6 can be reduced, a step does not occur when the lower electrode 6 is embedded and formed, and a decrease in the breakdown voltage of the capacitor is suppressed. You can do it. Therefore, a high-frequency integrated circuit can be realized with high yield and high reproducibility, and high reliability can be achieved.

[0012]

Next, the present invention will be described in detail with reference to examples, but the present invention is not limited by these examples.

Referring to FIG. 1, M according to a first embodiment of the present invention will be described.
A method for manufacturing an IM capacitor will be described. Semi-insulating substrate 1
(For example, a GaAs semi-insulating substrate) on a first insulating film S
i3N4 film is laminated at a thickness of 2000 ° and a second insulating film S
An iO ₂ film is laminated at 1 μm (FIG. 1A). At this time, it is desirable to select an etching condition and a film that can obtain an etching rate at which the etching rate of the second insulating film is 10 times or more higher than that of the first insulating film.

Next, a photoresist pattern 4 is formed by a usual photolithography technique, and the second insulating film SiO ₂ film is etched using this as a mask material (for example, RIE using CHF ₃ gas) to form a groove 5. Form. At this time, the emission spectrum is observed with a spectroscope or the like, and the etching is terminated when the surface of the first insulating film Si ₃ N ₄ is exposed (FIG. 1B).

Next, while the photoresist pattern 4 is left, a metal film (for example, Al) serving as the lower electrode 6 of the MIM capacitor is formed to a thickness of 1 μm by vapor deposition or the like (FIG. 1).
(C)). Next, the photoresist pattern 4 is removed together with the metal film deposited thereon to form the lower electrode 6 (FIG. 1D). Here, the lower electrode 6 is made of a second insulating film S
It is not embedded in the iO ₂ film and causes no step. Next, the dielectric film 7 (for example, SiO ₂ , Si ₃ N ₄ , SiON, PZT,
STO, TaO, etc.) are formed by a plasma CVD method or the like (FIG. 1E).

Next, a metal wiring (for example, Ti / Au) of the upper electrode 7 of the capacitor is formed by a normal vapor deposition method or a sputtering method, and is subjected to resist patterning by a normal photolithography technique and etching by RIE or the like. It is formed (FIG. 1F).

Next, in order to reduce the thermal resistance of the GaAs semi-insulating substrate 1, the back surface is ground by polishing or the like to reduce the substrate thickness to 100 μm.
m, and a photoresist pattern of an opening is formed on the back surface of the GaAs semi-insulating substrate 1 opposed to the lower electrode 6 of the capacitor by a photolithography technique using an exposure device or the like capable of overlapping both surfaces using infrared rays. Then, the GaAs semi-insulating substrate 1 is etched by RIE, and the etching is terminated when the GaAs semi-insulating substrate 1 reaches the first insulating film Si ₃ N ₄ (FIG. 1 (g)). Here, for the etching of the GaAs semi-insulating substrate 1, for example, a chlorine-based gas such as SiCl ₄ is used, and conditions are selected under which the first insulating film Si ₃ N ₄ film is hardly etched.

Next, the first insulating film Si ₃ N ₄ film is etched (for example, RIE using CHF ₃ + SF ₆ gas),
The etching is terminated when the lower electrode 6 is exposed. Finally, a back electrode 10 (for example, Au) is formed (FIG. 1).
(H)).

FIG. 2 shows a structural diagram of the second embodiment. Here, the first insulating film is formed of a SiO ₂ film 2000 °, and the etching conditions thereof are, for example, a RIF using a CHF ₃ gas.
Using an E method or the like, a 1 μm-thick Si ₃ N ₄ film is used as the second insulating film, and the etching condition thereof is, for example, an RIE method using a CHF ₃ + SF ₆ gas. Other conditional structures are first
This is the same as the embodiment. FIG. 3 shows a structural diagram of the third embodiment. Here, the first insulating film is made of a SiO ₂ film 2000Å.
RIE method using, for example, CHF ₃ gas as an etching condition, a polyimide film of 1 μm as a second insulating film, and an etching condition of, for example, CHF 3.
An RIE method using ₃ + SF ₆ gas is used. Other conditions are the same as in the first embodiment.

FIG. 4 shows a structural diagram of the fourth embodiment. Here, a Si ₃ N ₄ film 2000 # is used as the first insulating film, an RIE method using, for example, CHF ₃ + SF ₆ gas is used as an etching condition thereof, and a polyimide film 1 μm is used as the second insulating film.
m, and for example, CHF ₃ +
An RIE method using SF ₆ gas or the like is used. Other conditions are the same as in the first embodiment.

FIG. 5 shows an example of a high-frequency integrated circuit to which the above structure is applied.

[0022]

By using the present invention as described above,
When the via hole 9 is formed, the time that the lower wiring 6 is exposed to the RIE by the first insulating film 2 can be shortened, so that a hole is formed in the lower electrode 6 and the dielectric film 7 is further formed.
Of the lower electrode 6 and the upper electrode 8 can be suppressed from deteriorating. Further, the thickness of the lower layer wiring 6 can be reduced, so that a step does not occur when the lower layer electrode 6 is buried and formed, and a decrease in the dielectric breakdown voltage of the capacitor can be suppressed. Therefore, a high-frequency integrated circuit can be realized with a high yield and good reproducibility, and element characteristics can be stabilized, and high reliability can be achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure and a method of manufacturing an MIM capacitor according to a first embodiment of the present invention.

FIG. 2 is a structural diagram showing a second embodiment of the present invention.

FIG. 3 is a structural view showing a third embodiment of the present invention.

FIG. 4 is a structural diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram illustrating a high-frequency integrated circuit using an MIM capacitor according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a structure and a manufacturing method of a conventional MIM capacitor.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating substrate 2 first insulating film Si3N4 film 21 first insulating film SiO2 film 3 second insulating film SiO2 film 31 second insulating film Si3N4 film 32 second insulating film polyimide film 4 photoresist pattern 5 Groove of second insulating film 6 lower electrode of MIM capacitor 7 dielectric film 8 upper electrode of MIM capacitor 9 via hole 10 back electrode 11 channel layer 12 impurity diffusion region (source) 13 impurity diffusion region (drain) 101 MIM capacitor 102 MESFET

Claims (6)

[Claims] 1. A semiconductor device comprising: a semi-insulating substrate; a lower electrode on the semi-insulating substrate; a dielectric film formed on the lower electrode; and an upper electrode on the dielectric film. An MIM capacitor (Metal) wired by a via hole reaching the back surface of the semi-insulating substrate formed immediately below
Insulator Metal), a first insulating film is formed on a semi-insulating substrate, a second insulating film and a lower electrode are formed on the first insulating film, and the second insulating film and the lower electrode are formed. Wherein the upper surface of the MIM capacitor is substantially coplanar. 2. A semiconductor device comprising: a semi-insulating substrate; a lower electrode on the semi-insulating substrate; a dielectric film formed on the lower electrode; and an upper electrode on the dielectric film. In a method of manufacturing an MIM capacitor wired by a via hole reaching a back surface of the semi-insulating substrate formed immediately below, a first insulating film and a second insulating film are stacked on the semi-insulating substrate. A step of forming a recess in the second insulating film, and embedding a lower electrode in the recess so as to be substantially flush with the surface thereof.
A method for manufacturing an IM capacitor. 3. The method of manufacturing an MIM capacitor according to claim 2, wherein the recess formed in the second insulating film is formed up to near the surface of the first insulating film. 4. The first insulating film is a Si ₃ N ₄ film, SiO 2
_{The second} insulating film is different from the first insulating film and is selected from any one of resins such as a Si ₃ N ₄ film, a SiO ₂ film, and a polyimide film. 3. The method for manufacturing a MIM capacitor according to claim 2, wherein: 5. A via hole is formed from the back surface of the semi-insulating substrate by RIE (Reactive Ion Etching).
6. The MIM capacitor according to claim 2, wherein, when formed by the g) method, the etching is performed under etching conditions in which the etching rate of the first insulating film is lower than the etching rate of the semi-insulating substrate. Production method. 6. A high-frequency integrated circuit using the MIM capacitor according to claim 1.