JPH02122688A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPH02122688A
JPH02122688A JP27783588A JP27783588A JPH02122688A JP H02122688 A JPH02122688 A JP H02122688A JP 27783588 A JP27783588 A JP 27783588A JP 27783588 A JP27783588 A JP 27783588A JP H02122688 A JPH02122688 A JP H02122688A
Authority
JP
Japan
Prior art keywords
substrate
resist
hole
copper foil
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27783588A
Other languages
Japanese (ja)
Inventor
Osamu Hirai
修 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27783588A priority Critical patent/JPH02122688A/en
Publication of JPH02122688A publication Critical patent/JPH02122688A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To enable formation of fine circuit pattern by forming a copper foil circuit patterned with etching resist on a copper-clad board, applying electroplating resist to it, and electroplating holes and the copper foil. CONSTITUTION:A hole 4 is made through a substrate 1 sandwiched by copper foils 2, then catalyst 3 is applied on the inner wall of the hole 4 and the opposite faces of the substrate 1. Then the opposite faces of the substrate 1 are coated with etching resist 5 and subjected to exposure, development and etching. Thereafter, liquid photoresist is applied entirely on the opposite faces of the substrate, then it is dried, exposed, developed and hardened thus forming a plating resist 6. Then the etching resist 5 is removed. Thereafter, electroless copper plating is carried out on the inner wall of the hole 4 and the copper foil 2 thus forming a through-hole and a circuit pattern. Then solder mask 8 is printed on parts except a mounting pad, lands and through-holes thus producing a predetermined printed circuit board.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は印刷配線板の製造方法に関し、特にスルーホー
ル°を有する印刷配線板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a printed wiring board, and particularly to a method for manufacturing a printed wiring board having through holes.

〔従来の技術〕[Conventional technology]

従来、印刷配線板の製造方法としては、サブトラクティ
ブ法とアディティブ法とが用いられてきたが、特に、ア
ディティブ法は、印刷配線板の高密度化が進展して行く
なかで、ファインラインの形成が容易なことから近年注
目を集めている。
Conventionally, the subtractive method and additive method have been used as methods for manufacturing printed wiring boards, but in particular, the additive method has been used to form fine lines as the density of printed wiring boards continues to increase. It has attracted attention in recent years because it is easy to use.

アディティブ法には、スルーホールだけを無電解めっき
により形成するパートリ−アディティブ法とスルーホー
ルと回路パターンを共に無電解めっきにより形成するフ
ルアデイティブ法とがある。
Additive methods include a part-additive method in which only through-holes are formed by electroless plating, and a full-additive method in which both through-holes and circuit patterns are formed by electroless plating.

パートリ−アディティブ法は、第2図に示す如く、孔4
を穿設した銅張の基板1に触媒処理を施こした後、感光
性ドライフィルムを用いて銅箔2をエツチングして回路
パターンを形成し、次いで、孔4およびランドとパッド
を除く部分へめっきマスク6の形成、孔4およびランド
とパッドヘの銅めっき7を無電解めっきでの形成を行な
って、印刷配線板を形成する。
In the part-additive method, as shown in Figure 2, the hole 4
After performing catalytic treatment on the copper-clad substrate 1 with the holes drilled therein, the copper foil 2 is etched using a photosensitive dry film to form a circuit pattern. A printed wiring board is formed by forming a plating mask 6 and forming copper plating 7 on holes 4 and lands and pads by electroless plating.

また、フルアデイティブ法では、一般に、第3図に示す
如く、接着剤付触媒入りの基板1に孔4を穿設、めっき
レジスト6の形成を行なった後、無電解めっきにより孔
4および基板1上のめつきレジスト6で覆われていない
部分に銅めつき7を被着して、スルーホールおよび回路
パターンを形成する。さらに、ソルダーマスク8を印刷
して、所定の印刷配線板を形成していた。
In addition, in the full additive method, generally, as shown in FIG. 3, holes 4 are formed in a substrate 1 containing an adhesive and a catalyst, and after a plating resist 6 is formed, the holes 4 and the substrate are formed by electroless plating. Copper plating 7 is applied to portions of 1 that are not covered with plating resist 6 to form through holes and circuit patterns. Furthermore, a solder mask 8 was printed to form a predetermined printed wiring board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のアディティブ法による印刷配線板の製造
方法には、次に列挙する欠点があった。
The above-described conventional method for manufacturing a printed wiring board using the additive method has the following drawbacks.

(1)近年、印刷配線板の高密度化の進展はめざましく
、従来、0.1インチ格子間に1〜2本配線であったも
のが、現在では、3本配線が主流になりつつある。これ
に伴なって、回路パターンの幅も0,1インチ格子間2
本配線での200μm程度から、3本配線では、100
〜150μmと微細化してきており、今後、4〜6本配
線へと進展して行くにつれ、100μm以下の超微細パ
ターンへ進んで行くものと思われる。しかしながら、回
路パターンの幅の微細化は、一方では、導体であるべき
回路パターンの電気抵抗増大を招き、電子機器の安定動
作に対する電気的マージンが減少し、回路設計も複雑か
つ困難なものとなってしまう。
(1) In recent years, there has been remarkable progress in increasing the density of printed wiring boards, and what used to be one or two wires between 0.1-inch grids is now becoming mainstream with three wires. Along with this, the width of the circuit pattern is also 0.1 inch with a lattice spacing of 2
From about 200μm for main wiring to 100μm for three wirings
The pattern has been miniaturized to ~150 .mu.m, and it is thought that in the future, as the number of interconnects increases to 4 to 6, ultra-fine patterns of 100 .mu.m or less will become available. However, the miniaturization of circuit pattern widths, on the other hand, increases the electrical resistance of circuit patterns that should be conductors, reduces the electrical margin for stable operation of electronic devices, and makes circuit design more complex and difficult. It ends up.

前述したパートリ−アディティブ法では、銅箔のみで回
路パターンを形成し、通常、厚さ35μmの銀箔を使用
する。しかしながら、回路パターンがこのように微細化
してくると、35μm厚の銅箔では電気抵抗が高いとい
う問題がある。この問題を改善するため、銅箔厚を50
μmあるいは70μmと厚くする方法も用いられている
が、この場合、エツチング量が大きくなり、微細パター
ンの形成が困難になる。
In the above-mentioned part-additive method, a circuit pattern is formed only with copper foil, and usually silver foil with a thickness of 35 μm is used. However, as circuit patterns become finer in this way, there is a problem in that a 35 μm thick copper foil has high electrical resistance. To improve this problem, the copper foil thickness was increased by 50 mm.
A method of increasing the thickness to .mu.m or 70 .mu.m has also been used, but in this case, the amount of etching becomes large, making it difficult to form fine patterns.

(2)実装技術の表面実装化は、今や一般に普及してい
る技術である。表面実装部品の代表的なものとしてQu
ad Flat I’ackage  (Q F Pと
記す)があるが、QFPのパッド間ピッチは年々縮小化
し、現在では、0.5龍ピツチのものまで使用されてい
る。この場合、印刷配線板のパッド間隔は、0.2〜0
.25Iomと狭くなる。さらに、今f&0.4Il1
m程度へとQFPのパッド間ピッチは増々狭くなって行
き、印刷配線板のパッド間隔も0.15〜0.20mm
程度へと狭くなって行くものと思われる。
(2) Surface mounting of mounting technology is now a commonly used technology. Qu is a typical surface mount component.
There is an ad Flat I'ackage (abbreviated as QFP), but the pitch between QFP pads has been reduced year by year, and now even 0.5 dragon pitch is used. In this case, the pad spacing of the printed wiring board is 0.2 to 0.
.. It becomes narrower at 25 Iom. Furthermore, now f&0.4Il1
The pitch between QFP pads is becoming narrower and narrower, and the pad spacing on printed wiring boards is also 0.15 to 0.20 mm.
It seems that it will gradually become narrower.

このように、パッド間ピッチが狭くなると、上述したパ
ートリ−アディティブ法では、パッド間に析出しためっ
きによりブリッジ等が発生しやすく、このため修理工数
がかなりかかったり、歩留が著しく悪化する。
As described above, when the pitch between pads becomes narrow, in the above-mentioned part-additive method, bridging and the like are likely to occur due to plating deposited between the pads, which requires a considerable number of repair man-hours and significantly reduces yield.

(3)フルアデイティブ法は、接着割付でかつ触媒入り
の特殊基材を使用するため、材料コスト面でも、また、
材料の供給先が限定される。
(3) Since the fully additive method uses a special base material with adhesive layout and catalyst, it is also effective in terms of material cost.
Material supply destinations are limited.

(4)また、材料コストを下げる目的で触媒の入ってい
ない基材を使用し、孔あけ後、触媒処理をする方法も行
なわれているが、この場合、触媒が回路間に残り、絶縁
抵抗が著しく低下する。
(4) In addition, in order to reduce material costs, a method is used in which a base material without catalyst is used and treated with catalyst after drilling, but in this case, the catalyst remains between the circuits and the insulation resistance decreases significantly.

本発明の目的は、微細な回路パターンの形成が可能で表
面実装に対応出来、絶縁抵抗が高く、安価で安定して供
給出来る印刷配線板の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a printed wiring board that allows the formation of fine circuit patterns, is compatible with surface mounting, has high insulation resistance, and can be supplied stably at low cost.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の印刷配線板の製造方法は、表裏両面に銅箔が張
り合わされた基板に孔を穿設し触媒処理を施す工程と、
前記基板表裏両面にエツチングレジストを被着形成し前
記銅箔の露出部分をエツチング除去する工程と、前記銅
箔の除去された部分にめっきレジストを形成する工程と
、前記エツチングレジストを除去した後前記孔および銅
箔上にめっきを被着してスルーホールおよび回路パター
ンを形成する工程と、所定部分の前記回路パターンをソ
ルダーレジストで被覆する工程とを含んで構成されてい
る。
The method for manufacturing a printed wiring board of the present invention includes the steps of drilling holes in a substrate having copper foil laminated on both the front and back surfaces and subjecting it to catalyst treatment;
A step of depositing etching resist on both the front and back surfaces of the substrate and etching away the exposed portion of the copper foil, forming a plating resist on the removed portion of the copper foil, and after removing the etching resist, The method includes a step of depositing plating on the hole and copper foil to form a through hole and a circuit pattern, and a step of covering a predetermined portion of the circuit pattern with a solder resist.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(f)は本発明の第1の実施例の製造方
法を説明する工程順に示した断面図である。
FIGS. 1(a) to 1(f) are sectional views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

第1の実施例は、まず、第1図(a)に示す如く、表裏
両面に銅箔2が張り合わされた基板1に孔4を穿設した
後、触媒3を孔4内壁および基板1表裏両面に被着形成
する。
In the first embodiment, as shown in FIG. 1(a), a hole 4 is first formed in a substrate 1 on which copper foil 2 is laminated on both the front and back sides, and then a catalyst 3 is placed on the inner wall of the hole 4 and on the front and back sides of the substrate 1. Adhesion is formed on both sides.

次に、第1図(b)に示す如く、基板1の表裏両面に、
エツチングレジスト5として、例えば、ドライフィルム
レジストをラミネートし、露光・現像・エツチングを行
なう。
Next, as shown in FIG. 1(b), on both the front and back surfaces of the substrate 1,
As the etching resist 5, for example, a dry film resist is laminated and exposed, developed, and etched.

次に、第1図(c)に示す如く、写真現像型液状レジス
トを基板表裏両面全面に塗布・乾燥し、露光・現像・硬
化してめっきレジスト6を形成する。
Next, as shown in FIG. 1(c), a photo-developable liquid resist is applied to the entire surface of both the front and back surfaces of the substrate, dried, exposed, developed, and hardened to form a plating resist 6.

次に、第1図(d)に示す如く、エツチングレジスト5
を剥離除去する。
Next, as shown in FIG. 1(d), the etching resist 5
Peel and remove.

次に、第1図(e)に示す如く、無電解銅めっきを行な
い孔4の内壁および銅箔2上に銅めっき7を被着し、ス
ルーホールおよび回路パターンを形成する。
Next, as shown in FIG. 1(e), electroless copper plating is performed to deposit copper plating 7 on the inner wall of the hole 4 and the copper foil 2, thereby forming a through hole and a circuit pattern.

次に、第1図(f)に示す如く、部品実装用パッド、ラ
ンド、スルーホールを除く部分にソルダーマスク8を印
刷し、所定の印刷配線板を得た。
Next, as shown in FIG. 1(f), a solder mask 8 was printed on the parts excluding the component mounting pads, lands, and through holes to obtain a predetermined printed wiring board.

第2の実施例は、第1の実施例と同様第1図(a)に示
す如く、孔4を穿設し、触媒3を被着形成した基板1に
、第1図(b)に示す如く、エツチングレジスト5とし
て、例えば、ドライフィルムレジストをラミネートし、
露光・現像・エツチングする。
In the second embodiment, as shown in FIG. 1(a), holes 4 are formed and a catalyst 3 is deposited on a substrate 1, as shown in FIG. 1(b), similar to the first embodiment. As the etching resist 5, for example, a dry film resist is laminated,
Expose, develop, and etch.

次に、第1図(C)に示す如く、基板1表裏両面全面に
、めっきレジスト6を塗布し、硬化させた後、基板1表
裏両面を研磨して、エツチングレジスト5上に塗布され
ためっきレジスト6を除去する。
Next, as shown in FIG. 1(C), a plating resist 6 is applied to the entire surface of both the front and back surfaces of the substrate 1, and after curing, both the front and back surfaces of the substrate 1 are polished to remove the plating applied on the etching resist 5. Remove resist 6.

以後、第1の実施例と同様にエツチングレジスト5の剥
離、無電解銅めっき2ソルダーマスク8の印刷を行なっ
て、所定の印刷配線板を得た。
Thereafter, the etching resist 5 was peeled off and the electroless copper plating 2 solder mask 8 was printed in the same manner as in the first embodiment to obtain a predetermined printed wiring board.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、銅箔が張り合わされた基
板の銅箔をエツチングレジストを用いて銅箔回路パター
ンを形成した後、めっきレジストを形成し、孔および銅
箔上にめっきを被着することにより次に列挙する効果が
ある。
As explained above, the present invention involves forming a copper foil circuit pattern using an etching resist on the copper foil of a board on which the copper foils are laminated together, then forming a plating resist, and depositing plating on the hole and the copper foil. By doing so, the following effects can be achieved.

(1)一般の銅張積層基板を使用出来るため安価な印刷
配線板を安定して供給出来る。
(1) Since general copper-clad laminate boards can be used, inexpensive printed wiring boards can be stably supplied.

(2)表面実装に対応した印刷配線板が供給出来る。(2) Printed wiring boards compatible with surface mounting can be supplied.

(3)回路パターン幅の微細化に対応した印刷配線板が
製造出来る。
(3) Printed wiring boards compatible with miniaturization of circuit pattern width can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は本発明の第1の実施例の製造方
法を説明する工程順に示した断面図、第2図は従来の印
刷配線板の製造方法の一例を説明する断面図、第3図は
従来の印刷配線板の製造方法の他の例を説明する断面図
である。 1・・・基板、2・・・銅箔、3・・・触媒、4・・・
孔、5・・・エツチングレジスト、6・・・めっきレジ
スト、7・・・銅めっき、8・・・ソルダーマスク。
FIGS. 1(a) to (f) are cross-sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing an example of the conventional method for manufacturing a printed wiring board. 3 are cross-sectional views illustrating another example of the conventional method for manufacturing a printed wiring board. 1...Substrate, 2...Copper foil, 3...Catalyst, 4...
Hole, 5... Etching resist, 6... Plating resist, 7... Copper plating, 8... Solder mask.

Claims (1)

【特許請求の範囲】[Claims] 表裏両面に銅箔が張り合わされた基板に孔を穿設し触媒
処理を施す工程と、前記基板表裏両面にエッチングレジ
ストを被着形成し前記銅箔の露出部分をエッチング除去
する工程と、前記銅箔の除去された部分にめっきレジス
トを形成する工程と、前記エッチングレジストを除去し
た後前記孔および銅箔上にめっきを被着してスルーホー
ルおよび回路パターンを形成する工程と、所定部分の前
記回路パターンをソルダーレジストで被覆する工程とを
含むことを特徴とする印刷配線板の製造方法。
A step of drilling a hole in a substrate with copper foil laminated on both sides and subjecting it to catalyst treatment, a step of depositing an etching resist on both the front and back sides of the substrate and etching away the exposed portion of the copper foil, forming a plating resist on the removed portion of the foil; depositing plating on the hole and the copper foil after removing the etching resist to form a through hole and a circuit pattern; 1. A method for manufacturing a printed wiring board, comprising the step of covering a circuit pattern with a solder resist.
JP27783588A 1988-11-01 1988-11-01 Manufacture of printed circuit board Pending JPH02122688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27783588A JPH02122688A (en) 1988-11-01 1988-11-01 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27783588A JPH02122688A (en) 1988-11-01 1988-11-01 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPH02122688A true JPH02122688A (en) 1990-05-10

Family

ID=17588928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27783588A Pending JPH02122688A (en) 1988-11-01 1988-11-01 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPH02122688A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57118694A (en) * 1981-01-16 1982-07-23 Toray Industries Print wiring and producing method
JPS61290797A (en) * 1985-06-19 1986-12-20 株式会社日立製作所 Manufacture of printed circuit board
JPS6221297A (en) * 1985-07-19 1987-01-29 日立化成工業株式会社 Manufacture of printed wiring board
JPS6355998A (en) * 1986-08-27 1988-03-10 キヤノン株式会社 Manufacture of high density printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57118694A (en) * 1981-01-16 1982-07-23 Toray Industries Print wiring and producing method
JPS61290797A (en) * 1985-06-19 1986-12-20 株式会社日立製作所 Manufacture of printed circuit board
JPS6221297A (en) * 1985-07-19 1987-01-29 日立化成工業株式会社 Manufacture of printed wiring board
JPS6355998A (en) * 1986-08-27 1988-03-10 キヤノン株式会社 Manufacture of high density printed wiring board

Similar Documents

Publication Publication Date Title
JP3786554B2 (en) Circuit board manufacturing method for forming fine structure layer on both sides of flexible film
JP3666955B2 (en) Method for manufacturing flexible circuit board
JPH05183259A (en) Manufacture of high density printed wiring board
JPH0710029B2 (en) Method for manufacturing laminated circuit board
JPH05259639A (en) Manufacture of printed wiring board
JPH08107263A (en) Manufacturing method of printed-wiring board
JPH02122688A (en) Manufacture of printed circuit board
JPH1117315A (en) Manufacture of flexible circuit board
JP3941463B2 (en) Manufacturing method of multilayer printed wiring board
JPH02122689A (en) Manufacture of printed circuit board
JP2000307217A (en) Forming method of wiring pattern and semiconductor device
JPH03225894A (en) Manufacture of printed wiring board
JPS62156898A (en) Manufacture of through-hole printed wiring board
JP3648753B2 (en) Wiring board manufacturing method
JPH1117331A (en) Manufacture of flexible circuit board
JP3817291B2 (en) Printed wiring board
JPH0563941B2 (en)
JPH0548246A (en) Manufacture of flexible printed circuit board
JPH02105494A (en) Printed wiring board and manufacture thereof
JP3688940B2 (en) Wiring pattern formation method for flexible circuit board
JPH05259609A (en) Manufacture of printed wiring board
JPH0567871A (en) Printed-wiring board and manufacture thereof
JP2000133914A (en) Printed wiring board and manufacture thereof
JPH03175695A (en) Manufacture of through hole printed wiring board
JPH10173315A (en) Printed-wiring board and manufacturing method thereof