JPH02122653A - Layer film for semiconductor element - Google Patents

Abstract

PURPOSE:To reduce occurrence of deficits or hillocks when compared with the case where a layer film is employed by employing insulation films having compressive film stress as two other insulation films sandwiching an SOG film. CONSTITUTION:In a layer film 108, SOG film is employed as a second insulation film 104 constituting an intermediate layer and silicon oxide films (SiO2 film) are employed as first and third insulation films 103, 105. The second insulation film 104 is formed by applying SOG film liquid through spin coating onto the surface of a first insulation film 203 then baking the film liquid under the temperature of 300-400 deg.C. The first and third insulation films, i.e., silicon oxide films, 203, 205 are formed through plasma CVD reaction between SiH4 gas and N2O gas. Consequently, compressive stress in the range of 10<8>-10<9>dyn/cm<2> is obtained and the thickness of film of about 3000Angstrom can be achieved. The compressive stress functions to cancel tensile stress of the SOG film and the inner stress is totally balanced in the layer film 108.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an interlayer film for semiconductor devices.

[Prior Art] An interlayer film for semiconductor elements (hereinafter simply referred to as an interlayer film) is used, for example, between a gate electrode and wiring of a semiconductor element such as an LSI,
Alternatively, it is a film interposed between wirings, which not only requires performance as an insulating film to ensure insulation between electrodes and wirings or between wirings, but also fills in four parts of an uneven base. Performance as so-called step coverage is also required to create a smooth surface.

Up until now, as an interlayer film with excellent step coverage performance, three insulating films have been laminated in order to form a three-layer structure, and the insulating film constituting the intermediate layer is a SOG film (Spin 0n class film). A method using the method has been proposed and introduced, for example, in Japanese Patent Application Laid-Open No. 193265/1983.

FIG. 2 is a cross-sectional view of one conventional example of a semiconductor device using an interlayer film described in the above-mentioned publication.

This semiconductor element has a multilayer wiring structure in which wiring is divided into two layers. First, a first wiring 20 is placed on an IC board 201.
2 in close contact with each other, then a first insulating film 203, a second insulating film 204, and a third insulating film 205 are formed in close contact with each other in this order on this wiring 202, and further, the third insulating film 205 is This is obtained by forming a second wiring 206 on top, and then forming a protective film 207 on top of this wiring 206, and the three-layer interlayer film 208 is formed by the first to third insulating films described above. is configured.

The first and second wirings 202 and 206 both use aluminum (A) as a conductive material.

Further, in the interlayer film 208, the second insulating film 20
4 is used as the SOG film, and the first insulating film 203 is
And the third insulating film 205 is a Schifcon oxide film (SiO
Z membrane) is used.

Here, the SOG film which is the second insulating film 204 is first
The deliquent is applied to the surface of the first insulating film 203 by a spin code method (a method of diffusing the deliquid removed into a film using centrifugal force caused by rotation), and then the applied deliquid is applied to the surface of the first insulation film 203. It is formed by firing the liquid at about 450°C.

Furthermore, the silicon oxide films that are the first and third insulating films 203 and 205 are formed by existing thin film techniques such as CVD (vapor phase growth) and sputtering.

In a semiconductor device having such a structure, the second wiring 20
The annealing process is performed twice: at the stage where the formation of the protective film 207 is completed (that is, before the formation of the protective film 207) and at the stage where the formation of the protective film 207 is completed.

This annealing treatment is a so-called heat treatment, with a temperature of 400 to 10
By heating to 00.degree. C., damage to the IC substrate 201 caused by ion implantation, formation of the interlayer film 208 described above, etc. is recovered.

[Problems to be Solved by the Invention] As mentioned above, the interlayer film 208, which has a three-layer structure in which the SOG film is sandwiched between two other insulating films, is very effective in flattening the unevenness of the underlying layer. It is an excellent and important technology.

However, in the above-mentioned interlayer film 208, for example, the third
In the case where the insulating film 205 is formed by atmospheric pressure CVD, defects such as defects and hillocks are likely to occur in the second wiring 206, and it is difficult to reduce the incidence of these defects. In general, there has been a problem in that it causes inconveniences such as a decrease in product yield and a decrease in reliability.

Here, "defect" refers to a phenomenon in which part or all of the line width of the wiring is cut out, and it occurs as if it were broken due to a tensile load, and "hillock" is a phenomenon in which a part of the wiring is raised. This phenomenon occurs like buckling due to compressive load. In other words, the action of an external force is indispensable for both defects and hillocks to occur.

Therefore, the fact that such defects are likely to occur means that the second wiring 206 is removed from the interlayer film 208 during the annealing process.
It is inferred that an external force is acting on the device that should cause the defect.

Therefore, as a first step to solving the above-mentioned problems, the inventors of the present application decided to first analyze and clarify the relationship between the internal stress characteristics of the interlayer film 208 and the above-mentioned defect occurrence rate.

In analyzing and elucidating the internal stress characteristics of the interlayer film 208, it was found that the SOG film contracts during formation (firing), and as a result, becomes an insulating film with tensile stress as film stress. .

Further, a third insulating film 20 formed by normal pressure CVD method
It was found that No. 5 also had tensile stress as membrane stress.

In view of these facts, the inventor of the present application has made the following considerations.

In the case where the third insulating film 205 is an interlayer film 208 formed by atmospheric pressure CVD, the tensile stress of the second insulating film 204, which is an SOG film, is stronger due to the tensile stress of the third insulating film 205. This causes a stronger external force to act on the second wiring 206, and as a result, defects such as breaks and hillocks are more likely to occur during annealing.

Therefore, by appropriately selecting the internal stress characteristics of the first and third insulating films sandwiching the SOG film, the stress characteristics of the interlayer film 208 as a whole can be set to an optimal state, thereby preventing the above-mentioned defects. can reduce the incidence of ” The present invention was obtained as a result of repeated experiments and investigations based on the above considerations, and it is possible to significantly reduce the incidence of defects, hillocks, etc. that occur in wiring etc. by annealing treatment. The purpose of the present invention is to provide an interlayer film for semiconductor devices that can be used.

[Means for Solving the Problems] The interlayer film for semiconductor devices according to the present invention has a three-layer structure with three insulating films laminated in sequence, and an SOG film is used as the insulating film constituting the intermediate layer. It is what was done.

However, as for the other two insulating films sandwiching the SOG film,
An insulating film whose film stress is compressive stress is used.

[Function] In a semiconductor device using the interlayer film for semiconductor devices according to the present invention, when wiring etc. adjacent to the interlayer film for semiconductor devices are observed, there are no defects or hillocks compared to when a conventional interlayer film is used. It can be confirmed that the incidence of this has been significantly reduced.

The reason why such an effect is obtained can be inferred as follows.

In the interlayer film for semiconductor devices according to the present invention, the two insulating films sandwiching the SOG film both have compressive stress as film stress, and these compressive stresses cancel out the tensile stress of the SOG film. As a result, the interlayer film as a whole becomes a stable film in which the internal stress is maintained in an equilibrium state, and no unreasonable external force is applied to the wiring or the like adjacent to the interlayer film.

Therefore, no strain is applied to adjacent wirings during annealing treatment, and as a result, it is possible to significantly reduce the incidence of defects such as wiring defects and hillocks.

[Example] FIG. 1 shows a cross section of a semiconductor device employing an interlayer film according to an example of the present invention.

This semiconductor element has a multilayer wiring structure in which the wiring is divided into two layers, and is obtained by sequentially passing through the following six steps from the first to the sixth steps.

In the first step, as shown in FIG. 1 <a>, the IC substrate 1
The first wiring 102 is closely formed on top of the first wiring 102.

In the second step, as shown in FIG. 1(b), the wiring 1
An interlayer film 108 according to an embodiment is formed on the film 02.

The interlayer film 108 of this example is obtained by sequentially closely forming a first insulating film 103, a second insulating film 104, and a third insulating film 105 on the wiring 102. It has a three-layer structure.

In the third step, as shown in FIG. 1C, a second wiring 106 is formed on the third insulating film 105.

In the fourth step, as shown in FIG.
(indicated by the symbol (a))).

In the fifth step, when the -th annealing process is completed, a protective film 107 is formed on the second wiring 106, as shown in FIG. 1(d).

In the sixth step, a second annealing process (indicated by the symbol (b) in the figure) is performed on the material after the fifth step.

By sequentially performing the above six steps, a semiconductor element having two layers of wiring can be obtained.

The first and second wirings 102 and 106 described above both use aluminum (A[) as a conductive material and are formed by known photolithography techniques (vapor deposition, phosphorography, etching, etc.).

In that case, the thickness of the wiring is about 6000 in each case. However, as the conductive material, metal materials such as aluminum alloy, copper, molybdenum, tungsten, silicides thereof, doped polysilicon, etc. may be used instead of the aluminum.

In the interlayer film 108 of the above embodiment, an SOG film is used for the second insulating film 104 constituting the intermediate layer, and the first
A silicon oxide film (SIO! film) is used for the insulating film 103 and the third insulating film +05.

Here, the SOG film which is the second insulating film 104 is first
Deliquor removal for SOG membrane (OCD type manufactured by Tokyo Ohka Co., Ltd.)
e2) to the first insulating film 203 using the spin code method.
, and then remove the applied liquid from 300 to 40
It is formed by firing at about 0'C.

Furthermore, the silicon oxide films that are the first and third insulating films 203 and 205 are both formed by reacting 5IH4 gas and N20 gas by plasma CVD (vapor phase epitaxy). 108~l as stress
It has a compressive stress of about ogdyn/cm', and the film thickness is about 30008.

In this case, the film forming conditions are as follows: The temperature of the base is 300-3
Approximately 80°C, RF current is 1. OA, pressure is 300mT
Make it orr. In addition, the supply flow rates of 5IH4 gas and N, O gas to obtain a silicon oxide film (5iOy film) are as follows:
Converted to normal pressure, S i It is 50c per minute.
In the case of c, N, and O, the rate is 1000cc per minute. Furthermore, the film growth rate is approximately 600 per minute.

Now, in the above semiconductor device, the interlayer film +08
In order to confirm the effect, after the second annealing process was completed, the density of defects and the density of hillocks occurring in the second wiring 106 were observed in comparison with those of the conventional product.

In this case, the hillock was observed at a wiring location with a line width of about 20 μm, and the defect was a space I with a line width of 4.5 μm.

Observation was made at a wiring location of approximately 8 μm.

The hillock occurrence density is 10.2 hillocks/mm in the case where the conventional interlayer film 208 is used, whereas it is 69 hillocks/1+ in the case where the interlayer film 108 of the above embodiment is used.
The number had decreased to 1,111.

Furthermore, the density of defects is 5.0 pieces/mm in the case where the conventional interlayer film 208 is used, whereas it is 1.5 pieces/mm in the case where the interlayer film 108 of the above embodiment is used. v
It had decreased to ++.

In this way, both hillocks and defects could be significantly reduced.

Although a specific comparison of numerical values is omitted, the first wiring 1
Similarly to the case of the second wiring 106, a reduction in the incidence of defects such as defects and hillocks was confirmed in 02.

The reason why the above effects are obtained has not been clearly established theoretically. However, as a result of the experimental results of the inventor of the present application and intensive research thereof, it is presumed that the effect can be obtained for the following reasons.

That is, in the interlayer film 108 of the above embodiment, S
Two insulating films 1 sandwiching a second insulating film 104 which is an OG film
03 and 105 both have compressive stress as film stress, and these compressive stresses act to cancel out the tensile stress of the SOG film, so that the internal stress of the interlayer film 108 as a whole reaches an equilibrium state. This results in a stable and maintained film, and no excessive external force is applied to the wiring or the like adjacent to the interlayer film 108.

Therefore, no stress is applied to the wiring 102, the wiring 106, etc. during annealing treatment, and as a result, the incidence of defects such as wiring defects and hillocks is significantly reduced.

Note that the first and third insulating films sandwiching the SOG film may have compressive stress as film stress (although the method for forming them is not limited to the plasma CVD method in one embodiment). For example, a sputtering method or a bias sputtering method can also be used.
For example, one insulating film is formed by a plasma CVD method and the other insulating film is formed by a sputtering method.
Different formation methods may be used for each insulating film.

Further, the materials of the first and third insulating films are not limited to those of the above embodiment. For example, in the above embodiment, the material of the first and third insulating films is 5iot, but it may be replaced with P-SiO, P-SiN, Si, N, PSG, or the like.

In addition, the interlayer film according to the present invention is used as an insulating film covering the surface of the wiring in a semiconductor element with a single wiring, although the above embodiment shows a case where it is used in a semiconductor element with a multilayer wiring structure. You may do so.

[Effects of the Invention] In a semiconductor device using the interlayer film for semiconductor devices according to the present invention, when wiring etc. adjacent to the interlayer film for semiconductor devices are observed, there are fewer defects compared to when a conventional interlayer film is used. It can be confirmed that the occurrence rate of hillocks has been significantly reduced.

The reason why such an effect is obtained can be inferred as follows.

In the interlayer film for semiconductor devices according to the present invention, the two insulating films sandwiching the SOG film both have compressive stress as film stress, and these compressive stresses cancel out the tensile stress of the SOG film. As a result, the interlayer film as a whole becomes a stable film in which the internal stress is maintained in an equilibrium state, and no unreasonable external force is applied to the wiring or the like adjacent to the interlayer film.

Therefore, no strain is applied to adjacent wirings during annealing treatment, and as a result, it is possible to significantly reduce the incidence of defects such as wiring defects and hillocks.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are explanatory diagrams of the manufacturing process of a semiconductor element using an interlayer film for semiconductor elements which is an embodiment of the present invention, and FIG. 1(a) is an explanation of the first process. Figure 1(b)
is an explanatory diagram of the second step, FIG. 1(C) is an explanatory diagram of the third and fourth steps, FIG. 1(d) is an explanatory diagram of the fifth and sixth steps, and FIG. FIG. 2 is an explanatory diagram of the structure of a semiconductor element using a conventional interlayer film. 101...IC board, 102...First
wiring, 103...first insulating film, 104...
...Second insulating film, +05...Third insulating film, 1
06...Second wiring, +07...Protective film, 108...Interlayer film (interlayer film for semiconductor element)
. Figure 201, Substrate Figure 2 Procedures Manual (self-proposal) September 27, 1989 E1 Director General of the Patent Office Yoshi [1 sentence Toshi Tsuyoshi 1, Indication of the case 1988 Patent Application No. 274526 2, Title of the invention Relationship with the case involving the person who made interlayer film for semiconductor devices 3ura 11 Masa Patent applicant address (105) 1-7-1 Toranomon, Minato-ku, Tokyo Name (
029) Oki Electric Industry Co., Ltd. Representative: Nobumitsu Kosugi 2-4, Agent address: 4-10-3-5 Shibaura, Minato-ku, Tokyo 108.
Subject of amendment (1) “Detailed Description of the Invention” column of the specification. 6. Contents of amendment (1) “400 to 100” in page 4, line 7 to line 8 of the specification
Correct "0℃" to "300℃~500℃". (2) "r203" on page 11, line 4 of the specification],
Correct it as 03 J. (3) r203.205J on page 11, line 7 of the specification [
Corrected to 103,105J. (4) Correct Figure 2 as shown in the attached sheet. Below

Claims (1)

[Claims] This is an interlayer film for semiconductors in which three insulating films are laminated in order to form a three-layer structure, and an SOG film is used as the insulating film constituting the middle layer, and two other insulating films sandwich the SOG film. An interlayer film for a semiconductor device, characterized in that an insulating film whose film stress is compressive stress is used as the film.