JPH04167547A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04167547A JPH04167547A JP29608490A JP29608490A JPH04167547A JP H04167547 A JPH04167547 A JP H04167547A JP 29608490 A JP29608490 A JP 29608490A JP 29608490 A JP29608490 A JP 29608490A JP H04167547 A JPH04167547 A JP H04167547A
- Authority
- JP
- Japan
- Prior art keywords
- film
- constituted
- interlayer insulating
- alloy
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000002844 melting Methods 0.000 claims abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 abstract description 11
- 229910000676 Si alloy Inorganic materials 0.000 abstract description 7
- 238000013508 migration Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 3
- 230000005012 migration Effects 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 22
- 239000004642 Polyimide Substances 0.000 description 9
- 239000010409 thin film Substances 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にポリイミドを層間絶縁
膜とする多層配線構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a multilayer wiring structure using polyimide as an interlayer insulating film.
電極配線材料としてはアルミニウム（Ａり薄膜あるいは
アルミニウム合金薄膜が用いられてきた。As an electrode wiring material, an aluminum (Al) thin film or an aluminum alloy thin film has been used.
半導体素子の高集積化にともない配線幅が小さくなるに
つれて、信頼性においてエレクトロマイグレーションや
ストレスマイグレーションなどの深刻な障害が生じてい
る。As the interconnect width becomes smaller as semiconductor devices become more highly integrated, serious reliability problems such as electromigration and stress migration are occurring.
この問題を解決するためＡ）薄膜あるいはＡ７合金薄膜
の上に萬融点シリサイド薄膜を形成した積層構造の配線
が用いられている。In order to solve this problem, A) a layered wiring structure in which a melting point silicide thin film is formed on a thin film or an A7 alloy thin film is used.
また半導体素子の高集積化にともない配線がチップに占
める面積の増大によって多層配線が必須となり、表面の
段差が大きくなる。Furthermore, as semiconductor devices become more highly integrated, the area occupied by wiring on a chip increases, making multilayer wiring essential and increasing the level difference on the surface.
したがって層間絶縁膜の平坦化が重要であり、量産に適
したポリイミドの開発が進められている。Therefore, planarization of the interlayer insulating film is important, and development of polyimide suitable for mass production is underway.
従来技術においては第３図に示すように、Ａ！薄膜ある
いはＡ１合金薄膜の上に高融点シリサイド薄膜を形成し
た積層配線８において、層間絶縁膜としてポリイミドを
塗布してから熱処理すると、シリサイドにクラック９が
生じたり、ＡｔあるいはＡ７合金からラテラルヒロック
１０が成長するという問題があった。In the prior art, as shown in FIG. 3, A! In a laminated wiring 8 in which a high melting point silicide thin film is formed on a thin film or an A1 alloy thin film, if polyimide is applied as an interlayer insulating film and then heat treated, cracks 9 may occur in the silicide, or lateral hillocks 10 may occur from At or A7 alloy. There was a problem with growing up.
本発明の半導体装置は、アルミニウム膜およびアルミニ
ウム合金膜のうち１つの上に高融点シリサイド膜を形成
した積層構造の下層配線の上に、さらに厚さ１００λ以
上の窒化シリコン膜および酸化シリコン膜のうち１つが
形成され、ポリイミドを層間絶縁膜とする多層配線を備
えたものである。The semiconductor device of the present invention is provided on a lower wiring of a laminated structure in which a high melting point silicide film is formed on one of an aluminum film and an aluminum alloy film, and one of a silicon nitride film and a silicon oxide film with a thickness of 100λ or more. One is formed and includes multilayer wiring using polyimide as an interlayer insulating film.
本発明の第１の実施例について、第１図（ａ）〜（ｅ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (e)
Explain with reference to.
はじめに第１図（ａ）に示すように、Ｐ型シリコン基板
１に、熱酸化により酸化膜２を形成し、ＣＶＤ法により
ＢＰＳＧ膜３を形成する。First, as shown in FIG. 1(a), an oxide film 2 is formed on a P-type silicon substrate 1 by thermal oxidation, and a BPSG film 3 is formed by CVD.
つぎに第１図（ｂ）に示すように、スパッタ法により圧
力１５ｍＴｏｒｒ１温度２００℃、ＲＦパワー５ｋＷの
条件で厚さ１．ＯｌｔｍのＡ１−１％Ｓｉ合金４および
厚さ０．１μｍのＷＳｉｘ５を順次堆積する。Next, as shown in FIG. 1(b), a thickness of 1.5 mm was formed by sputtering under the conditions of a pressure of 15 mTorr, a temperature of 200° C., and an RF power of 5 kW. Oltm Al-1% Si alloy 4 and WSix 5 with a thickness of 0.1 μm are sequentially deposited.
つぎに第１図（Ｃ）に示すように、フォトリソグラフィ
によりＷＳｉｘ５およびへ１−１％Ｓｉ合金４を選択エ
ツチングする。Next, as shown in FIG. 1C, WSix 5 and the 1-1% Si alloy 4 are selectively etched by photolithography.
つぎに第１図（ｄ）に示すように、プラズマＣＶＤ法に
よりＳｉＨ４およびＮＨ３の混合ガスの圧力０１ＩＴｏ
ｒ ｒｖ温度３００℃、ＲＦパワー１ｋＷの条件で厚
さ１５００人の窒化膜６を形成する。Next, as shown in FIG. 1(d), the pressure of the mixed gas of SiH4 and NH3 is 01ITo by plasma CVD method.
A nitride film 6 with a thickness of 1500 mm is formed under the conditions of r rv temperature of 300° C. and RF power of 1 kW.
つぎに第１図（ｅ）に示すように、層間絶縁膜としてポ
リイミド７を塗布してから４００℃、６０分の熱処理を
行なう。Next, as shown in FIG. 1(e), polyimide 7 is applied as an interlayer insulating film, and then heat treatment is performed at 400° C. for 60 minutes.
つぎに本発明の第２の実施例について、第２図（ａ）〜
（ｅ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (e).
はじめに第２図（ａ）に示すように、Ｐ型シリコン基板
１に、熱酸化により酸化膜２を形成し、ＣＶＤ法により
ＢＰＳＧ膜３を形成する。First, as shown in FIG. 2(a), an oxide film 2 is formed on a P-type silicon substrate 1 by thermal oxidation, and a BPSG film 3 is formed by CVD.
つぎに第２図（ｂ）に示すように、スパッタ法によりＡ
ノー１％Ｓｉ合金４およびＷＳｉｘ５を順次堆積する。Next, as shown in FIG. 2(b), A
No. 1% Si alloy 4 and WSix 5 are sequentially deposited.
つぎに第２図（Ｃ）に示すように、プラズマＣＶＤ法に
より窒化膜６を形成する。Next, as shown in FIG. 2(C), a nitride film 6 is formed by plasma CVD.
つぎに第２図（ｄ）に示すように、フォトリングラフィ
により窒化膜６、ＷＳｉｘ５、ＡＩ−１％Ｓｉ合金４を
選択エツチングする。Next, as shown in FIG. 2(d), the nitride film 6, WSix 5, and AI-1%Si alloy 4 are selectively etched by photolithography.
つぎに第２図（ｅ）に示すように、層間絶縁膜としてポ
リイミド７を塗布してから４００’Ｃ１６０分の熱処理
を行なう。Next, as shown in FIG. 2(e), polyimide 7 is applied as an interlayer insulating film, and then heat treatment is performed for 160 minutes at 400'C.
本実施例においては、ＷＳｉｘ５のクラック発生を抑制
する効果はあるが、パフ−１％Ｓｉ合金４のラテラルヒ
ロックを防止する効果はやや小さくなる。In this example, although there is an effect of suppressing the occurrence of cracks in WSix 5, the effect of preventing lateral hillocks in Puff-1% Si alloy 4 is slightly reduced.
ポリイミドを眉間絶縁膜とした多層配線においてＡＩま
たはＡ７合金の上にシリサイドを積層した配線の上に、
さらに厚さ１００Å以上のＳｉＮまたはＳｉＯ□保護膜
を備えている。In a multilayer wiring with polyimide as an insulating film between the eyebrows, on the wiring where silicide is laminated on AI or A7 alloy,
Furthermore, a SiN or SiO□ protective film with a thickness of 100 Å or more is provided.
そのためポリイミドを塗布したのち、熱処理を行なって
もシリサイドにクラックが生じたり、ＡＩまたはＡ１合
金からラテラルヒロックが成長することはなくなった。Therefore, even if heat treatment was performed after applying polyimide, cracks did not occur in the silicide, and lateral hillocks did not grow from the AI or A1 alloy.
エレクトロマイグレーションやストレスマイグレーショ
ンの対する耐性が向上した。Improved resistance to electromigration and stress migration.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を工程順
に示す断面図、第２図（ａ）〜（ｅ）は本発明の第２の
実施例を工程順に示す断面図、第３図は従来技術の問題
点を示す平面図である。
■・・・Ｐ型シリコン基板、２・・・酸化膜、３・・・
ＢＰＳＧＭ、４・・・Ａノー１％Ｓｉ合金、５・・・Ｗ
Ｓｉｘ１６・・・窒化膜、７・・・ポリイミド、８・・
・シリサイドとＡ１合金の積層配線、θ・・・シリサイ
ドに生したクラ、り、１０・・・Ａ１合金から成長した
ラテラルヒロック。FIGS. 1(a) to (e) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (e) are cross-sectional views showing the second embodiment of the present invention in the order of steps. 3 are plan views showing problems of the prior art. ■...P-type silicon substrate, 2...oxide film, 3...
BPSGM, 4...A no 1% Si alloy, 5...W
Six16...Nitride film, 7...Polyimide, 8...
・Laminated wiring of silicide and A1 alloy, θ...cracks and ri formed in silicide, 10...lateral hillocks grown from A1 alloy.
Claims (1)
上に高融点シリサイド膜を形成した積層構造の下層配線
の上に、さらに厚さ１００Å以上の窒化シリコン膜およ
び酸化シリコン膜のうち１つが形成され、ポリイミドを
層間絶縁膜とする多層配線を備えた半導体装置。One of a silicon nitride film and a silicon oxide film with a thickness of 100 Å or more is further formed on the lower wiring of the stacked structure in which a high melting point silicide film is formed on one of the aluminum film and the aluminum alloy film. A semiconductor device equipped with multilayer wiring as an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29608490A JPH04167547A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29608490A JPH04167547A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04167547A true JPH04167547A (en) | 1992-06-15 |
Family
ID=17828912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29608490A Pending JPH04167547A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04167547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100408767B1 (en) * | 2001-04-16 | 2003-12-11 | 미쓰비시덴키 가부시키가이샤 | Pressure sensitive device and method of manufacturing semiconductor substrate used therefor |
-
1990
- 1990-10-31 JP JP29608490A patent/JPH04167547A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100408767B1 (en) * | 2001-04-16 | 2003-12-11 | 미쓰비시덴키 가부시키가이샤 | Pressure sensitive device and method of manufacturing semiconductor substrate used therefor |
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